programmers may be used. The MX27C4000 supports
a intelligent fast programming algorithm which can result
in programming time of less than two minutes.
This EPROM is packaged in industry standard 32 pin
dual-in-line packages, 32 lead PLCC, 32 lead SOP, and
32 lead TSOP packages.
1
REV. 3.8, AUG. 26, 2003
P/N: PM00192
PIN CONFIGURATIONS
32 PDIP/SOP
32 PLCC
PIN DESCRIPTION
FEATURES
512K x 8 organization
Single +5V power supply
+12.5V programming voltage
Fast access time: 90/100/120/150 ns
Totally static operation
Completely TTL compatible
Operating current: 40mA
Standby current: 100uA
Package type:
- 32 pin plastic DIP
- 32 pin PLCC/SOP
- 32 pin TSOP
GENERAL DESCRIPTION
The MX27C4000 is a 5V only, 4M-bit, One Time
Programmable Read Only Memory. It is organized as
512K words by 8 bits per word, operates from a single
+5 volt supply, has a static standby mode, and features
fast single address location programming. All program-
ming signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM
BLOCK DIAGRAM
32 TSOP
SYMBOL
PIN NAME
A0~A18
Address Input
Q0~Q7
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
VPP
Program Supply Voltage
VCC
Power Supply Pin (+5V)
GND
Ground Pin
MX27C4000
4M-BIT [512K x8] CMOS EPROM
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q7
CE
OE
A0~A18
ADDRESS
INPUTS
Y-DECODER
X-DECODER
Y-SELECT
4M BIT
CELL
MAXTRIX
VCC
VSS
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
MX27C4000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
1
4
5
9
13
14
17
20
21
25
29
32
30
A14
A13
A8
A9
A11
OE
A10
CE
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
A12
A15
A16
VPP
VCC
A18
A17
MX27C4000
A11
A9
A8
A13
A14
A17
A18
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX27C4000
2
MX27C4000
REV. 3.8, AUG. 26, 2003
P/N: PM00192
FUNCTIONAL DESCRIPTION
THE PROGRAMMING OF THE MX27C4000
When the MX27C4000 is delivered, or it is erased, the
chip has all 4M bits in the "ONE" or HIGH state.
"ZEROs" are loaded into the MX27C4000 through the
procedure of programming.
For programming, the data to be programmed is applied
with 8 bits in parallel to the data pins.
Vcc must be applied simultaneously or before Vpp, and
removed simultaneously or after Vpp. When
programming an MXIC EPROM, a 01uF capacitor is
required across Vpp and ground to suppress spurious
voltage transients which may damage the device.
FAST PROGRAMMING
The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 100us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V
10%.
PROGRAM INHIBIT MODE
Programming of multiple MX27C4000s in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C4000 may be common. A
TTL low-level program pulse applied to an MX27C4000
CE input with VPP = 12.5
0.5 V and CE LOW will
program that MX27C4000. A high-level CE input inhibits
the other MX27C4000s from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE and CEat
VIL, and VPP at its programming voltage.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25
C
5
C ambient
temperature range that is required when programming
the MX27C4000.
To activate this mode, the programming equipment
must force 12.0
0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C4000, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB (Q7)
defined as the parity bit.
READ MODE
The MX27C4000 has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - tOE.
STANDBY MODE
The MX27C4000 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC
0.3 V.
The MX27C4000 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
3
MX27C4000
REV. 3.8, AUG. 26, 2003
P/N: PM00192
NOTES:
1. VH = 12.0 V
0.5 V
2. X = Either VIH or VIL
3. A1 - A8 = A10 - A18 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during programming.
MODE SELECT TABLE
PINS
MODE
CE
OE
A0
A9
VPP
OUTPUTS
Read
VIL
VIL
X
X
VCC
DOUT
Output Disable
VIL
VIH
X
X
VCC
High Z
Standby (TTL)
VIH
X
X
X
VCC
High Z
Standby (CMOS)
VCC
0.3V
X
X
X
VCC
High Z
Program
VIL
VIH
X
X
VPP
DIN
Program Verify
VIH
VIL
X
X
VPP
DOUT
Program Inhibit
VIH
VIH
X
X
VPP
High Z
Manufacturer Code(3)
VIL
VIL
VIL
VH
VCC
C2H
Device Code(3)
VIL
VIL
VIH
VH
VCC
40H
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
PDF 
ZIP
