FEATURES

With Page Mode function, 8-word/16-byte page

512K x 8 or 256K x 16 organization

+12.5V programming voltage

Fast access time: 90/100/120/150 ns

Page mode access time 50/60/75 ns

Totally static operation

Completely TTL compatible

Operating current: 60mA

Standby current: 100uA

Package type:

- 40 pin plastic DIP
- 40 pin SOP

REV. 2.7, NOV. 19, 2002

P/N: PM0239

PIN CONFIGURATIONS

PDIP/SOP

BLOCK DIAGRAM

GENERAL DESCRIPTION

The MX27C4111 is a 4M-bit, One Time Programmable
Read Only Memory with page mode. It is organized as
512K x 8 or 256K x 16, operates from a single + 5 volt
supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For
programming outside from the system, existing EPROM
programmers may be used. The MX27C4111 supports
a intelligent fast programming algorithm which can result
in programming time of less than two minutes.

MX27C4111 provides Page Read Access Mode which
can greatly reduce the read access time. Normal read
access time and Page Mode read access time is as fast
as 90/50ns. It is designed to be compatible with all
microprocessors and similar applications in which high
perofmrance, large bit storage and simple interfacing
are important design considerations.

This EPROM is packaged in industry standard 40 pin
dual-in-line packages and 40 pin SOP packages.

MX27C4111

PRELIMINARY

4M-BIT [512K x8/256K x16] CMOS EPROM

WITH PAGE MODE

MX27C4111

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

A17

A7
A6
A5
A4
A3
A2
A1
A0

GND

Q0
Q8
Q1
Q9
Q2

Q10

Q11

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q14

Q15/A-1

BYTE/VPP

A0~A17

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-SELECT

4M BIT

CELL

MAXTRIX

VCC

GND

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

WORD MODE(BYTE = VCC)

Q15/A-1

MODE

Q0-Q14

SUPPLY CURRENT

High Z

Non selected

High Z

Standby(ICC2)

High Z

Non selected

High Z

Operating(ICC1)

DOUT

Selected

DOUT

Operating(ICC1)

NOTE : X = H or L

PIN DESCRIPTION

SYMBOL

PIN NAME

A0~A17

Address Input

Q0~Q14

Data Input/Output

Chip Enable Input

Output Enable Input

BYTE/VPP Word/Byte Selection/Program Supply

Voltage

Q15/A-1

Q15(Word mode)/LSB addr. (Byte

mode)

VCC

Power Supply Pin (+5V)

GND

Ground Pin

TRUTH TABLE OF BYTE FUNCTION

BYTE MODE(BYTE = GND)

Q15/A-1

MODE

Q0-Q7

SUPPLY CURRENT

Non selected

High Z

Standby(ICC2)

Non selected

High Z

Operating(ICC1)

A-1 input

Selected

DOUT

Operating(ICC1)

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C4111

When the MX27C4111 is delivered, or it is erased, the
chip has all 4M bits in the "ONE" or HIGH state. "ZEROs"
are loaded into the MX27C4111 through the procedure
of programming.

For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.

VCC must be applied simultaneously or before VPP,
and removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and OE = VIH (Algorithm is shown in
Figure 1). The programming is achieved by applying a
single TTL low level 100us pulse to the CE input after
addresses and data line are stable. If the data is not
verified, an additional pulse is applied for a maximum of
25 pulses. This process is repeated while sequencing
through each address of the device. When the
programming mode is completed, the data in all address
is verified at VCC = VPP = 5V

10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C4111's in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C4111 may be common. A
TTL low-level program pulse applied to an MX27C4111
CE input with VPP = 12.5

0.5 V will program the

MX27C4111. A high-level CE input inhibits the other
MX27C4111s from being programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE at VIL, CE
at VIH, and VPP at its programming voltage.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25

C ambient

temperature range that is required when programming
the MX27C4111.

To activate this mode, the programming equipment
must force 12.0

0.5 V on address line A9 of the device.

Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C4111, these two identifier bytes are given in the
Mode Select Table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.

READ MODE

The MX27C4111 provides page mode with 8 words/16
bytes per page. In order to get the benefit of fast page
read, the user should keep chip enable(CE) low and
toggle address A0~A2 in word mode or A-1~A2 in byte
mode. Page Read access time(tPA) is equal to the
delay from address stable to data output. It is twice as
fast as normal tACC and is highly recommended.

WORD-WIDE MODE

With BYTE/VPP at VCC

0.2V outputs Q0-7 present

data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.

BYTE-WIDE MODE

With BYTE/VPP at GND

0.2V, outputs Q8-15 are tri-

stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

STANDBY MODE

The MX27C4111 has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC

0.3 V.

The MX27C4111 also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-
line control function is provided to allow for:

1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and

connected to the READ line from the system control
bus. This assures that all deselected memory devices
are in their low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.

MODE SELECT TABLE

BYTE/

MODE

Q15/A-1

VPP(5)

Q8-14

Q0-7

Read (Word)

VIL

Q15 Out

VCC

Q8-14 Out

Q0-7 Out

Read (Upper Byte)

VIL

VIH

GND

High Z

Q8-15 Out

Read (Lower Byte)

VIL

GND

High Z

Q0-7 Out

Output Disable

VIL

VIH

High Z

Standby

VIH

High Z

Program

VIL

VIH

Q15 In

VPP

Q8-14 In

Q0-7 In

Program Verify

VIH

VIL

Q5 Out

VPP

Q8-14 Out

Q0-7 Out

Program Inhibit

VIH

High Z

VPP

High Z

Manufacturer Code(3)

VIL

VCC

00H

C2H

Device Code(3)

VIL

VIH

VCC

38H

00H

NOTES:
1.VH = 12.0V

0.5V

2.X = Either VIH or VIL
3.A1 - A8, A10 - A17 = VIL (For auto select)
4.See DC Programming Characteristics for VPP

voltages.

5.BYTE/VPP is intended for operation under DC

Voltage conditions only.

6.Manufacture code = 00C2H

Device code = B800H

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

SWITCHING TEST CIRCUITS

SWITCHING TEST WAVEFORMS

DEVICE

UNDER

TEST

DIODES = IN3064

OR EQUIVALENT

CL = 100 pF including jig capacitance

6.2K ohm

1.8K ohm

+5V

2.0V

0.8V

TEST POINTS

INPUT

2.0V

0.8V

OUTPUT

AC TESTING:

AC driving levels

AC driving levels are 2.4V/0.4V.

Input pulse rise and fall times are < 20ns.

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

C to 70

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to VCC + 0.5V

VCC to Ground Potential

-0.5V to 7.0V

A9 & VPP

-0.5V to 13.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended period may affect reliability.

NOTICE:
Specifications contained within the following tables are sub-
ject to change.

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

AC CHARACTERISTICS

27C4111-90 27C4111-10

27C4111-12

27C4111-15

Symbol PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN. MAX.

MIN.

MAX. UNIT CONDITIONS

tACC

Address to Output Delay

100

120

150

CE = OE = VIL

tCE

Chip Enable to Output Delay

100

120

150

OE = VIL

tPA

Page Address to Output Delay

CE = OE =VIL

tOE

Output Enable to Output Delay

CE = VIL

tDF

OE High to Output Float,

or CE High to Output Float

tOH

Output Hold from Address,

CE or OE which ever occurred first

tBHA

BYTE Access Time

100

120

150

tOHB

BYTE Output Hold Time

tBHZ

BYTE Output Delay Time

tBLZ

BYTE Output Set Time

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.4mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.3

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

ILO

Output Leakage Current

-10

VOUT = 0 to 5.5V

ICC3

VCC Power-Down Current

100

CE = VCC

0.3V

ICC2

VCC Standby Current

1.5

CE = VIH

ICC1

VCC Active Current

CE = VIL, f=5MHz, Iout = 0mA

IPP

VPP Supply Current Read

CE = OE = VIL, VPP = 5.5V

CAPACITANCE

TA = 25

C, f = 1.0 MHz (Sampled only)

SYMBOL

PARAMETER

TYP.

MAX.

UNIT

CONDITIONS

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

CVPP

VPP Capacitance

VPP = 0V

MX27C4111

-90

-10

-12

-15

Operating Temperature Commercial

C to 70

C 0

C to 70

Vcc POwer Supply

5V ± 5%

10%

DC/AC Operating Condition for Read Operation

MX27C4111

REV. 2.7, NOV. 19, 2002

P/N: PM0239

DC PROGRAMMING CHARACTERISTICS

TA = 25

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.40mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.3

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

A9 Auto Select Voltage

11.5

12.5

ICC3

VCC Supply Current (Program & Verify)

IPP2

VPP Supply Current(Program)

CE = VIL, OE = VIH

VCC1

Fast Programming Supply Voltage

6.00

6.50

VPP1

Fast Programming Voltage

12.5

13.0

AC PROGRAMMING CHARACTERISTICS

TA = 25

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

tAS

Address Setup Time

2.0

tOES

OE Setup Time

2.0

tDS

Data Setup Time

2.0

tAH

Address Hold Time

tDH

Data Hold Time

2.0

tDFP

Chip Enable to Output Float Delay

130

tVPS

BYTE/VPP Setup Time

2.0

tPW

CE initial Program Pulse Width

105

tVCS

VCC Setup Time

2.0

tOE

Data valid from OE

150

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