P/N: PM0515

FEATURES

· 5.0V

10% for read, erase and write operation

· 131072x8 only organization
· Fast access time: 90/120ns
· Low power consumption

- 30mA maximum active current(5MHz)
- 1u

typical standby current

· Command register architecture

- Byte Programming (7us typical)
- Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte
x 2, 32K-Byte x 1, and 64K-Byte x 1)

· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically programs and verifies data at
specified address

· Erase Suspend/Erase Resume

Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.

· Status Reply

- Data polling & Toggle bit for detection of program
and erase cycle completion.

· Chip protect/unprotect for 5V only system or 5V/12V

system

· 100,000 minimum erase/program cycles
· Latch-up protected to 100mA from -1 to VCC+1V
· Boot Code Sector Architecture

- T = Top Boot Sector
- B = Bottom Boot Sector

· Low VCC write inhibit is equal to or less than 3.2V
· Package type:

- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP

· Boot Code Sector Architecture

- T=Top Boot Sector
- B=Bottom Boot Sector

· 20 years data retention

GENERAL DESCRIPTION

The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's
Flash memories offer the most cost-effective and
reliable read/write non-volatile random access
memory. The MX29F001T/B is packaged in 32-pin
PLCC, TSOP, PDIP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.

The standard MX29F001T/B offers access time
90ns. To eliminate bus contention, the MX29F001T/
B has separate chip enable (CE) and output enable
(OE) controls.

MXIC's Flash memories augment EPROM function-
a l i t y w i t h i n - c i r c u i t e l e c t r i c a l e r a s u r e a n d
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs
and fixed power supply levels during erase and

programming, while maintaining maximum EPROM
compatibility.

MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
o p e r a t i o n s p r o d u c e s r e l i a b l e c y c l i n g . T h e
MX29F001T/B uses a 5.0V

10% VCC supply to

perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.

MX29F001T/B

1M-BIT [128K x 8] CMOS FLASH MEMORY

REV. 2.6, DEC. 29, 2003

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

PIN CONFIGURATIONS

32 TSOP (TYPE 1)

PIN DESCRIPTION:

(NORMAL TYPE)

SECTOR STRUCTURE

MX29F001T Sector Architecture

MX29F001B Sector Architecture

SYMBOL

PIN NAME

A0~A16

Address Input

Q0~Q7

Data Input/Output

Chip Enable Input

Write Enable Input

Output Enable Input

VCC

Power Supply Pin (+5V)

GND

Ground Pin

MX29F001T/B

A16

A15

A12

GND

VCC

A14

A13

A11

A10

A14

A13

A11

A10

GND

A12

A15

A16

VCC

MX29F001T/B

A11

A9
A8

A13
A14

VCC

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

MX29F001T/B

8 K - B Y T E

0 0 0 0 0 H

6 4 K - B Y T E

3 2 K - B Y T E

8 K - B Y T E

4 K - B Y T E

1 F F F F H

0 F F F F H

0 5 F F F H

0 2 F F F H

0 1 F F F H

0 3 F F F H

A 1 6 ~ A 0

0 7 F F F H

6 4 K - B Y T E

0 0 0 0 0 H

8 K - B Y T E

4 K - B Y T E

8 K - B Y T E

3 2 K - B Y T E

1 F F F F H

1 D F F F H

1 C F F F H

1 9 F F F H

1 7 F F F H

0 F F F F H

1 B F F F H

A 1 6 ~ A 0

32 PLCC

32 PDIP

REV. 2.6, DEC. 29, 2003

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MX29F001T/B

AUTOMATIC PROGRAMMING

The MX29F001T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Program-
ming algorithm does not require the system to time out
or verify the data programmed. The typical chip pro-
gramming time of the MX29F001T/B at room tempera-
ture is less than 3.5 seconds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 3 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled within the device.

AUTOMATIC SECTOR ERASE

The MX29F001T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally con trolled by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provides feed-
back to the user as to the status of the programming
operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches addresses and data needed for the pro-
gramming and erase operations. During a system write
cycle, addresses are latched on the falling edge, and
data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F001T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

REV. 2.6, DEC. 29, 2003

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MX29F001T/B

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Cycle Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr Data

Addr

Data

Reset

XXXH

F0H

Read

Read Silicon ID

555H

AAH

2AAH

55H

555H

90H

ADI

DDI

Chip Protect Verify

555H

AAH

2AAH

55H

555H

90H

(SA)

00H

X02H

01H

Program

555H

AAH

2AAH

55H

555H A0H

Chip Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH 55H 555H 10H

Sector Erase

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH 55H

SA 30H

Sector Erase Suspend 1

XXXH

B0H

Sector Erase Resume

XXXH

30H

Unlock for chip

555H

AAH

2AAH

55H

555H

80H

555H

AAH

2AAH 55H

555H 20H

protect/unprotect

TABLE 1. SOFTWARE COMMAND DEFINITIONS

Note:
1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to

Table 3)
DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.

Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A16 in either state.

4. For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data

is 00H, it means the chip is still not being protected.

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register

command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).

REV. 2.6, DEC. 29, 2003

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MX29F001T/B

Pins

Q0 ~ Q7

Mode

Read Silicon ID

(2)

C2H

Manufacturer Code(1)

Read Silicon ID

(2)

18H/19H

Device Code(1)

Read

OUT

Standby

HIGH Z

Output Disable

HIGH Z

Write

(3)

Chip Protect with 12V

(2)

system(6)

Chip Unprotect with 12V

(2)

system(6)

Verify Chip Protect

(2)

Code(5)

with 12V system

Chip Protect without 12V

system (6)

Chip Unprotect without 12V

system (6)

Verify Chip Protect/Unprotect

Code(5)

without 12V system (7)

Reset

HIGH Z

TABLE 2. MX29F001T/B BUS OPERATION

NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.

Code=01H means protected.

6. Refer to chip protect/unprotect algorithm and waveform.

Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system"
command.

7. The "verify chip protect/unprotect without 12V system" is only following "Chip protect/unprotect without 12V

system" command.

REV. 2.6, DEC. 29, 2003

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MX29F001T/B

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The de-
vice remains enabled for reads until the command regis-
ter contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design prac-
tice.

The MX29F001T/B contains a Silicon-ID-Read operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the read sili-
con ID command sequence into the command register.
Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 18H for MX29F001T,19H for MX29F001B.

Pins

Code (Hex)

Code

Manufacture code

VIL

C2H

Device code

VIH

VIL

18H

for MX29F001T

Device code

VIH

VIL

19H

for MX29F001B

Chip Protection Verification

VIH

01H (Protected)

VIH

00H (Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

SET-UP AUTOMATIC CHIP ERASE COM-
MANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verification begin. The
erase and verification operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system does not require to pro-
vide any control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verify command is required).

If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating an erase operation exceed
internal timing limit.

The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.

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MX29F001T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Set-up Sector Erase command and Automatic
Sector Erase command. Upon executing the Automatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verifi-
cation begin. The erase and verification operations are
complete when the data on Q7 is "1" and the data on Q6
stops toggling for two consecutive read cycles, at which
time the device returns to the Read mode. The system
does not require to provide any control or timing during
these operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector erase
is a six-bus cycle operation. There are two "unlock" write
cycles. These are followed by writing the set-up com-
mand 80H. Two more "unlock" write cycles are then fol-
lowed by the sector erase command 30H. The sector
address is latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE. Sec-
tor addresses selected are loaded into internal register
on the sixth falling edge of WE. Each successive sector
load cycle started by the falling edge of WE must begin
within 30us from the rising edge of the preceding WE.
Otherwise, the loading period ends and internal auto sec-
tor erase cycle starts. (Monitor Q3 to determine if the
sector erase timer window is still open, see section Q3,
Sector Erase Timer.) Any command other than Sector
Erase (30H) or Erase Suspend (B0H) during the time-out
period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. Writing the Erase Suspend com-
mand during the Sector Erase time-out immediately ter-
minates the time-out immediately terminates the time-
out period and suspends the erase operation. After this
command has been executed, the command register will
initiate erase suspend mode. The state machine will re-
turn to read mode automatically after suspend is ready.
At this time, state machine only allows the command
register to respond to the Read Memory Array, Erase
Resume and Program commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.

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MX29F001T/B

Status

Byte Program in Auto Program Algorithm

Toggle

N/A

In Progress

Auto Erase Algorithm

Toggle

Erase Suspended Mode

Erase Suspend Read

Data

Erase Suspend Program

Toggle

N/A

(Non-Erase Suspended Sector)

(Note1)

Byte Program in Auto Program Algorithm

Toggle

N/A

Exceeded

Erase in Auto Erase Algorithm

Toggle

Time Limits

Erase Suspended Mode

Erase Suspend Program

Toggle

N/A

(Non-Erase Suspended Sector)

Table 4. Write Operation Status

Note:
1. Performing successive read operations from any address will cause Q6 to toggle.

REV. 2.6, DEC. 29, 2003

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MX29F001T/B

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.

Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising edge
of the WE pulse. The rising edge of WE also begins the
programming operation. The system does not require to
provide further controls or timings. The device will auto-
matically provide an adequate internally generated pro-
gram pulse and verify margin.

If the program operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode
(no program verify command is required).

WRITE OPERATION STATUS

TOGGLE BIT-Q6

The MX29F001T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.

While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in Q6 toggling between one and zero.
Once the Automatic Program or Erase algorithm is com-
pleted, Q6 will stop toggling and valid data will be read.
The toggle bit is valid after the rising edge of the sixth

WE pulse of the six write pulse sequences for chip/sec-
tor erase.

The Toggle Bit feature is active during Automatic Pro-
gram/Erase algorithms or sector erase time-out. (see
section Q3 Sector Erase Timer)

DATA POLLING-Q7

The MX29F001T/B also features Data Polling as a
method to indicate to the host system that the Auto-
matic Program or Erase algorithms are either in progress
or completed.

While the Automatic Programming algorithm is in opera-
tion, an attempt to read the device will produce the comple-
ment data of the data last written to Q7. Upon comple-
tion of the Automatic Program Algorithm an attempt to
read the device will produce the true data last written to
Q7. The Data Polling feature is valid after the rising edge
of the fourth WE pulse of the four write pulse sequences
for automatic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE pulse of six write pulse sequences
for automatic chip/sector erase.

The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm or sector erase time-out.(see sec-
tion Q3 Sector Erase Timer)

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MX29F001T/B

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not suc-
cessfully completed. Data Polling and Toggle Bit are the
only operating functions of the device under this condi-
tion.

If this time-out condition occurs during sector erase op-
eration, it is specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sec-
tors. Write the Reset command sequence to the device,
and then execute program or erase command sequence.
This allows the system to continue to use the other ac-
tive sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.

If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be re-
used, (other sectors are still functional and can be re-
used).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.

Q3
Sector Erase Timer

After the completion of the initial sector erase command
sequence the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept addi-
tional sector erase commands. To insure the command
has been accepted, the system software should check
the status of Q3 prior to and following each subsequent
sector erase command. If Q3 were high on the second
status check, the command may not have been accepted.

DATA PROTECTION

The MX29F001T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory con-
tents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.

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MX29F001T/B

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND. (Using a 10uF bulk capacitor
connected for high current condition is available if nec-
essary.)

CHIP PROTECTION WITH 12V SYSTEM

The MX29F001T/B features hardware chip protection.
Which will disable both program and erase operations.
To activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (sug-
gest VID=12V) A6=VIL and CE=VIL.(see Table 2) Pro-
gramming of the protection circuitry begins on the falling
edge of the WE pulse and is terminated with the rising
edge of the same. Please refer to chip protect algorithm
and waveform.

To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH. When A1=1, it
will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the ad-
dress, except for A1, are don't care. Address locations
with A1 = VIL are reserved to read manufacturer and
device codes.(Read Silicon ID)

It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command. Per-
forming a read operation with A1=VIH, it will produce a
logical "1" at Q0 for the protected status.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F001T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect completion to incorporate any changes in the
code.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and wave-
form for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

CHIP PROTECTION WITHOUT 12V SYSTEM

The MX29F001T/B also feature a hardware chip protec-
tion method in a system without 12V power supply. The
programming equipment do not need to supply 12 volts
to protect all sectors. The details are shown in chip pro-
tect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F001T/B also feature a hardware chip
unprotection method in a system without 12V power sup-
ply. The programming equipment do not need to supply
12 volts to unprotect all sectors. The details are shown
in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

The MX29F001T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command se-
quences.

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

C to 70

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to 7.0V

VCC to Ground Potential

-0.5V to 7.0V

A9 & OE

-0.5V to 13.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and
functional operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended period may affect reliability.

NOTICE:
Specifications contained within the following tables are
subject to change.

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

VIN = 0V

CIN2

Control Pin Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS

VCC = 5V

10%

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = GND to VCC

ILO

Output Leakage Current

VOUT = GND to VCC

ISB1

Standby VCC current

CE = VIH

ISB2

CE = VCC + 0.3V

ICC1

Operating VCC current

IOUT = 0mA, f=5MHz

ICC2

IOUT = 0mA, f=10MHz

VIL

Input Low Voltage

-0.3(NOTE 1)

0.8

VIH

Input High Voltage

2.0

VCC + 0.3

VOL

Output Low Voltage

0.45

IOL = 2.1mA

VOH1

Output High Voltage(TTL)

2.4

IOH = -2mA

VOH2

Output High Voltage(CMOS)

VCC-0.4

IOH = -100uA

VCC=VCC MIN

NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

CAPACITANCE

TA = 25

C, f = 1.0 MHz

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

AC CHARACTERISTICS

VCC = 5V

10%

NOTE:

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

· Input pulse levels: 0.45V/2.4V

· Input rise and fall times: <10ns

· Output load: 1 TTL gate + 100pF (Including scope and

jig)

· Reference levels for measuring timing : 0.8V & 2.0V

29F001T/B-90

29F001T/B-12

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

CONDITIONS

tACC

Address to Output Delay

120

CE=OE=VIL

tCE

CE to Output Delay

120

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note1)

CE=VIL

tOH

Address to Output hold

CE=OE=VIL

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ICC1 (Read)

Operating VCC Current

IOUT=0mA, f=5MHz

ICC2

IOUT=0mA, F=10MHz

ICC3 (Program)

In Programming

ICC4 (Erase)

In Erase

ICCES

VCC Erase Suspend Current

CE=VIH, Erase Suspended

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

NOTES:
1. VIL min. = -0.6V for pulse width < 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

READ TIMING WAVEFORMS

A0~16

tACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z

DATA Valid

tOE

tDF

tCE

DATA

Q0~7

tOH

ADD Valid

DC CHARACTERISTICS

VCC = 5V

10%

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

29F001T/B-90

29F001T/B-12

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

tOES

OE setup time

tCWC

Command programming cycle

120

tCEP

WE programming pulse width

tCEPH1

WE programming pulse width High

tCEPH2

WE programming pulse width High

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

tCESC

CE setup time before command write

tDF

Output disable time (Note 1)

tAETC

Total erase time in auto chip erase

3(TYP.)

tAETB

Total erase time in auto sector erase

1(TYP.)

tAVT

Total programming time in auto verify

210

tBAL

Sector address load time

100

tCH

CE Hold Time

tCS

CE setup to WE going low

tVLHT

Voltage Transition Time

tOESP

OE Setup Time to WE Active

tWPP

Write pulse width for chip protect

tWPP2

Write pulse width for chip unprotect

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

AC CHARACTERISTICS

VCC = 5V

10%

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

One byte data is programmed. Verification in fast
algorithm and additional programming by external control
are not required because these operations are executed
automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle bit

AUTOMATIC PROGRAMMING TIMING WAVEFORM

checking after automatic verify starts. Device outputs
DATA during programming and DATA after programming
on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,
timing waveform)

tCWC

tAS

tCEP

tDS

tDH

tDF

Vcc 5V

Q0~Q2

,Q4(Note 1)

A11~A16

tCEPH1

tAH

ADD Valid

tCESC

Command In

ADD Valid

A0~A10

Command In

Data In

DATA

Command In

Data In

DATA

tAVT

tOE

DATA polling

2AAH

555H

Command #AAH

Command #55H

Command #A0H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

matic erase starts. Device outputs 0 during erasure and
1 after erasure 0n Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)

All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA polling and toggle bit checking after auto

AUTOMATIC CHIP ERASE TIMING WAVEFORM

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A16

tCEPH1

tAH

Command In

A0~A10

Command In

tAETC

DATA polling

2AAH

555H

Command #AAH

Command #55H

Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H

2AAH

555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

AUTOMATIC CHIP ERASE TIMING WAVEFORM

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector data indicated by A13 to A16 are erased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit

checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

tAH

Sector

Address0

555H

2AAH

555H

Sector

Address1

Sector

Addressn

Vcc 5V

Q0,Q1,

Q4(Note 1)

A13~A16

A0~A10

Command

Command #30H

Command #55H

Command #AAH

Command #80H

Command #55H

Command #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

-1.0V

13.5V

Input Voltage with respect to GND on all I/O pins

-1.0V

Vcc + 1.0V

Current

-100mA

+100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

Chip Erase Time

Byte Programming Time

210

Chip Programming Time

3.5

10.5

sec

Erase/Program Cycles

100,000

Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE (1)

Note:

1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25

C, 5V.

3.Maximum values measured at 25

C, 4.5V.

PARAMETER

MIN.

UNIT

Data Retention Time

Years

DATA RETENTION

REV. 2.6, DEC. 29, 2003

P/N: PM0515

MX29F001T/B

Revision

Description

Page

Date

2.0

1. To remove "Advanced Information" data sheet marking and

DEC/21/1999

contain information on products in full production
2.The modification summary from Revision 0.0 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles

P1,38

2-2.To add data retention 20 years

P1,38

2-3.To remove A9 from the timing waveform of protection/

P32,33

unprotection without 12V
2-4.Multi-sector erase time out:80ms-->30us

2-5.tBAL:80us-->100us

P16,17

2.1

To modify "Package Information"

P39~41

JUN/14/2001

2.2

To corrected typing error

All

JUL/01/2002

2.3

1. Add industrial grade spec

P13,38

JUL/09/2002

2. Modify maximum value measurement temperature from 25

C to 85

C P37

2.4

1. Remove industrial grade spec

P13,37,38

AUG/12/2002

2.5

1. To modify Package Information

P39~41

NOV/20/2002

2.6

1. Removed 55ns/70ns specification

P1,13~18,37 DEC/29/2003

REVISION HISTORY

MX29F001T/B

ACRONIX

NTERNATIONAL

O.,

TD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

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TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

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Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

ACRONIX

MERICA,

NC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

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