GENERAL DESCRIPTION

The MX29F002T/B is a 2-mega bit Flash memory organ-
ized as 256K bytes of 8 bits only. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29F002T/B is
packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is
designed to be reprogrammed and erased in-system or in-
standard EPROM programmers.

The standard MX29F002T/B offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F002T/B has separate chip enable (CE) and output
enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F002T/B uses a command register to manage this
functionality. The command register allows for 100% TTL
level control inputs and fixed power supply levels during
erase and programming, while maintaining maximum
EPROM compatibility.

FEATURES

262,144x 8 only

Fast access time: 55/70/90/120ns

Low power consumption

- 30mA maximum active current(5MHz)

- 1uA typical standby current

Programming and erasing voltage 5V ± 10%

Command register architecture

- Byte Programming (7us typical)

- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte

x1, and 64K-Byte x 3)

Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors or the

whole chip with Erase Suspend capability.

- Automatically programs and verifies data at specified

address

Erase Suspend/Erase Resume

- Suspends an erase operation to read data from, or

program data to, a sector that is not being erased, then

resumes the erase operation.

Status Reply

- Data polling & Toggle bit for detection of program and

erase cycle completion.

Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

- Sector protect/unprotect for 5V only system or 5V/12V

system

100,000 minimum erase/program cycles

Latch-up protected to 100mA from -1 to VCC+1V

Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

Hardware RESET pin(only for 29F002T/B)

- Resets internal state machine to read mode

Low VCC write inhibit is equal to or less than 3.2V

Package type:

- 32-pin PDIP

- 32-pin PLCC

- 32-pin TSOP (Type 1)

20 years data retention

P/N: PM0547

REV. 1.5, MAR. 28, 2005

MXIC's Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields for
erase and programming operations produces reliable
cycling. The MX29F002T/B uses a 5.0V ± 10% VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.

The highest degree of latch-up protection is achieved with
MXIC's proprietary non-epi process. Latch-up protection is
proved for stresses up to 100 milliamps on address and
data pin from -1V to VCC + 1V.

MX29F002/002N T/B

2M-BIT [256K x 8] CMOS FLASH MEMORY

REV. 1.5, MAR. 28, 2005

P/N: PM0547

MX29F002/002N T/B

PIN CONFIGURATIONS

32 PDIP

SECTOR STRUCTURE

32 PLCC

32 TSOP (TYPE 1)

(NORMAL TYPE)

PIN DESCRIPTION

SYMBOL

PIN NAME

A0~A17

Address Input

Q0~Q7

Data Input/Output

Chip Enable Input

Write Enable Input

RESET

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

VCC

Power Supply Pin (+5V)

GND

Ground Pin

MX29F002T Sector Architecture

MX29F002B Sector Architecture

MX29F002T/B

RESET

A16

A15

A12

GND

VCC

A17

A14

A13

A11

A10

NC on MX29F002NT/B

A11

A9
A8

A13
A14
A17

VCC

RESET

A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

MX29F002T/B

(NC on MX29F002NT/B)

A14

A13

A11

A10

VSS

A12

A15

A16

RESET

VCC

A17

MX29F002T/B

NC on MX29F002NT/B

1 6 K - B Y T E

8 K - B Y T E

3 2 K - B Y T E

0 0 0 0 0 H

3 F F F F H

( B O O T S E C T O R )

6 4 K - B Y T E

3 B F F F H

3 9 F F F H

3 7 F F F H

2 F F F F H

1 F F F F H

0 F F F F H

A 1 7 ~ A 0

1 6 K - B Y T E

8 K - B Y T E

3 2 K - B Y T E

0 0 0 0 0 H

( B O O T S E C T O R )

6 4 K - B Y T E

3 F F F F H

2 F F F F H

1 F F F F H

0 7 F F F H

0 5 F F F H

0 3 F F F H

0 F F F F H

A 1 7 ~ A 0

REV. 1.5, MAR. 28, 2005

P/N: PM0547

MX29F002/002N T/B

AUTOMATIC PROGRAMMING

The MX29F002T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical chip
programming time of the MX29F002T/B at room temperature
is less than 3.5 seconds.

AUTOMATIC CHIP ERASE

Typical erasure at room temperature is accomplished in
less than 3 seconds. The device is erased using the
Automatic Erase algorithm. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
internally controlled by the device.

AUTOMATIC SECTOR ERASE

The MX29F002T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically programs
the specified sector(s) prior to electrical erase. The timing
and verification of electrical erase are internally controlled
by the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write a program set-up commands include 2
unlock write cycle and A0H and a program command
(program data and address). The device automatically
times the programming pulse width, verifies the program,
and counts the number of sequences. A status bit similar
to DATA polling and a status bit toggling between
consecutive read cycles, provides feedback to the user as
to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard
microprocessor write timings. The device will automati-

cally pre-program and verify the entire array. Then the
device automatically times the erase pulse width, verifies
the erase, and counts the number of sequences. A status
bit similar to DATA polling and status bit toggling between
consecutive read cycles provides feedback to the user as
to the status of the programming operation.

Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as inputs to an internal state-machine which controls
the erase and programming circuitry. During write cycles,
the command register internally latches address and data
needed for the programming and erase operations. During
a system write cycle, addresses are latched on the falling
edge, and data are latched on the rising edge of WE .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29F002T/B electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.

During a program cycle, the state-machine will control the
program sequences and command register will not re-
spond to any command set. During a Sector Erase cycle,
the command register will only respond to Erase Suspend
command. After Erase Suspend is completed, the device
stays in read mode. After the state machine has com-
pleted its task, it will allow the command register to
respond to its full command set.

REV. 1.5, MAR. 28, 2005

P/N: PM0547

MX29F002/002N T/B

First Bus

Second Bus

Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr Data

Reset

XXXH F0H

Read

Read Silicon ID

555H AAH

2AAH 55H

555H

90H

ADI

DDI

Sector Protect

555H AAH

2AAH 55H

555H

90H

(SA)

00H

Verification

(X02H) 01H

Program

555H AAH

2AAH 55H

555H A0H

Chip Erase

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H 555H 10H

Sector Erase

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H SA 30H

Sector Erase Suspend

XXXH B0H

Sector Erase Resume

XXXH 30H

Unlock for sector

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H

555H 20H

protect/unprotect

TABLE 1. SOFTWARE COMMAND DEFINITIONS

COMMAND DEFINITIONS

Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.

Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).

DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't

care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated
with A11~A17 in either state.

4.For Sector Protect Verification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset command
sequences will reset the device(when applicable).

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