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1
MX10EXA
Major Difference
Product
FLASH
RAM
BIT
Package
(K BYTES) (BYTES) (CPU BUS)
MX10EXAQC
MX10EXAUC
44 PLCC
MX10EXAQCG
64 K
2048
16
40 LQFP
MX10EXAUCG
Feature
2
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
1
XA 16-bit Microcontroller Family
64K Flash/2K RAM, Watchdog, 2UARTs
FEATURE
4.5V to 5.5V
64K bytes of on-chip Flash program memory with In-
System Programming capability
Five Flash blocks = two 8k byte blocks and three 16k
byte blocks
Single supply voltage In-System Programming of the
Flash memory, (VPP=VDD or VPP=12V if desired)
Boot ROM contains low level Flash programming
routines for In-Application Programming and a default
serial loader using the UART
2048 bytes of on-chip data RAM
Supports off-chip program and data addressing up to 1
megabyte (20 address lines)
Three standard counter/timers with enhanced features
All timers have a toggle output capability
Watchdog timer
Two enhanced UARTs with independent baud rates
Seven software interrupts
Four 8-bit I/O ports, with 4 programmable output
configurations for each pin
30 MHz operating frequency at 5V
Power saving operating modes: Idle and Power-
Down.Wake-Up from power-down via an external inter-
rupt is supported.
44-pin PLCC (MX10EXAQC) Commercial grade
44-pin LQFP (MX10EXAUC) Commercial grade
44-pin PLCC (MX10EXAQI) Industrial grade
44-pin LQFP (MX10EXAUI) Industrial grade
GENERAL DESCRIPTION
The MX10EXA is a member of Philips' 80C51 XA
(eXtended Architecture) family of high performance 16-
bit single-chip microcontrollers.
The MX10EXA contains 64k bytes of Flash program
memory, and provides three general purpose timers/
counters, a watchdog timer, dual UARTs, and four gen-
eral purpose I/O ports with programmable output con-
figurations.
PIN CONFIGURATIONS
44 PLCC
A default serial loader program in the Boot ROM allows
In-System Programming (ISP) of the Flash memory with-
out the need for a loader in the Flash code. User pro-
grams may erase and reprogram the Flash memory at
will through the use of standard routines contained in
the Boot ROM (In-Application Programming).
MX10EXAUC
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
P2.5/A17D13
P1.4/RxD1
P1.3/A3
P1.2/A2
P1.1/A1
P1.0/A0/WRH
V
SS
V
DD
P0.0/A4D0
P0.1/A5D1
P0.2/A6D2
P0.3/A7D3
P3.6/WRL
P3.7/RD
XT
AL2
XT
AL1
V
SS
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
P2.4/A16D12
44
34
33
23
1
11
12
22
44 LQFP
MX10EXAQC
P1.5/TxD1
P1.6/T2
P1.7/T2EX
RST
P3.0/RxD0
NC
P3.1/TxD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1/BUSW
P0.4/A8D4
P0.5/A9D5
P0.6/A10D6
P0.7/A11D7
EA/VPP/WAIT
NC
ALE
PSEN
P2.7/A19D15
P2.6/A18D14
P2.5/A17D13
P1.4/RxD1
P1.3/A3
P1.2/A2
P1.1/A1
P1.0/A0/WRH
V
SS
V
DD
P0.0/A4D0
P0.1/A5D1
P0.2/A6D2
P0.3/A7D3
P3.6/WRL
P3.7/RD
XT
AL2
XT
AL1
V
SS
V
DD
P2.0/A12D8
P2.1/A13D9
P2.2/A14D10
P2.3/A15D11
P2.4/A16D12
6
44
40
39
34
29
7
12
17
18 23
28
1
3
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
BLOCK DIAGRAM
LOGIC SYMBOL
XA CPU Core
64K Bytes
FLASH
Program
Memory Bus
SFR
Bus
Data
Bus
2048 Bytes
Static RAM
UART0
UART1
Timer 0,1
Timer 2
Watchdog
Timer
Port 0
Port 1
Port 2
Port 3
POR
T 1
* NOT AVAILABLE ON 40-PIN DIP PACKAGE
T2EX*
T2*
TxD1
RxD1
A3
A2
A1
A0/WRH
RxD0
TxD0
INT0
INT1
T0
T1/BUSW
WRL
RD
RST
EA/WAIT
PSEN
ALE
ADDRESS
BU
S
ADDRESS AND D
A
T
A
B
U
S
POR
T 2
POR
T 0
POR
T 3
AL
TERNA
TE FUNCTIONS
XTAL2
XTAL1
VDD VSS
4
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
PIN DESCRIPTIONS
MNEMONIC PIN. NO.
TYPE
NAME AND FUNCTION
PLCC
LQFP
V SS
1, 22
16,39
I
Ground: 0V reference.
V DD
23, 44
17,38
I
Power Supply: This is the power supply voltage for normal, idle, and
power down operation.
P0.0-P0.7
43-36
37-30
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.
Port 0 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 0 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used, Port 0 becomes the mul-
tiplexed low data/instruction byte and address lines 4 through 11.
P1.0-P1.7
2-9
40-44,
I/O
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type.
1-3
Port 1 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 1 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 1 also provides special functions as described below.
2
40
O
A0/WRH: Address bit 0 of the external address bus when the external
data bus is configured for an 8 bit width. When the external data bus is
configured for a 16 bit width, this pin becomes the high byte write
strobe.
3
41
O
A1: Address bit 1 of the external address bus.
4
42
O
A2: Address bit 2 of the external address bus.
5
43
O
A3: Address bit 3 of the external address bus.
6
44
I
RxD1 (P1.4): Receiver input for serial port 1.
7
1
O
TxD1 (P1.5): Transmitter output for serial port 1.
8
2
I/O
T2 (P1.6): Timer/counter 2 external count input/clockout.
9
3
I
T2EX (P1.7): Timer/counter 2 reload/capture/direction control
P2.0-P2.7
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
Port 2 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. The operation of port 2 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2
becomes the multiplexed high data/instruction byte and address lines
12 through 19. When the external program/data bus is used in 8-bit
mode, the number of address lines that appear on port 2 is user pro-
grammable.
5
P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
MNEMONIC PIN. NO.
TYPE
NAME AND FUNCTION
PLCC
LQFP
P3.0-P3.7
11,13-19
5,7-13
I/O
Port 3: Port 3 is an 8-bit I/O port with a user configurable output type.
Port 3 latches have 1s written to them and are configured in the quasi-
bidirectional mode during reset. the operation of port 3 pins as inputs
and outputs depends upon the port configuration selected. Each port
pin is configured independently. Refer to the section on I/O port con-
figuration and the DC Electrical Characteristics for details.
Port 3 also provides various special functions as described below.
11
5
I
RxD0 (P3.0): Receiver input for serial port 0.
13
7
O
TxD0 (P3.1): Transmitter output for serial port 0.
14
8
I
INT0 (P3.2): External interrupt 0 input.
15
9
I
INT1 (P3.3): External interrupt 1 input.
16
10
I/O
T0 (P3.4): Timer 0 external input, or timer 0 overflow output.
17
11
I/O
T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output.
The value on this pin is latched as the external reset input is released
and defines the default external data bus width (BUSW). 0 = 8-bit bus
and 1 = 16-bit bus.
18
12
O
WRL (P3.6): External data memory low byte write strobe.
19
13
O
RD (P3.7): External data memory read strobe.
RST
10
4
I
Reset: A low on this pin resets the microcontroller, causing I/O ports
and peripherals to take on their default states, and the processor to
begin execution at the address contained in the reset vector. Refer to
the section on Reset for details.
ALE
33
27
I/O
Address Latch Enable: A high output on the ALE pin signals external
circuitry to latch the address portion of the multiplexed address/data
bus. A pulse on ALE occurs only when it is needed in order to process
a bus cycle.
PSEN
32
26
O
Program Store Enable: The read strobe for external program memory.
When the microcontroller accesses external program memory, PSEN
is driven low in order to enable memory devices. PSEN is only active
when external code accesses are performed.
EA/WAIT
35
29
I
External Access/Wait/Programming Supply Voltage: The EA input
/VPP
determines whether the internal program memory of the microcontroller
is used for code execution. The value on the EA pin is latched as the
external reset input is released and applies during later execution. When
latched as a 0, external program memory is used exclusively, when
latched as a 1, internal program memory will be used up to its limit, and
external program memory used above that point. After reset is released,
this pin takes on the function of bus Wait input. If Wait is asserted high
during any external bus access, that cycle will be extended until Wait
is released. During EPROM programming, this pin is also the program-
ming supply voltage input.
XTAL1
21
15
I
Crystal 1: Input to the inverting amplifier used in the oscillator circuit
and input to the internal clock generator circuits.
XTAL2
20
14
O
Crystal 2: Output from the oscillator amplifier.
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