1
P/N:PM0241
REV. 2.3, JUN. 20, 2003
FEATURES
Bit organization
- 2M x 8 (byte mode)
- 1M x 16 (word mode)
Fast access time
- Random access: 100ns (max.)
- Page access: 30ns (max.)
Page Size
- 8 double words per page
Current
- Operating: 60mA
- Standby: 50uA
Supply voltage
- 5V
10%
Package
- 44 pin SOP (500mil)
- 42 pin PDIP (600mil)
- 48 pin TSOP (20mm x 12mm)
ORDER INFORMATION
Part No.
Access Page Access Package
Time
Time
MX23C1611MC-10 100ns
30ns
44 pin SOP
MX23C1611MC-12 120ns
50ns
44 pin SOP
MX23C1611PC-10
100ns
30ns
42 pin PDIP
MX23C1611PC-12
120ns
50ns
42 pin PDIP
MX23C1611TC-10
100ns
30ns
48 pin TSOP
MX23C1611TC-12
120ns
50ns
48 pin TSOP
PIN DESCRIPTION
Symbol
Pin Function
A0~A19
Address Inputs
D0~D14
Data Outputs
D15/A-1
D15 (Word Mode)/ LSB Address
(Byte Mode)
CE
Chip Enable Input
OE
Output Enable Input
Byte
Word/ Byte Mode Selection
VCC
Power Supply Pin
VSS
Ground Pin
NC
No Connection
PIN CONFIGURATION
44 SOP
42 PDIP
MODE SELECTION
CE
OE
Byte
D31/A-1
D0~D15
D16~D31
Mode
Power
H
X
X
X
High Z
High Z
-
Stand-by
L
H
X
X
High Z
High Z
-
Active
L
L
H
Output
D0~D7
D8~D15
Word
Active
L
L
L
Input
D0~D7
High Z
Byte
Active
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
MX23C1611
MX23C1611
MX23C1611
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
D0
D8
D1
D9
D2
D10
D3
D11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
5 Volt 16-Mbit (2M x 8 / 1M x 16) Mask ROM with Page Mode
2
P/N:PM0241
REV. 2.3, JUN. 20, 2003
MX23C1611
48 TSOP (Normal Type)
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
VSS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VSS
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
VCC
NC
D11
D3
D10
D2
D9
D1
D8
D0
OE
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23C1611
(Normal Type)
BLOCK DIAGRAM
Address
Buffer
Memory
Array
Page
Buffer
Page
Decoder
Word/
Byte
Output
Buffer
D0
D15/(D7)
A3
A19
A0/(A-1)
A2
CE
BYTE
OE
Note: Chip Enable active low input activates the chip's control logic, Address buffer and Page buffer.
3
P/N:PM0241
REV. 2.3, JUN. 20, 2003
MX23C1611
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
Voltage on any Pin Relative to VSS
VIN
-1.3V to VCC+2.0V (Note)
Ambient Operating Temperature
Topr
-40
C to 85
C
Storage Temperature
Tstg
-65
C to 125
C
DC CHARACTERISTICS (Ta = 0
C ~ 70
C, VCC = 5V
10%)
Item
Symbol
MIN.
MAX.
Conditions
Output High Voltage
VOH
2.4V
-
IOH = -1.0mA
Output Low Voltage
VOL
-
0.4V
IOL = 2.1mA
Input High Voltage
VIH
2.2V
VCC+0.3V
Input Low Voltage
VIL
-0.3V
0.2 x VCC
Input Leakage Current
ILI
-
5uA
0V, VCC
Output Leakage Current
ILO
-
5uA
0V, VCC
Operating Current
ICC1
-
60mA
tRC = 100ns, all output open
Standby Current (TTL)
ISTB1
-
1mA
CE = VIH
Standby Current (cmos)
ISTB2
-
50uA
CE>VCC-0.2V
Input Capacitance
CIN
-
10pF
Ta = 25
C, f = 1MHZ
Output Capacitance
COUT
-
10pF
Ta = 25
C, f = 1MHZ
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transi-
tions, input may overshoot VCC to VCC+2.0V for peri-
ods of up to 20ns.
AC CHARACTERISTICS (Ta = 0
C ~ 70
C, VCC = 5V
10%)
Item
Symbol
23C1611-10
23C1611-12
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
tRC
100ns
-
120ns
-
Address Access Time
tAA
-
100ns
-
120ns
Chip Enable Access Time
tCE
-
100ns
-
120ns
Page Mode Access Time
tPA
-
30ns
-
50ns
Output Enable Time
tOE
-
30ns
-
50ns
Output Hold After Address
tOH
0ns
-
0ns
-
Output High Z Delay
tHZ
-
20ns
-
20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaran-
teed by design over the full voltage and temperature op-
erating range - not tested.
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P/N:PM0241
REV. 2.3, JUN. 20, 2003
MX23C1611
AC Test Conditions
Input Pulse Levels
0.4V~ 2.4V
Input Rise and Fall Times
10ns
Input Timing Level
1.5V
Output Timing Level
0.8V and 2.0V
Output Load
See Figure
TIMING DIAGRAM
RANDOM READ
PAGE READ
A3-A19
(A-1),A0,A1,A2
DATA
Note: CE, OE are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
VALID ADD
VALID
1'st ADD
2'nd ADD
tPA
tAA
3'rd ADD
VALID
VALID
Note:
No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
DOUT
C<30pF
IOL (load)=2.1mA
IOH (load)=-1mA
tCE
tAA
tOH
tHZ
ADD
ADD
ADD
ADD
CE
OE
DATA
VALID
VALID
VALID
tRC
tOE
5
P/N:PM0241
REV. 2.3, JUN. 20, 2003
MX23C1611
PACKAGE INFORMATION
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