P/N:PM0439

REV. 2.2 , NOV. 29, 2002

MX29F400T/B

4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY

erase cycle completion.

· Ready/Busy pin (RY/BY)

- Provides a hardware method of detecting program or
erase cycle completion.
- Sector protect/unprotect for 5V only system or 5V/
12V system.

· Sector protection

- Hardware method to disable any combination of
sectors from program or erase operations

· 100,000 minimum erase/program cycles
· Latch-up protected to 100mA from -1V to VCC+1V
· Boot Code Sector Architecture

- T = Top Boot Sector
- B = Bottom Boot Sector

· Low VCC write inhibit is equal to or less than 3.2V
· Package type:

- 44-pin SOP
- 48-pin TSOP

· Compatibility with JEDEC standard

- Pinout and software compatible with single-power
supply Flash

· 20 years data retention

FEATURES

· 524,288 x 8/262,144 x 16 switchable
· Single power supply operation

- 5.0V only operation for read, erase and program
operation

· Fast access time: 55/70/90/120ns
· Low power consumption

- 40mA maximum active current(5MHz)
- 1uA typical standby current

· Command register architecture

- Byte/word Programming (7us/12us typical)
- Sector Erase (Sector structure 16K-Bytex1, 8K-
Bytex2, 32K-Bytex1, and 64K-Byte x7)

· Auto Erase (chip & sector) and Auto Program

- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address

· Erase suspend/Erase Resume

- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.

· Status Reply

- Data polling & Toggle bit for detection of program and

GENERAL DESCRIPTION

The MX29F400T/B is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits or 256K words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29F400T/B is packaged in 44-pin SOP,
48-pin TSOP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.

The standard MX29F400T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F400T/B has separate chip enable (CE) and
output enable (OE) controls.

MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F400T/B uses a command register to manage this
functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29F400T/B uses a 5.0V

10% VCC sup-

ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.

The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

PIN CONFIGURATIONS

44 SOP(500 mil)

PIN DESCRIPTION

SYMBOL

PIN NAME

A0~A17

Address Input

Q0~Q14

Data Input/Output

Q15/A-1

Q15(Word mode)/LSB addr(Byte mode)

Chip Enable Input

Write Enable Input

BYTE

Word/Byte Selection input

RESET

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

RY/BY

Ready/Busy Output

VCC

Power Supply Pin (+5V)

GND

Ground Pin

48 TSOP (Standard Type) (12mm x 20mm)

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

RY/BY

A17

A7
A6
A5
A4
A3
A2
A1
A0

GND

Q0
Q8
Q1
Q9
Q2

Q10

Q11

RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC

MX29F400T/B

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

RESET

NC
NC

RY/BY

A17

A7
A6
A5
A4
A3
A2
A1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

MX29F400T/B

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

Sector Size

Address Range (in hexadecimal)

(Kbytes/

(x8)

(x16)

Sector

A17

A16

A15

A14

A13

A12

Kwords)

Address Range

SA0

64/32

00000h-0FFFFh

00000h-07FFFh

SA1

64/32

10000h-1FFFFh

08000h-0FFFFh

SA2

64/32

20000h-2FFFFh

10000h-17FFFh

SA3

64/32

30000h-3FFFFh

18000h-1FFFFh

SA4

64/32

40000h-4FFFFh

20000h-27FFFh

SA5

64/32

50000h-5FFFFh

28000h-2FFFFh

SA6

64/32

60000h-6FFFFh

30000h-37FFFh

SA7

32/16

70000h-77FFFh

38000h-3BFFFh

SA8

8/4

78000h-79FFFh

3C000h-3CFFFh

SA9

8/4

7A000h-7BFFFh

3D000h-3DFFFh

SA10

16/8

7C000h-7FFFFh

3E000h-3FFFFh

Sector Size

Address Range (in hexadecimal)

(Kbytes/

(x8)

(x16)

Sector

A17

A16

A15

A14

A13

A12

Kwords)

Address Range

SA0

16/8

00000h-03FFFh

00000h-01FFFh

SA1

8/4

04000h-05FFFh

02000h-02FFFh

SA2

8/4

06000h-07FFFh

03000h-03FFFh

SA3

32/16

08000h-0FFFFh

04000h-07FFFh

SA4

64/32

10000h-1FFFFh

08000h-0FFFFh

SA5

64/32

20000h-2FFFFh

10000h-17FFFh

SA6

64/32

30000h-3FFFFh

18000h-1FFFFh

SA7

64/32

40000h-4FFFFh

20000h-27FFFh

SA8

64/32

50000h-5FFFFh

28000h-2FFFFh

SA9

64/32

60000h-6FFFFh

30000h-37FFFh

SA10

64/32

70000h-7FFFFh

38000h-3FFFFh

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

SECTOR STRUCTURE

MX29F400T TOP BOOT SECTOR ADDRESS TABLE

MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AUTOMATIC PROGRAMMING

The MX29F400T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F400T/B is less than 4 sec-
onds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm au-
tomatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are con-
trolled internally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.

Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first .

MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F400T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.

During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

First Bus

Second Bus Third Bus

Fourth Bus

Fifth Bus

Sixth Bus

Command

Bus

Cycle

Cycle Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data Addr

Data

Reset

XXXH F0H

Read

Read Silicon ID Word

555H AAH

2AAH 55H

555H

90H

ADI

DDI

Byte

AAAH AAH

555H 55H

AAAH 90H

ADI

DDI

Sector Protect

Word

555H AAH

2AAH 55H

555H

90H

(SA)

XX00H

Verify

x02H XX01H

Byte

AAAH AAH

555H 55H

AAAH 90H

(SA)

00H

x04H 01H

Program

Word

555H AAH

2AAH 55H

555H

A0H

Byte

AAAH AAH

555H 55H

AAAH A0H

Chip Erase

Word

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H

555H 10H

Byte

AAAH AAH

555H 55H

AAAH 80H

AAAH AAH

555H

55H

AAAH 10H

Sector Erase

Word

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H

30H

Byte

AAAH AAH

555H 55H

AAAH 80H

AAAH AAH

555H

55H

30H

Sector Erase Suspend

XXXH B0H

Sector Erase Resume

XXXH 30H

Unlock for sector

555H AAH

2AAH 55H

555H

80H

555H AAH

2AAH 55H

555H 20H

protect/unprotect

TABLE1. SOFTWARE COMMAND DEFINITIONS

Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it

means the sector is still not being protected.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

Pins

Q0 ~ Q15

Mode

Read Silicon ID

(2)

C2H (Byte mode)

Manufacture Code(1)

00C2H (Word mode)

Read Silicon ID

(2)

23H/ABH (Byte mode)

Device Code(1)

2223H/22ABH (Word mode)

Read

OUT

Standby

HIGH Z

Output Disable

HIGH Z

Write

(3)

Sector Protect with 12V

(2)

system(6)

Chip Unprotect with 12V

(2)

system(6)

Verify Sector Protect

(2)

Code(5)

with 12V system

Sector Protect without 12V

system (6)

Chip Unprotect without 12V

system (6)

Verify Sector Protect/Unprotect

Code(5)

without 12V system (7)

Reset

HIGH Z

TABLE 2. MX29F400T/B BUS OPERATION

NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.
A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system"

command.

Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset com-
mand sequences will reset the device(when applicable).

COMMAND DEFINITIONS

Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.

If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design
practice.

The MX29F400T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 23H/2223H for MX29F400T, ABH/22ABH
for MX29F400B.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Pins

Q15~Q8 Q7

Q2 Q1

Code(Hex)

Manufacture code

Word

VIL

00H

00C2H

Byte

VIL

C2H

Device code

Word

VIH

VIL

22H

2223H

for MX29F400T

Byte

VIH

VIL

23H

Device code

Word

VIH

VIL

22H

22ABH

for MX29F400B

Byte

VIH

VIL

ABH

Sector Protection

VIH

01H (Protected)

Verification

VIH

00H (Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

COMMANDS

Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.

When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).

If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.

The automatic erase begins on the rising edge of the
last WE or CE, whichever happens later, pulse in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

Status

RY/BY

Note1

Note2

Byte Program in Auto Program Algorithm

Toggle

N/A

Toggle

Auto Erase Algorithm

Toggle

Erase Suspend Read

N/A Toggle

(Erase Suspended Sector)

Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

N/A

Byte Program in Auto Program Algorithm

Toggle

N/A

Toggle

Exceeded
Time Limits Auto Erase Algorithm

Toggle

Erase Suspend Program

Toggle

N/A

erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the set-
up command 80H. Two more "unlock" write cycles are
then followed by the sector erase command 30H. The
sector address is latched on the falling edge of WE or
CE, whichever happens later, while the command(data)
is latched on the rising edge of WE or CE, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE or
CE, whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE, which-
ever happens later, must begin within 30us from the
rising edge of the preceding WE or CE, whichever hap-
pens First, otherwise, the loading period ends and inter-
nal auto sector erase cycle starts. (Monitor Q3 to deter-
mine if the sector erase timer window is still open, see
section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Set-up Sector Erase command and Auto-
matic Sector Erase command. Upon executing the Au-
tomatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.

When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.

When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate

Table 4. Write Operation Status

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

ERASE SUSPEND

This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com-
mand is written during a sector erase operation, the de-
vice requires a maximum of 100us to suspend the erase
operations. However, When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto-
matically after suspend is ready. At this time, state ma-
chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.

The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.

SET-UP AUTOMATIC PROGRAM

COMMANDS

To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.

Once the Automatic Program command is initiated, the
next WE or CE, pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE or CE, whichever happens first,
pulse. The rising edge of WE or CE, whichever happens
first, also begins the programming operation. The sys-

tem is not required to provide further controls or timings.
The device will automatically provide an adequate inter-
nally generated program pulse and verify margin.

If the program operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).

DATA POLLING-Q7

The MX29F400T/B also features Data Polling as a
method to indicate to the host system that the Auto-
matic Program or Erase algorithms are either in progress
or completed.

While the Automatic Programming algorithm is in opera-
tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WE or CE, whichever happens
first, pulse of the four write pulse sequences for auto-
matic program.

While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE or CE, whichever happens first
pulse of six write pulse sequences for automatic chip/
sector erase.

The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm or sector erase time-out. (see sec-
tion Q3 Sector Erase Timer)

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence. Since
RY/BY is an open-drain output, several RY/BY pins can
be tied together in parallel with a pull-up resistor to Vcc.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid af-
ter the rising edge of the final WE or CE, whichever hap-
pens first, pulse in the command sequence.

Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.

The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence (prior to
the program or erase operation), and during the sector
time-out.

During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to con-
trol the read cycles. When the operation is complete, Q6
stops toggling.

After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.

The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.

Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the de-
vice is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.

Table 4 shows the outputs for RY/BY.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

Q5
Exceeded Timing Limits

Q5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling and Toggle Bit
are the only operating functions of the device under this
condition.

If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.

If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.

If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).

The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops tog-
gling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.

DATA PROTECTION

The MX29F400T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorpo-
rates several features to prevent inadvertent write cycles

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously
protected sector to change data in-system. The Tempo-
rary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin, all the previously protected sectors are pro-
tected again.

Sector Erase Timer

After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.

resulting from VCC power-up and power-down transition
or system noise.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F400T/B features hardware sector protection.
This feature will disable both program and erase opera-
tions for these sectors protected. To activate this mode,
the programming equipment must force VID on address
pin A9 and control pin OE, (suggest VID = 12V) A6 =
VIL and CE = VIL.(see Table 2) Programming of the
protection circuitry begins on the falling edge of the WE
pulse and is terminated on the rising edge. Please refer
to sector protect algorithm and waveform.

To verify programming of the protection circuitry, the pro-
gramming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the addresses,
except for A1, are don't care. Address locations with A1
= VIL are reserved to read manufacturer and device
codes.(Read Silicon ID)

It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F400T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before
activating chip unprotect mode.

To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated on the rising edge.

It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.

POWER-UP SEQUENCE

The MX29F400T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

-40

C to 125

C (*)

Ambient Temperature with Power

-55

C to 125

Applied

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to 7.0V

VCC to Ground Potential

-0.5V to 7.0V

A9 & OE

-0.5V to 13.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect reliability.

NOTICE:
Specifications contained within the following tables are sub-
ject to change.
* The automotive grade is under development.

SECTOR PROTECTION WITHOUT 12V

The MX29F400T/B also feature a hardware sector
protection method in a system without 12V power suppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protect algorithm and waveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.

SYSTEM

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

CAPACITANCE TA = 25

C, f = 1.0 MHz

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

CIN1

Input Capacitance

VIN = 0V

CIN2

Control Pin Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

DC CHARACTERISTICS

TA = 0

C to 70

C, -40

C to 125

C(Note 3), VCC = 5V

10%

SYMBOL PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

VIN = GND to VCC

ILO

Output Leakage Current

VOUT = GND to VCC

ISB1

Standby VCC current

CE = VIH

ISB2

1(Note3) 5(Note3)

CE = VCC

0.3V

ICC1

Operating VCC current

IOUT = 0mA, f=5MHz

ICC2

IOUT= 0mA, f=10MHz

VIL

Input Low Voltage

-0.3(NOTE 1)

0.8

VIH

Input High Voltage(NOTE 2)

2.0

VCC + 0.3

VOL

Output Low Voltage

0.45

IOL = 2.1mA

VOH1

Output High Voltage(TTL)

2.4

IOH = -2mA

VOH2

Output High Voltage(CMOS) VCC-0.4

IOH = -100uA,VCC=VCC MIN

NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ISB2 20uA max. for Automotive grade. Which is under development.

READ OPERATION

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AC CHARACTERISTICS

TA = 0

C to 70

C, -40

C to 125

C(Note 3), VCC = 5V

10%

29F400T/B-55

(Note2)

29F400T/B-70

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT Conditions

tACC

Address to Output Delay

CE=OE=VIL

tCE

CE to Output Delay

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note1)

CE=VIL

tOH

Address to Output hold

CE=OE=VIL

NOTE:

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

2. VCC=5V

10%,CL=50pF,VIH/VIL=3.0V/0V,

VOH/VOL=1.5V/1.5V, IOL=2mA,IOH=-2mA.
3. Automotive grade is only provided for MX29F400T/B-

90 & MX29F400T/B-12. Which are under development.

TEST CONDITIONS:

· Input pulse levels: 0.45V/2.4V
· Input rise and fall times is equal to or less than 10ns
· Output load: 1 TTL gate + 100pF (Including scope and

jig)

· Reference levels for measuring timing: 0.8V, 2.0V

29F400T/B-90 (Note3) 29F400T/B-12(Note3)

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT Conditions

tACC

Address to Output Delay

120

CE=OE=VIL

tCE

CE to Output Delay

120

OE=VIL

tOE

OE to Output Delay

CE=VIL

tDF

OE High to Output Float (Note1) 0

CE=VIL

tOH

Address to Output hold

CE=OE=VIL

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

READ TIMING WAVEFORMS

Addresses

tACC

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z

DATA Valid

tOE

tDF

tCE

Outputs

tOH

ADD Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.
5. The automotive grade is under development.

DC CHARACTERISTICS

TA = 0

C to 70

C, -40

C to 125

C(Note 5), VCC = 5V

10%

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ICC1 (Read)

Operating VCC Current

IOUT=0mA, f=5MHz

ICC2

IOUT=0mA, F=10MHz

ICC3 (Program)

In Programming

ICC4 (Erase)

In Erase

ICCES

VCC Erase Suspend Current

CE=VIH, Erase Suspended

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AC CHARACTERISTICS TA = 0

C to 70

C, VCC = 5V

10%

29F400T/B-55(Note2)

29F400T/B-70

Symbol

PARAMETER

MIN.

MAX.

MIN.

MAX.

Unit

tOES

OE setup time

tCWC

Command programming cycle

tCEP

WE programming pulse width

tCEPH1

WE programming pluse width High

tCEPH2

WE programming pluse width High

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

tCESC

CE setup time before command write 0

tDF

Output disable time (Note 1)

tAETC

Total erase time in auto chip erase

4(TYP.)

tAETB

Total erase time in auto sector erase

1.3(TYP.)

10.4

1.3(TYP.)

10.4

tAVT

Total programming time in auto verify 7/12(TYP.)

210/360

7/12(TYP.)

210/360

(byte/ word program time)

tBAL

Sector address load time

100

tCH

CE Hold Time

tCS

CE setup to WE going low

tVLHT

Voltge Transition Time

tOESP

OE Setup Time to WE Active

tWPP1

Write pulse width for sector protect

tWPP2

Write pulse width for sector unprotect 12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under condition of VCC=5V

10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AC CHARACTERISTICS TA = 0

C to 70

C, -40

C to 125

C(Note 3), VCC = 5V

10%

29F400T/B-90

29F400T/B-120

Symbol

PARAMETER

MIN.

MAX.

MIN.

MAX.

Unit

tOES

OE setup time

tCWC

Command programming cycle

120

tCEP

WE programming pulse width

tCEPH1

WE programming pluse width High

tCEPH2

WE programming pluse width High

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

tCESC

CE setup time before command write

tDF

Output disable time (Note 1)

tAETC

Total erase time in auto chip erase

4(TYP.)

tAETB

Total erase time in auto sector erase

1.3(TYP.)

10.4

1.3(TYP.)

10.4

tAVT

Total programming time in auto verify

7/12(TYP.)

210/360

7/12(TYP.)

210/360

(byte/ word program time)

tBAL

Sector address load time

100

tCH

CE Hold Time

tCS

CE setup to WE going low

tVLHT

Voltge Transition Time

tOESP

OE Setup Time to WE Active

tWPP1

Write pulse width for sector protect

tWPP2

Write pulse width for sector unprotect

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. Under condition of VCC=5V

10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.

3. The automotive grade is under development.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AUTOMATIC PROGRAMMING TIMING

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

WAVEFORM

One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed auto-
matically by internal control circuit. Programming
completion can be verified by DATA polling and toggle

bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after pro-
gramming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)

tCWC

tAS

tCEP

tDS

tDH

tDF

Vcc 5V

Q0,Q1,Q2

Q4(Note 1)

A11~A17

tCEPH1

tAH

ADD Valid

tCESC

Command In

ADD Valid

A0~A10

Command In

Data In

DATA

Command In

Data In

DATA

tAVT

tOE

DATA polling

2AAH

555H

(Q0~Q7)

Command #55H

Command #A0H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

Command #AAH

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA polling and toggle bit checking after auto-

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

tCWC

tAS

tCEP

tDS tDH

Vcc 5V

Q0,Q1,

Q4(Note 1)

A11~A17

tCEPH1

tAH

Command In

A0~A10

Command In

tAETC

DATA polling

2AAH

555H

Command #AAH

Command #55H

Command #80H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

555H

2AAH

555H

Command In

Command #AAH

Command In

Command #55H

Command In

Command #10H

AUTOMATIC CHIP ERASE TIMING WAVEFORM

matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

Sector data indicated by A12 to A17 are erased. Exter-
nal erase verify is not required because data are erased
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit check-

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)

tAH

Sector

Address0

555H

2AAH

555H

Sector

Address1

Sector

Addressn

Vcc 5V

Q0,Q1,

Q4(Note 1)

A12~A17

A0~A10

Command

Command #30H

Command #55H

Command #AAH

Command #80H

Command #55H

Command #AAH

(Q0~Q7)

Command

tDH

tDS

tCEP

tCWC

tAETB

tBAL

DATA polling

tCEPH1

tAS

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

-1.0V

13.5V

Input Voltage with respect to GND on all I/O pins

-1.0V

Vcc + 1.0V

Current

-100mA

+100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

1.3

10.4

sec

Chip Erase Time

sec

Byte Programming Time

210

Word Programming Time

360

Chip Programming Time

sec

Erase/Program Cycles

100,000

Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE(1)

Note:

1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25

C,5V.

3.Maximum values measured at 25

C,4.5V.

PARAMETER

MIN.

UNIT

Data Retention Time

Years

DATA RETENTION

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

ORDERING INFORMATION

PART NO.

Access Time Operating Current Standby Current Temperature

PACKAGE

Remark

(ns)

MAX.(mA)

MAX.(uA)

Range

MX29F400TMC-55

C~70

44 Pin SOP

MX29F400TMC-70

C~70

44 Pin SOP

MX29F400TMC-90

C~70

44 Pin SOP

MX29F400TMC-12

120

C~70

44 Pin SOP

MX29F400TTC-55

C~70

48 Pin TSOP

(Normal Type)

MX29F400TTC-70

C~70

48 Pin TSOP

(Normal Type)

MX29F400TTC-90

C~70

48 Pin TSOP

(Normal Type)

MX29F400TTC-12

120

C~70

48 Pin TSOP

(Normal Type)

MX29F400TTC-55G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400TTC-70G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400TTC-90G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400TTC-12G

120

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400BMC-55

C~70

44 Pin SOP

MX29F400BMC-70

C~70

44 Pin SOP

MX29F400BMC-90

C~70

44 Pin SOP

MX29F400BMC-12

120

C~70

44 Pin SOP

MX29F400BTC-55

C~70

48 Pin TSOP

(Normal Type)

MX29F400BTC-70

C~70

48 Pin TSOP

(Normal Type)

MX29F400BTC-90

C~70

48 Pin TSOP

(Normal Type)

MX29F400BTC-12

120

C~70

48 Pin TSOP

(Normal Type)

MX29F400BTC-55G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400BTC-70G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400BTC-90G

C~70

48 Pin TSOP PB free

(Normal Type)

MX29F400BTC-12G

120

C~70

48 Pin TSOP PB free

(Normal Type)

Note: MX29F400T/B-55 is supplied by request.

P/N:PM0439

MX29F400T/B

REV. 2.2, NOV. 29, 2002

REVISION HISTORY

Revision

Description

Page

Date

1.0

To remove "Advanced Information" datasheet marking and

JUL/01/1999

contain information on products in full production.

1.1

To correct the typing error on package dimension.

P41

SEP/01/1999

In fact,the physical packages are never changed,just correct the
previously typing error.

1.2

To add the description for 100K endurance cycles

P1,P40

SEP/17/1999

To modify timing of sector address loading period while

operating multi-sector erase from 80uS to 30uS
To modify tBAL from 80uS to 100uS

P20,P21

1.3

1.Program/erase cycle times:10K cycles-->100K cycles

P1,34

DEC/20/1999

2.To add data retention minimum 20 years

P1,34

3.To remove A9 from "timing waveform for sector protection for P34
system without 12V"
To remove A9 from "timing waveform for chip unprotection for P35
system without 12V"

1.4

Add erase suspend ready max. 100us in ERASE SUSPEND's

P10

MAY/29/2000

section at page10

1.5

To modify "Package Information"

P41~42

JUN/12/2001

1.6

Add automotive grade

P16-20,40

NOV/12/2001

1.7

Add MX29F400BTA-90/12 in Ordering Information

P40

FEB/04/2002

1.8

Add MX29F400TMI-55/70/90/12 & MX29F400TTI-55/70/90/12 in P40

FEB/19/2002

Ordering Information

1.9

To added 48-TSOP with PB free package

P41

APR/03/2002

2.0

1. Remove industrial grade

P40

AUG/13/2002

2. Add remark of "under development" for automotive grade

P16~19,21

2.1

To modify Package Information

P41~42

NOV/20/2002

2.2

Updated ordering information

P40

NOV/29/2002

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX29F400BMC-12

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MX29F400BMC-12