MDT10P22(BE)

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P. 1

2005/6 Ver. 1.4

1. General Description

This EPROM-Based 8-bit micro-controller
uses a fully static CMOS design technology
to achieve high speed, small size, low power
and high noise immunity.

On chip memory includes 1K words EPROM
and80 bytes static RAM.
Four comparator inputs with external Vref
(not for 18 pin package) are also provided.

2. Features

Fully CMOS static design

8-bit data bus

On chip EPROM size : 1 K words

Internal RAM size : 80 bytes

(72 general purpose registers, 8
special registers)

36 single word instructions

14-bit instructions

2-level stacks

Operating voltage : 2.3V ~ 5.5 V

Operating frequency : 0 ~ 20 MHz

The most fast execution time is 200 ns
under 20 MHz in all single cycle
instructions except

the branch instruction

Addressing modes include direct,

indirect and

relative addressing modes

Built-in Power-on Reset

4 Channel comparator

Power edge-detector Reset

Sleep Mode for power saving

8-bit real time clock/counter(RTCC) with

8-bit programmable prescaler

4 types of oscillator can be selected by

programming option:

Low cost RC oscillator

LFXT

Low frequency crystal oscillator

XTAL

Standard crystal oscillator

HFXT

High frequency crystal oscillator

4 oscillator start-up time can be selected

by programming option:

150

s, 20 ms, 40 ms, 80 ms

On-chip RC oscillator based Watchdog

Timer(WDT) can be operated freely

12 I/O(for 18 pins package),14 I/O(for 20

pins package),16 I/O(for 22/24 pins
package) pins with their own independent
direction control

3. Applications

The application areas of this MDT10P22
range from appliance motor control and high
speed automotive to low power remote
transmitters/receivers, pointing devices, and
telecommunications processors, such as
Remote controller, small instruments,
chargers, toy, automobile and PC
peripheral ... etc

MDT10P22(BE)

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P. 2

2005/6 Ver. 1.4

4. Pin Assignment

20PINS, A2

22PINS,

24PINS, A5 :18 PINS

PDIP,S

SOP, K

SKINNY

A1P,A1S

PA5 1

20 PA4/VREF

PA2/CIC2 2

19 PA1/CIC1

PA3/CIC3 3

18 PA0/CIC0

RTCC 4

17 OSC1

/MCLR 5

16 OSC2

Vss 6

15 Vdd

PB0 7

14 PB7

PB1 8

13 PB6

PB2 9

12 PB5

PB3 10

11 PB4

A2K

PA7 1

22 PA6

PA5 2

21 PA4/VREF

PA2/CIC2 3

20 PA1/CIC1

PA3/CIC3 4

19 PA0/CIC0

RTCC 5

18 OSC1

/MCLR 6

17 OSC2

Vss 7

16 Vdd

PB0 8

15 PB7

PB1 9

14 PB6

PB2 10

13 PB5

PB3 11

12 PB4

A3S

NC 1

24 NC

PA7 2

23 PA6

PA5 3

22 PA4/VREF

PA2/CIC2 4

21 PA1/CIC1

PA3/CIC3 5

20 PA0/CIC0

RTCC 6

19 OSC1

/MCLR 7

18 OSC2

Vss 8

17 Vdd

PB0 9

16 PB7

PB1 10

15 PB6

PB2 11

14 PB5

PB3 12

13 PB4

A5P,A5S

PA2CIC2 1

18 PA1/CIC1

PA3/CIC3 2

17 PA0/CIC0

RTCC 3

16 OSC1

/MCLR 4

15 OSC2

Vss 5

14 Vdd

PB0 6

13 PB7

PB1 7

12 PB6

PB2 8

11 PB5

PB3 9

10 PB4

MDT10P22(BE)

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P. 3

2005/6 Ver. 1.4

5. Block Diagram

Stack Two Levels

Program Counters

Oscillator Circuit

Power on Reset

Power Down Reset

8-bit Timer/Counter

EPROM

14 (MDT10P22)

Instruction

Decoder

Working Register

ALU

Prescale

RAM

Special Register

Control Circuit

Status Register

WDT/OST

Timer

Port B

Port A

C2 MC

Data

8-bit

RTCC

10 bits

14 bits

Port

PA0~P

(22,24

pins)

PA0~P

(20

pins)

PA0~P

(18

pins)

8 bits

Port

PB0~P

8 bits

D0~D

Comparat

or mode
Register

CMR0~C

MR5

MDT10P22(BE)

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P. 4

2005/6 Ver. 1.4

6. Pin Function Description

Pin Name

I/O

Function Description

PA0~PA7

I/O

PA0~PA3 : TTL input level or comparator input
PA4 : TTL input level or comparator VREF input
PA5~PA7 : TTL input level

PB0~PB7

I/O

Port B, TTL input level

RTCC

Real Time Clock/Counter, Schmitt Trigger input levels

/MCLR

Master Clear, Schmitt Trigger input levels

OSC1

Oscillator Input

OSC2

Oscillator Output

Vdd

Power supply

Vss

Ground

Unused ,do not connect

7. Memory Map

(A) Register Map

Address

Description

Indirect Addressing Register

RTCC

STATUS

MSR

Port A

Port B

Control register for comparator

08~0F

Internal RAM, General Purpose Register

10~1F

Internal RAM, Memory bank 0

30~3F

Internal RAM, Memory bank 1

50~5F

Internal RAM, Memory bank 2

70~7F

Internal RAM, memory bank 3

MDT10P22(BE)

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P. 5

2005/6 Ver. 1.4

(1) IAR ( Indirect Address Register) : R0

(2) RTCC (Real Time Counter/Counter Register) : R1

(3) PC (Program Counter) : R2

Write PC, CALL --- always 0

LJUMP, JUMP, LCALL --- from instruction word

RTWI, RET --- from STACK

A7~A0

Write PC, JUMP, CALL --- from STATUS b5

LJUMP, LCALL --- from instruction word

RTWI, RET --- from STACK

Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK

(4) STATUS (Status register) : R3

Bit

Symbol

Function

0
1
2
3
4
5

C
HC
Z
PF
TF
page

----

Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
Time overflow Flag bit
ROM Page select bit :

00 : 000H --- 1FFH
01 : 200H --- 3FFH
General purpose bit

MDT10P22(BE)

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P. 6

2005/6 Ver. 1.4

(5) MSR (Memory Select Register) : R4

Memory Select Register :

00 : 10~1F
01 : 30~3F
10 : 50~5F
11 : 70~7F

Read only "1"

Indirect Addressing Mode

(6) PORT A : R5

PA7~PA0, I/O Register for 22, 24 pins

PA5~PA0, I/O Register for 20 pins
PA3~PA0, I/O Register for 18 pins

(7) PORT B : R6

PB7~PB0, I/O Register

(8) CMR(Comparator Mode Register) : R7

Bit

Function

5:4

7:6

0: Define PA0 as TTL input
1: Define PA0 as comparator input
0: Define PA1 as TTL input
1: Define PA1 as comparator input
0: Define PA2 as TTL input
1: Define PA2 as comparator input
0: Define PA3 as TTL input
1: Define PA3 as comparator input

Reference Voltage select

00: 1/4 VDD
01: 1/2 VDD
10: 3/4 VDD
11: VREF (External pin and PA4 must be set to input)
Register bits

MDT10P22(BE)

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P. 7

2005/6 Ver. 1.4

(9) TMR (Time Mode Register)

Bit

Symbol

Function

Prescaler Value

RTCC rate

WDT rate

PS2

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

PSC

Prescaler assignment bit :
0

RTCC

Watchdog Timer

TCE

RTCC signal Edge :
0

Increment on low-to-high transition on RTCC pin

Increment on high-to-low transition on RTCC pin

TCS

RTCC signal set :
0

Internal instruction cycle clock

Transition on RTCC pin

(10) CPIO A, CPIO B (Control Port I/O Mode Register)

The CPIO register is "write-only"

"0", I/O pin in output mode;

"1", I/O pin in input mode.

(11) EPROM Option by writer programming :
A. FIRST WORD

Oscillator Type

Oscillator Start-up Time

RC Oscillator

150

LFXT Oscillator

20 ms

XTAL Oscillator

40 ms

HFXT Oscillator

80 ms

Watchdog Timer control

Watchdog timer disable all the time

Watchdog timer enable all the time

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 8

2005/6 Ver. 1.4

Power Edge Detect

Security bit

PED Disable

Security Disable

PED Enable

Security Enable

(B) Program Memory

Address

Description

000- 3FF

Program memory

3FF

The starting address of the power on, external reset
or WDT

8. Reset Condition for all Registers

Address

Power-On Reset /MCLR Reset

WDT Reset

CPIO A

1111 1111

CPIO B

1111 1111

TMR

--11 1111

IAR

00h

RTCC

01h

xxxx xxxx

uuuu uuuu

02h

1111 1111

STATUS

03h

0001 1xxx

000# #uuu

MSR

04h

100x xxxx

100u uuuu

1uuu uuuu

PORT A

05h

xxxx xxxx

uuuuuuuu

uuuu uuuu

PORT B

06h

xxxx xxxx

uuuu uuuu

CMR

07h

0000 0000

uuuu uuuu

Note : u

unchanged, x

unknown, -

unimplemented, read as "0"

value depends on the condition of the following table

Condition

Status: bit 4

Status: bit 3

/MCLR reset (not during SLEEP)

/MCLR reset during SLEEP

WDT reset (not during SLEEP)

WDT reset during SLEEP

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 9

2005/6 Ver. 1.4

9. Instruction Set

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010000
00000000

NOP

No operation

None

010000
00000001

CLRWT

Clear Watchdog timer

TF, PF

010000
00000010

SLEEP

Sleep mode

WT, stop OSC

TF, PF

010000
00000011

TMODE

Load W to TMODE register W

TMODE

None

010000
00000100

RET

Return

Stack

None

010000 00000rrr CPIO R

Control I/O port register

CPIO r

None

010001 1rrrrrrr STWR R Store W to register W

None

011000 trrrrrrr

LDR R, t

Load register R

111010 iiiiiiii

LDWI I

Load immediate to W I

None

010111 trrrrrrr

SWAPR R, t Swap halves register [R(0~3)

R(4~7)]

None

011001 trrrrrrr

INCR R, t Increment register

R + 1

011010 trrrrrrr

INCRSZ R, t Increment register, skip if

zero

R + 1

None

011011 trrrrrrr

ADDWR R, t Add W and register

W + R

C, HC, Z

011100 trrrrrrr

SUBWR R, t Subtract W from register

(R+/W+1

C, HC, Z

011101 trrrrrrr

DECR R, t Decrement register

011110 trrrrrrr

DECRSZ R,
t

Decrement register, skip if
zero

None

010010 trrrrrrr

ANDWR R, t AND W and register

110100 iiiiiiii

ANDWI i

AND W and immediate

010011 trrrrrrr

IORWR R, t Inclu. OR W and register

110101 iiiiiiii

IORWI i

Inclu. OR W and immediate i

010100 trrrrrrr

XORWR R, t Exclu. OR W and register

110110 iiiiiiii

XORWI i

Exclu. OR W and immediate i

011111 trrrrrrr

COMR R, t Complement register

010110 trrrrrrr

RRR R, t Rotate right register R(n)

R(n-1), C

R(7), R(0)

Instruction Code

Mnemonic

Operands

Function

Operating

Status

MDT10P22(BE)

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P. 10

2005/6 Ver. 1.4

010101 trrrrrrr

RLR R, t Rotate left register R(n)

r(n+1),

R(0), R(7)

010000 1xxxxxxx CLRW

Clear working register

010001 0rrrrrrr CLRR R Clear register 0

0000bb brrrrrrr BCR R, b Bit clear

R(b)

None

0010bb brrrrrrr BSR R, b Bit set

R(b)

None

0001bb brrrrrrr BTSC R, b Bit Test, skip if clear

Skip if R(b)=0 None

0011bb brrrrrrr BTSS R, b Bit Test, skip if set

Skip if R(b)=1 None

100nnn nnnnnnnn LCALL n

Long CALL subroutine

PC, PC+1

Stack

None

101nnn nnnnnnnn LJUMP n Long JUMP to address

None

110000 nnnnnnnn CALL n

Call subroutine n

PC, PC+1

Stack

None

110001 iiiiiiii

RTWI i

Return, place immediate to
W

Stack

PC,i

None

11001n nnnnnnnn JUMP n JUMP to address

None

Note :

: Working register b :

Bit position

: Watchdog timer

t :

Target

TMODE : TMODE mode register

Working register

CPIO

: Control I/O port register

1 :

General register

: Timer overflow flag

R :

General register address

: Power loss flag

C :

Carry flag

: Program Counter

HC :

Half carry

OSC

: Oscillator

Zero flag

Inclu.

: Inclusive `

Complement

Exclu.

: Exclusive `

Don't care

AND

: Logic AND `

Immediate data ( 8 bits )

Immediate address

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 11

2005/6 Ver. 1.4

10. Electrical Characteristics

(Operating temperature at 25

Sym

Description

Condition

Min

Typ

Max Unit

Vdd Operating voltage

2.3

5.5

Input Low Voltage

PA, PB
RTCC, /MCLR

Vdd=5V
Vdd=5V

-0.6
-0.6

1.0
1.0

V
V

Input high Voltage

PA, PB
RTCC, /MCLR

Vdd=5V
Vdd=5V

2.0
3.2

Vdd
Vdd

V
V

Input leakage current

Vdd=5V

+/-1

µA

Output Low Voltage

PA, PB

Vdd=5V, I

=20mA

Vdd=5V, I

=5mA

0.4
0.1

V
V

Output High Voltage

PA, PB

Vdd=5V, I

= -20mA

Vdd=5V, I

= -5mA

3.8
4.5

V
V

slp

Sleep current (WDT disable)

2.3 ~ 5.5 V

0.1

1.0

slp

Sleep current (WDT enable)

2.3 V

3.0 V

4.0 V

5.0 V

5.5 V

1
3
8

17
25

Power Edge-detector Reset

Voltage

1.1

1.3

Twdt The basic WDT time-out cycle

time

2.3 V

3.0 V

4.0 V

5.0 V

5.5 V

25.6
22.4
19.6
17.6
16.9

mS
mS
mS
mS

FLT

/MCLR filter

5.0 V

600

Icc Comparator Supply current (one

comparator)

Vdd=5.0v

Vref Input reference voltage

Vdd=2.5v ~5.5v

Vdd-0.8

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 12

2005/6 Ver. 1.4

Sym

Description

Condition

Min

Typ

Max Unit

---

Comparator Response time
V-=Vdd/4, V+=V- ± 0.2v
V-=Vdd/2, V+=V- ± 0.2v
V-=Vdd3/4, V+=V- ± 0.2v
V-=VDD-0.8,V+=V± 0.2v

Vdd=5.0v , V- = Vref
V+ = (PA0~PA3)

8
8
8
8

11. Operating Current

Temperature

, the typical value as followings :

11.1 OSC Type

RC ; WDT

Enable; Comparator Disable

PED=Disable

Vdd=5.0V

Cext. (F)

Rext. (Ohm)

Frequency (Hz)

Current (A)

4.7 K

11.88M

1.65 mA

10.0 K

5.98M

900

47.0 K

1.34M

295

100.0 K

640K

205

300.0 K

217.2K

145

470.0 K

136K

135

4.7 K

5.6M

860

10.0 K

2.78M

500

20P

47.0 K

622.4K

210

100.0 K

297.2K

160

300.0 K

100.8K

135

470.0 K

63.2K

130

4.7 K

1.85M

365

10.0 K

916K

235

100P

47.0 K

201.6K

145

100.0 K

95.6K

130

300.0 K

32.4K

125

470.0 K

20.3K

120

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 13

2005/6 Ver. 1.4

Cext. (F)

Rext. (Ohm)

Frequency (Hz)

Current (A)

4.7 K

710.4K

210

10.0 K

352K

160

300P

47.0 K

75.8K

125

100.0 K

36K

120

300.0 K

12.2K

115

470.0 K

7.6K

110

11.2 OSC Type

LF (OSC1&OSC2 External Cap about 20P); WDT

Disable ;

Comparator

Disable

PED=Enable

Voltage/Frequency 32 K(Ext 30P)

455 K

1 M

Sleep

2.1 V

3.5

1.0

3.0 V

8.5

1.0

4.0 V

110

1.0

5.0 V

120

165

1.0

5.5 V

105

155

205

11.3 OSC Type

XT (OSC1&OSC2 External Cap about 20P); WDT

Enable ;

Comparator

Disable

PED=Enable

Voltage/Frequency

1 M

4 M

10 M

Sleep

2.1 V

155

340

1.0

3.0 V

125

290

580

4.0 V

235

470

890

5.0 V

410

710

1.3mA

5.5 V

500

845

1.5mA

11.4 OSC Type

HF (OSC1&OSC2 External Cap about 20P); WDT

Enable ;

Comparator

Disable

Voltage/Frequency

4 M

10 M

20 M

Sleep

2.3 V

190

400

700

1.0

3.0 V

325

625

1.2mA

4.0 V

530

960

1.7mA

5.0 V

820

1.5mA

2.6mA

5.5 V

1.1mA

1.7mA

3.1mA

MDT10P22(BE)

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P. 14

2005/6 Ver. 1.4

11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V

5.0 V

2.1~2.2 V

(Power Supply)

12. Port A Equivalent Circuit

PA0-PA3

I/O

Control

Write

Data

Bus

Rea

Data O/P

Latch

I/O

Control

Latch

C
K

Q
B

Input Resistor

Port I/O

Data I/P

Latch

VREF

Compartor Control

comparator level

TTL input level

MDT10P22(BE)

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P. 15

2005/6 Ver. 1.4

PA4

I/O

Control

Write

Data

Bus

Rea

Data O/P

Latch

I/O

Control

Latch

C
K

Q
B

Input Resistor

Port I/O

Data I/P

Latch

TTL Input Level

Vref

S0 S1

CMR_4
CMR_5

3/4

VDD

1/2

VDD

1/4

VDD

comparator

enable

PA5-PA7

I/O

Control

Write

Data

Bus

Rea

Data O/P

Latch

I/O

Control

Latch

C
K

Q
B

Input Resistor

Port I/O

Data I/P

Latch

TTL Input Level

MDT10P22(BE)

This specification are subject to be changed without notice. Any latest information

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P. 18

2005/6 Ver. 1.4

14. External Capacitor Selection For Crystal Oscillator

@ V

5.0 V

Osc. Type

Resonator Freq.

Capacity Range

20 MHz

10 pF ~ 50 pF

10 MHz

20 pF ~ 50 pF

4 MHz

10 pF ~ 30 pF

10 MHz

10 pF ~ 50 pF

4 MHz

10 pF ~ 50 pF

1 MHz

20 pF ~50 pF

1 MHz

20 pF ~ 30 pF

455 K

20 pF ~30 pF

32 K

20 pF ~30 pF

MDT10P22

OSC1

OSC2

To increase the stability of oscillator and the ability of anti-noise, the above values of the external
capacitor are for reference only, but the higher capacitance also increases the start-up time.

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