MDT10P41A1
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
1 of 11 2005/6 Ver.1.6
1. General Description
This EPROM-Based 8-bit Micro-controller uses a
fully static CMOS technology to achieve high
speed, small size, low power and high noise
immunity. Internal RC oscillator
On chip memory includes 1K words of EPROM,
and 31 bytes of static RAM.
2. Features
u
Fully CMOS static design
u
8-bit data bus
u
On chip ROM size :1 K words
u
Internal RAM size : 31 bytes
(25 general purpose registers, 6 special
registers)
u
34 single word instructions
u
14-bit instructions
u
2-level stacks
u
Operating voltage : 2.3V ~ 5.5 V
u
Addressing modes include direct, indirect
and relative addressing modes
u
Power-on Reset
u
Internal RC oscillator : 6.5MHz ~ 7.5MHz
u
12 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT10P41A1 range
from appliance motor control and high speed
automotive to low power remote
transmitters/receivers, pointing devices, and
telecommunications processors, such as Remote
controller, small instruments, chargers, toy,
automobile and PC peripheral ... etc.
4. Pin Assignment
MDT10P41A1P / MDT10P41A1S
PB4 1
16 PB3
PB5 2
15 PB2
PB6 3
14 PB1
PB7 4
13 PB0
Vdd 5
12 Vss
NC 6
11 PA3
NC 7
10 PA2
PA0 8
9 PA1
MDT10P41A1
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
2 of 11 2005/6 Ver.1.6
5. Block Diagram
Stack Two
Levels
Program Counters
Internal RC
Power on Reset
Power Down Reset
EPROM
102414
Instruction
Register
Instruction
Decoder
Working Register
ALU
RAM
258
Special Register
Control Circuit
Status Register
Port A
Port B
Data
8bit
10 bits
10 bits
14
bits
Port
PB2 ~PB3
D0~D7
Port
PB4 ~PB7
Port
PA0~PA3
4 bits
Port PB0
Port PB1
MDT10P41A1
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
3 of 11 2005/6 Ver.1.6
6. Pin Function Description
Pin Name
I/O
Function Description
PA0
I/O
Open drain ouput pin with 130K ohm pull-high resistor for input.
PA1~PA3
I/O
Port A, TTL input level.
PA1-PA3 are I/O pins with 50K ohm pull-high resistor for input.
PB0
I/O
I/O pin with 10K ohm pull-high resistor for input.
PB1
I/O
Open drain output with 10K ohm pull-high resistor for input.
PB2~PB3
I/O
Port B, TTL input level.
PB2-PB3 are I/O pins with 35K ohm pull-low resistors for input.
PB4~PB7
I/O
Port B, TTL input level
Vdd
Power supply
Vss
Ground
7. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
Unimplemented
02
PC
03
STATUS
04
MSR
05
Port A
06
Port B
07~1F
Internal RAM, General Purpose Register
MDT10P41A1
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
4 of 11 2005/6 Ver.1.6
(1) IAR ( Indirect Address Register) : R0
(2) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K)
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK
(3) STATUS (Status register) : R3
Bit
Symbol
Function
0
1
2
3
4
5
6
--
7
C
HC
Z
PF
----
page 0
----
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
Always read as high
Page select bit :
0 : 000H --- 1FFH
1 : 200H --- 3FFH
General purpose bit
(4) MSR (Memory Select Register) : R4
(5) PORT A : R5
Bit 3-0 : PA0~PA3, I/O Register
6-4 : Always read as high.
7 : Always read as zero.
(6) PORT B : R6
PB7~PB0, I/O Register
(7) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is "write-only"
"0", I/O pin in output mode;
"1", I/O pin in input mode.
MDT10P41A1
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
5 of 11 2005/6 Ver.1.6
(8) EPROM Option by writer programming :
Security bit
Weak Disable
Disable
Enable
The default EPROM security is weak disable.
8. Reset Condition for all Registers
Register
Address
Power-On Reset
CPIO A
1111 1111
CPIO B
1111 1111
IAR
00h
PC
02h
1111 1111
STATUS
03h
0001 1xxx
MSR
04h
111x xxxx
PORT A
05h
- 111 xxxx
PORT B
06h
xxxx xxxx
Note : " x "
unknown, " "
unimplemented, read as "0"
9. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000010
SLEEP
Sleep mode
0
WT,
stop OSC
TF, PF
010000 00000100
RET
Return
Stack
PC
None
010000 00000rrr
CPIO R
Control I/O port register
W
CPIO r
None
010001 1rrrrrrr
STWR R
Store W to register
W
R
None
011000 trrrrrrr
LDR R, t
Load register
R
t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I
W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3)
R(4~7)]
t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1
t
Z
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