MDT10P72
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 1
2005/6 Ver. 1.9
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static
CMOS technology process to achieve higher speed and
smaller size with the low power consumption and high noise
immunity. On chip memory includes 2K words of ROM, and
128 bytes of static RAM.
2. Features
The followings are some of the features on the hardware
and software :
u
Fully CMOS static design
u
8-bit data bus
u
On chip EPROM size : 2.0 K words
u
Internal RAM size : 160 bytes
(128 general purpose registers, 32 special
registers)
u
37 single word instructions
u
14-bit instructions
u
8-level stacks
u
Operating voltage : 2.5 V ~ 5.5 V (PRD Disable)
4.5 V ~ 5.5 V (PRD Enable)
u
Operating frequency : DC ~ 20 MHz
u
The most fast execution time is 200 ns under 20
MHz in all single cycle instructions except the
branch instruction
u
Addressing modes include direct, indirect and
relative addressing modes
u
Power-on Reset
u
Power edge-detector Reset
u
Power range-detector Reset
u
Sleep Mode for power saving
u
Capture,Compare,PWM module
u
Synchronous serial port with SCM
u
8 interrupt sources:
-External INT pin
-TMR0 timer,TMR1 timer,TMR2 timer
-A/D conversion completion
-PortB<7:4> interrupt on change
-CCP,SCM
u
A/D converter module:
-5 analog inputs multiplexed into one A/D
converter
-8-bit resolution
u
TMR0 : 8-bit real time clock/counter
TMR1 : 16-bit real time clock/count
TMR2 : 8-bit clock/counter(internal)
u
4 types of oscillator can be selected by
programming option:
RC
Low cost RC oscillator
LFXT
Low frequency crystal oscillator
XTAL
Standard crystal oscillator
HFXT
High frequency crystal oscillator
u
On-chip RC oscillator based Watchdog Timer(WDT)
u
22 I/O pins with their own independent direction
control
3. Applications
The application areas of this MDT10P72 range from
appliance motor control and high speed auto-motive to low
power remote transmitters/receivers, pointing devices, and
telecommunications processors, such as Remote
controller, small instruments, chargers, toy, automobile
and PC peripheral ... etc.
MDT10P72
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 2
2005/6 Ver. 1.9
4. Pin Assignment
/MCLR 1
28 PB7
PA0/AIC0 2
27 PB6
PA1/AIC1 3
26 PB5
PA2/AIC2 4
25 PB4
PA3/AIC3/Vref 5
24 PB3
PA4/RTCC 6
23 PB2
PA5/SS/AIC4 7
22 PB1
V
ss
8
21 PB0/INT
OSC1/CLKIN 9
20 V
dd
OSC2/CLKOUT 10
19 V
ss
PC0/T1OSO/T1CKI 11
18 PC7
PC1/T1OSI 12
17 PC6
PC2/CCP 13
16 PC5/SDO
PC3/SCK 14
15 PC4/SDI
5. Pin Function Description
Pin Name
I/O
Function Description
PA0~PA3,PA5
I/O
Port A, TTL input level / Analog input channel
RTCC/PA4
I/O
Real Time Clock/Counter, Schmitt Trigger input level
Open drain output
PB0~PB7
I/O
Port B, TTL input level / PB0:External interrupt input ,
PB4~PB7:Interrupt on pin change
PC0~PC7
I/O
Port C, Schmitt Trigger input level
/MCLR
I
Master Clear, Schmitt Trigger input level
OSC1/CLKIN
I
Oscillator Input/external clock input
OSC2/CLKOUT
O
Oscillator Output/in RC mode
the CLKOUT pin has 1/4 frequency
of CLKIN
V
dd
Power supply
V
ss
Ground
MDT10P72
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 4
2005/5 Ver. 1.8
Address
Description
07
CPIO C
0C
PIEB1
0E
PSTA
12
T2PER
14
SCMSTA
1F
ADS1
A0~BF
General purpose register
(1) IAR ( Indirect Address Register) : R00
(2) RTCC (Real Time Counter/Counter Register) : R01
(3) PC (Program Counter) : R02,R0A
Write PC --- from PCHLAT
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register) : R03
Bit
Symbol
Function
0
1
2
3
4
5
7-6
C
HC
Z
PF
TF
RBS0
----
Carry bit
Half Carry bit
Zero bit
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit :
0 : 00H --- 7FH (Bank0)
1 : 80H --- FFH (Bank1)
General purpose bit
MDT10P72
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 5
2005/5 Ver. 1.8
(5) MSR (Memory Bank Select Register) : R04
Memory Bank Select Register :
0 : 00~7F (Bank0)
1 : 80~FF (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A : R05
PA5~PA0, I/O Register
(7) PORT B : R06
PB7~PB0, I/O Register
(8) PORT C : R07
PC7~PC0, I/O Register
(9)PCHLAT: R0A
(10) INTS ( Interrupt Status Register ) : R0B
Bit
Symbol
Function
0
RBIF
PORT B change interrupt flag. Set when PB <7:4> inputs change
1
INTF
Set when INT interrupt occurs. INT interrupt flag.
2
TIF
Set when TMR0 overflows.
3
RBIE
0 : disable PB change interrupt
1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt
1 : enable INT interrupt
5
TIS
0 : disable TMR0 interrupt
1 : enable TMR0 interrupt
6
PEIE
0 : disable all peripheral interrupt
1 : enable all peripheral interrupt
7
GIS
0 : disable global interrupt
1 : enable global interrupt
PDF 
ZIP