TH8055
Single Wire CAN Transceiver
TH8055
-
Datasheet
Page
1
of
18
3901008055
September 2002
Rev. 002
Features and Benefits
Fully compatible with J2411 Single Wire CAN specification for Class B in vehicle
communications
30 A typical power consumption in sleep mode independent from CAN voltage range
Operating voltage range 5...18V
Up to 100 kbps high-speed transmission mode
Up to 40 kbps bus speed
Selective BUS wakeup
Low RFI due to output wave shaping
Fully integrated receiver filter
Bus terminals proof against short-circuits and transients in automotive environment
Loss of ground protection
Protection against load dump, jump start
Thermal overload and short circuit protection
ESD protection of 4 kV on CAN pin (2kV on any other pin)
Undervoltage lock out
Bus dominant timeout feature
Ordering Information
Part
No.
Temperature
Range
Package
TH8055 J
(-40
to
125
C) DC
(SOIC8)
General Description
The TH8055 is a physical layer device for a single wire data link capable of operating with various CSMA/CR protocols
such as the Bosch Controller Area Network (CAN) version 2.0. This serial data link network is intended for use in
applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical
media components and in the microprocessor and/or dedicated logic devices which use the network.
The network shall be able to operate in either the normal data rate mode or a high speed data download mode for
assembly line and service data transfer operations. The high speed mode is only intended to be operational when the
bus is attached to an off-board service node. This node shall provide temporary bus electrical loads which facilitate
higher speed operation. Such temporary loads shall be removed when not performing download operations.
The bit rate for normal communications is typically 33 kbit/s, for high speed transmissions like described above a typical
bit rate of 83 kbit/s is recommended. The TH8055 is designed in accordance to the Single Wire CAN Physical Layer
Specification GMW3089 V1.26 and supports many additional features like undervoltage lockout, timeout for faulty
blocked input signals, output blanking time in case of bus ringing and a very low sleep mode current.
TH8055
Single Wire CAN Transceiver
TH8055
-
Datasheet
Page
2
of
18
3901008055
September 2002
Rev. 002
Contents
1.
Functional Diagram................................................................................................ 3
2.
Functional Description........................................................................................... 4
2.1
TxD Input Pin ........................................................................................................................................ 4
2.2
Mode 0 and Mode 1 pins ...................................................................................................................... 4
2.3
RxD Output pin...................................................................................................................................... 5
2.4
Bus LOAD pin ....................................................................................................................................... 5
2.5
VBAT INPUT pin ................................................................................................................................ 6
2.6
CAN BUS input/output pin .................................................................................................................... 6
3.
Electrical Specification .......................................................................................... 7
3.1
Operating Conditions ............................................................................................................................ 7
3.2
Absolute Maximum Ratings .................................................................................................................. 7
3.3
Static Characteristics ............................................................................................................................ 8
3.4
Dynamic Characteristics ..................................................................................................................... 10
3.5
Bus loading requirements ................................................................................................................... 11
3.6
Timing Diagrams................................................................................................................................. 12
4.
Application Circuitry ............................................................................................ 14
5.
Pin Description ..................................................................................................... 15
6.
Mechanical Specification..................................................................................... 16
7.
Reliability Information.......................................................................................... 17
8.
Disclaimer ............................................................................................................. 17
TH8055
Single Wire CAN Transceiver
TH8055
-
Datasheet
Page
3
of
18
3901008055
September 2002
Rev. 002
1.
1.
1.
1. Functional Diagram
Functional Diagram
Functional Diagram
Functional Diagram
TxD
MODE0
RxD
CANH
MODE
CONTROL
MODE1
Time Out
Wave Shaping
CAN Driver
Reverse
Current
Protection
Biasing and
V
BAT
Monitor
V
BAT
5V Supply
and
References
Reverse
Current
Protection
Feedback
Loop
Loss of
Ground
Detection
Receive
Comparator
Input Filter
RC-Osc
TH8055
RxD Blanking
Time Filter
GND
LOAD
Figure 1- Block Diagram
TH8055
Single Wire CAN Transceiver
TH8055
-
Datasheet
Page
4
of
18
3901008055
September 2002
Rev. 002
2.
2.
2.
2. Functional Description
Functional Description
Functional Description
Functional Description
2.1 TxD Input Pin
TxD Polarity
TxD = logic 1 (or floating) on this pin produce an undriven or recessive bus state (low bus voltage)
TxD = logic 0 on this pin produce either a bus normal or a bus high voltage dominant state depending on the
transceiver mode state (high bus voltage)
If the TxD pin is driven to a logic low state while the sleep mode (Mode0=0 and Mode1=0) is activated, the
transceiver not drive the CANH pin to the dominant state.
The transceiver provides an internal pull up current on the TxD pin which will cause the transmitter to default
to the bus recessive state when TxD is not driven.
TxD input signals are standard CMOS logic levels.
Timeout Feature
In case of a faulty blocked dominant TxD input signal the CANH output is switched off automatically after the
specified TxD timeout reaction time to prevent a dominant bus.
The transmission is continued by next TxD L to H transition without delay.
2.2 Mode 0 and Mode 1 pins
The transceiver provides a weak internal pull down current on each of these pins which causes the
transceiver to default to sleep mode when they are not driven. The mode input signals are standard CMOS
logic level.
M0
M1
Mode
L
L
Sleep mode
H
L
High speed mode
L
H
Wake up
H
H
Normal mode
Sleep Mode
Transceiver is in low power state, waiting for wake up via high voltage signal or by mode pins change to any
state other than 0,0. In this state, the CANH pin is not in the dominant state regardless of the state of the
TxD pin.
High Speed Mode
This mode allows high speed download with bitrates up to 100Kbit/s. The output waveshaping circuit is
disabled in this mode. Bus transmitter drive circuits for those nodes which are required to communicate in
high speed mode are able to drive reduced bus resistance in this mode (see Table Static Characteristics).
High speed communications shall utilize the normal mode signal voltage levels as specified in Static
Characteristics.
TH8055
Single Wire CAN Transceiver
TH8055
-
Datasheet
Page
5
of
18
3901008055
September 2002
Rev. 002
Wake Up Mode
This bus includes a selective node awake capability, which allows normal communication to take place
among some nodes while leaving the other nodes in an undisturbed sleep state. This is accomplished by
controlling the signal voltages such that all nodes must wake up when they receive a higher voltage
message signal waveform. The communication system communicates to the nodes information as to which
nodes are to stay operational (awake) and which nodes are to put themselves into a non communicating low
power "sleep" state. Communication at the lower, normal voltage levels shall not disturb the sleeping nodes.
Normal mode
Transmission bit rate in normal communication is 33 Kbits/s. In normal transmission mode the TH8055
supports controlled waveform rise and overshoot times. Waveform trailing edge control is required to assure
that high frequency components are minimized at the beginning of the downward voltage slope. The
remaining fall time occurs after the bus is inactive with drivers off and is determined by the RC time constant
of the total bus load.
2.3 RxD Output pin
RxD polarity
RxD = logic 1 on this pin indicates a bus recessive state (low bus voltage)
RxD = logic 0 on this pin indicates a bus normal or high voltage bus dominant state
RxD in Sleep Mode
RxD do not pass signals to the micro processor while in sleep mode until a valid wake up bus voltage level is
received or the Mode 0,1 pins are not 0,0 respectively. When the valid wake up bus voltage signal awakens
the transceiver, the RxD pin signalised an interrupt (logic 0). However, if the Mode 0 & 1 pins are at logic 0,
the transceiver returns to the sleep condition when the wake up bus voltage signal is not present.
When not in sleep mode all valid bus signals will be sent out on the RxD pin.
RxD will be placed in the undriven or off state when in sleep mode.
RxD Typical Load
Resistance: 2.7 kOhm
Capacitance: < 25 pF
2.4
Bus LOAD pin
Resistor ground with internal open-on-loss-of-ground protection
When the ECU experiences a loss of ground condition, this pin is switched to a high impedance state.
The ground connection through this pin is not interrupted in any transceiver operating mode including the
sleep mode. The ground connection only is interrupted when there is a valid loss of ground condition.
This pin provides the bus load resistor with a path to ground which contributes less than 0.1 volts to the bus
offset voltage when sinking the maximum current through one unit load resistor.
The transceiver's maximum bus leakage current contribution to VOL from the LOAD pin when in a loss of
ground state is 50uA over all operating temperatures and 3.5 < VBAT < 18 volts .
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