May 2005
1
M9999-051305
KS8995MA
Micrel, Inc.
KS8995MA
Integrated 5-Port 10/100 Managed Switch
Rev 2.4
General Description
The KS8995MA is a highly integrated Layer 2 managed
switch with optimized bill of materials (BOM) cost for low port
count, cost-sensitive 10/100Mbps switch systems. It also
provides an extensive feature set such as tag/port-based
VLAN, quality of service (QoS) priority, management, MIB
counters, dual MII interfaces and CPU control/data interfaces
to effectively address both current and emerging Fast Ether-
net applications.
The KS8995MA contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five media access
control (MAC) units, a high-speed non-blocking switch fabric,
a dedicated address lookup engine, and an on-chip frame
buffer memory.
All PHY units support 10BASE-T and 100BASE-TX.
In addition, two of the PHY units support 100BASE-FX
(ports 4 and 5).
Features
Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
Shared memory based switch fabric with fully non-
blocking configuration
1.4Gbps high-performance memory bandwidth
10BASE-T, 100BASE-TX, and 100BASE-FX modes
(FX in ports 4 and 5)
Dual MII configuration: MII-Switch (MAC or PHY mode
MII) and MII-P5 (PHY mode MII)
IEEE 802.1q tag-based VLAN (16 VLANs, full-range
VID) for DMZ port, WAN/LAN separation or inter-VLAN
switch links
VLAN ID tag/untag options, per-port basis
Programmable rate limiting 0Mbps to 100Mbps, ingress
and egress port, rate options for high and low priority,
per-port basis in 32Kbps increments
Flow control or drop packet rate limiting (ingress port)
Integrated MIB counters for fully compliant statistics
gathering, 34 MIB counters per port
Micrel, Inc. 2180 Fortune Drive San Jose, CA 95131 USA tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com
Functional Diagram
1K Look-Up
Engine
Queue
Mgmnt
10/100
MAC 1
Buffer
Mgmnt
Frame
Buffers
FIFO, Flow Contro
l, VLAN
Ta
g
ging, Pri
ority
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
SPI
EEPROM
I/F
LED I/F
Auto
MDI/MDI-X
Control Reg I/F
KS8995MA
MIB
Counters
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MII-P5
MDC, MDI/O
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
KS8995MA
Micrel, Inc.
M9999-051305
2
May 2005
Features
(continued)
Enable/Disable option for huge frame size up to 1916
bytes per frame
IGMP v1/v2 snooping for multicast packet filtering
Special tagging mode to send CPU info on ingress
packet's port value
SPI slave (complete) and MDIO (MII PHY only) serial
management interface for control of register configura-
tion
MAC-id based security lock option
Control registers configurable on-the-fly (port-priority,
802.1p/d/q, AN...)
CPU read access to MAC forwarding table entries
802.1d Spanning Tree Protocol
Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port or MII
Broadcast storm protection with % control global and
per-port basis
Optimization for fiber-to-copper media conversion
Full-chip hardware power-down support (register
configuration not saved)
Per-port based software power-save on PHY (idle link
detection, register configuration preserved)
QoS/CoS packets prioritization supports: per port,
802.1p and DiffServ based
802.1p/q tag insertion or removal on a per-port basis
(egress)
MDC and MDI/O interface support to access the MII
PHY control registers (not all control registers)
MII local loopback support
On-chip 64Kbyte memory for frame buffering (not
shared with 1K unicast address table)
Wire-speed reception and transmission
Integrated look-up engine with dedicated 1K MAC
addresses
Full duplex IEEE 802.3x and half-duplex back pressure
flow control
Comprehensive LED support
7-wire SNI support for legacy MAC interface
Automatic MDI/MDI-X crossover for plug-and-play
Disable automatic MDI/MDI-X option
Low power:
Core: 1.8V
I/O: 2.5V or 3.3V
0.18m CMOS technology
Commercial temperature range: 0C to +70C
Industrial temperature range: 40C to +85C
Available in 128-pin PQFP package
Applications
Broadband gateway/firewall/VPN
Integrated DSL or cable modem multi-port router
Wireless LAN access point plus gateway
Home networking expansion
Standalone 10/100 switch
Hotel/campus/MxU gateway
Enterprise VoIP gateway/phone
FTTx customer premise equipment
Managed Media converter
Ordering Information
Part Number
Temp. Range
Package
Lead Finish
KS8995MA
0C to +70C
128-Pin PQFP
Standard
KSZ8995MA
0C to +70C
128-Pin PQFP
Lead-Free
KS8995MAI
40C to +85C
128-Pin PQFP
Standard
May 2005
3
M9999-051305
KS8995MA
Micrel, Inc.
Revision History
Revision
Date
Summary of Changes
2.0
10/10/03
Created.
2.1
10/30/03
Editorial changes on electrical characteristics.
2.2
4/1/04
Editorial changes on the TTL input and output electrical characteristics.
2.3
1/19/05
Insert recommended reset circuit., Pg. 70. Editorial, Pg. 36
2.4
4/13/05
Changed VDDIO to 3.3V.
Changed Jitter to 16 ns Max.
KS8995MA
Micrel, Inc.
M9999-051305
4
May 2005
Table of Contents
System Level Applications ......................................................................................................................................... 7
Pin Description by Number ........................................................................................................................................ 9
Pin Description by Name .......................................................................................................................................... 15
Pin Configuration ...................................................................................................................................................... 21
Introduction
........................................................................................................................................................... 22
Functional Overview: Physical Layer Transceiver ............................................................................................... 22
100BASE-TX Transmit ........................................................................................................................................ 22
100BASE-TX Receive ......................................................................................................................................... 22
PLL Clock Synthesizer ......................................................................................................................................... 22
Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 22
100BASE-FX Operation ....................................................................................................................................... 22
100BASE-FX Signal Detection ............................................................................................................................ 22
100BASE-FX Far End Fault ................................................................................................................................ 23
10BASE-T Transmit ............................................................................................................................................. 23
10BASE-T Receive .............................................................................................................................................. 23
Power Management ............................................................................................................................................. 23
MDI/MDI-X Auto Crossover ................................................................................................................................. 23
Auto-Negotiation .................................................................................................................................................. 23
Functional Overview: Switch Core ......................................................................................................................... 24
Address Look-Up ................................................................................................................................................. 24
Learning
........................................................................................................................................................... 24
Migration
........................................................................................................................................................... 24
Aging
........................................................................................................................................................... 24
Forwarding ........................................................................................................................................................... 24
Switching Engine ................................................................................................................................................. 24
MAC Operation .................................................................................................................................................... 24
Inter-Packet Gap (IPG) ................................................................................................................................ 24
Backoff Algorithm ......................................................................................................................................... 24
Late Collision ................................................................................................................................................ 26
Illegal Frames .............................................................................................................................................. 26
Flow Control ................................................................................................................................................. 26
Half-Duplex Back Pressure .......................................................................................................................... 26
Broadcast Storm Protection ......................................................................................................................... 26
MII Interface Operation ........................................................................................................................................ 26
SNI Interface Operation ....................................................................................................................................... 28
Advanced Functionality ............................................................................................................................................ 28
Spanning Tree Support ........................................................................................................................................ 28
Special Tagging Mode ......................................................................................................................................... 29
IGMP Support ...................................................................................................................................................... 30
Port Mirroring Support ......................................................................................................................................... 31
VLAN Support ...................................................................................................................................................... 31
Rate Limit Support ............................................................................................................................................... 32
Configuration Interface ........................................................................................................................................ 33
I
2
C Master Serial Bus Configuration ............................................................................................................ 35
SPI Slave Serial Bus Configuration ............................................................................................................. 35
MII Management Interface (MIIM) ....................................................................................................................... 38
May 2005
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M9999-051305
KS8995MA
Micrel, Inc.
Register Description ................................................................................................................................................. 39
Global Registers .................................................................................................................................................. 39
Register 0 (0x00): Chip ID0 ......................................................................................................................... 39
Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39
Register 2 (0x02): Global Control 0 ............................................................................................................. 40
Register 3 (0x03): Global Control 1 ............................................................................................................. 40
Register 4 (0x04): Global Control 2 ............................................................................................................. 41
Register 5 (0x05): Global Control 3 ............................................................................................................. 42
Register 6 (0x06): Global Control 4 ............................................................................................................. 42
Register 7 (0x07): Global Control 5 ............................................................................................................. 43
Register 8 (0x08): Global Control 6 ............................................................................................................. 43
Register 9 (0x09): Global Control 7 ............................................................................................................. 43
Register 10 (0x0A): Global Control 8 ........................................................................................................... 43
Register 11 (0x0B): Global Control 9 ........................................................................................................... 43
Port Registers ...................................................................................................................................................... 44
Register 16 (0x10): Port 1 Control 0 ........................................................................................................... 44
Register 17 (0x11): Port 1 Control 1 ........................................................................................................... 44
Register 18 (0x12): Port 1 Control 2 ........................................................................................................... 45
Register 19 (0x13): Port 1 Control 3 ........................................................................................................... 46
Register 20 (0x14): Port 1 Control 4 ........................................................................................................... 46
Register 21 (0x15): Port 1 Control 5 ........................................................................................................... 46
Register 22 (0x16): Port 1 Control 6 ........................................................................................................... 46
Register 23 (0x17): Port 1 Control 7 ........................................................................................................... 46
Register 24 (0x18): Port 1 Control 8 ........................................................................................................... 47
Register 25 (0x19): Port 1 Control 9 ........................................................................................................... 47
Register 26 (0x1A): Port 1 Control 10 ......................................................................................................... 47
Register 27 (0x1B): Port 1 Control 11 ......................................................................................................... 47
Register 28 (0x1C): Port 1 Control 12 ......................................................................................................... 48
Register 29 (0x1D): Port 1 Control 13 ......................................................................................................... 49
Register 30 (0x1E): Port 1 Status 0 ............................................................................................................ 49
Register 31 (0x1F): Port 1 Control 14 ......................................................................................................... 50
Advanced Control Registers ................................................................................................................................ 50
Register 96 (0x60): TOS Priority Control Register 0 ................................................................................... 50
Register 97 (0x61): TOS Priority Control Register 1 ................................................................................... 50
Register 98 (0x62): TOS Priority Control Register 2 ................................................................................... 50
Register 99 (0x63): TOS Priority Control Register 3 ................................................................................... 50
Register 100 (0x64): TOS Priority Control Register 4 ................................................................................. 50
Register 101 (0x65): TOS Priority Control Register 5 ................................................................................. 50
Register 102 (0x66): TOS Priority Control Register 6 ................................................................................. 50
Register 103 (0x67): TOS Priority Control Register 7 ................................................................................. 50
Register 104 (0x68): MAC Address Register 0 ........................................................................................... 50
Register 105 (0x69): MAC Address Register 1 ........................................................................................... 50
Register 106 (0x6A): MAC Address Register 2 .......................................................................................... 51
Register 107 (0x6B): MAC Address Register 3 .......................................................................................... 51
Register 108 (0x6C): MAC Address Register 4 .......................................................................................... 51
Register 109 (0X6D): MAC Address Register 5 .......................................................................................... 51
Register 110 (0x6E): Indirect Access Control 0 .......................................................................................... 51
Register 111 (0x6F): Indirect Access Control 1 .......................................................................................... 51
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