The MIC1832 is a multifunction circuit which monitors
microprocessor activity, external reset and power
supplies in microprocessor based systems. The circuit
functions include a watchdog timer, power supply
monitor, microprocessor reset, and manual pushbutton
reset input.

The power supply line is monitored with a comparator
and an internal voltage reference. RST is forced low
when an out-of-tolerance condition exists and remains
asserted for at least 250ms after V

rises above the

threshold voltage (2.55V or 2.88V). The RST pin will
remain logic low with V

as low as 1.4V.

The Watchdog input (ST) monitors

P activity and will

assert RST if no

P activity has occurred within the

watchdog timeout period. The watchdog timeout period
is selectable with a nominal periods of 150, 600, or
1200 milliseconds.

TOL

GND

RST

MIC1832

PBRST

MIC1832N - 8 Lead Plastic DIP Package
MIC1832M - 8 Lead Plastic SOIC Package

Part

Package

Temp. Range

MIC1832N

8-Lead PDIP

-40°C to +85°C

MIC1832M

8-Lead SOIC

-40°C to +85°C

Automotive Systems

Intelligent Instruments

Critical Microprocessor Power Monitoring

Battery Powered Computers

Controllers

Power OK/Reset Time Delay, 250ms min.

Watchdog Timer, 150ms, 600ms, or

1.2s typical

Precision Supply Voltage Monitor, Select

Between 5% or 10% of Supply Voltage

Available in 8-pin Surface Mount (SO)

Debounced External Reset Input

Low Supply Current,

A Typ.

VCC

RST

µP

RESET

VCC

MIC1832

VCC

PBRST

TOL GND

I/O

Typical Operating Circuit

Features

Description

Pin Configuration

Ordering Information

Typical Applications

Top View

MIC1832 µP Supervisory Circuit

MIC1832

µP Supervisory Circuit

MIC1832

P Supervisory Circuit

Electrical Characteristics

VCC = 3 to 5.5 V, T

= Operating Temperature Range, unless otherwise noted.

Parameter

Conditions

Min

Typ

Max

Units

Supply Voltage Range

VCC

5.5

Supply Current

ICC @ VCC = 5V (See Note 1)

ICC @ VCC = 3.3V (See Note 1)

ST and PBRST Input Levels

VIH (See Note 2)

2.0

VCC + 0.3

VIH (See Note 3)

VCC - 0.4

VCC + 0.3

VIL

-0.3

0.5

Input Leakage, ST (See Note 4)

IIL

±1

Output Voltage, RST, RST

ISOURCE = 350

A, VCC = 3.3V

2.4

Output Voltage, RST, RST

ISINK = 10mA, VCC = 3.3V

0.4

Output Voltage, RST

VCC = 1.4V, ISINK = 50

0.3

VCC 5% Trip Point (Reset

TOL = Gnd

2.80

2.88

2.97

Threshold Voltage)

VCC 10% Trip Point (Reset

TOL = VCC

2.47

2.55

2.64

Threshold Voltage)

Input Capacitance, ST, TOL

CIN (See Note 5)

Output Capacitance, RST, RST

COUT (See Note 5)

Absolute Maximum Ratings

Terminal Voltage

VCC, . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.0V

All Other Inputs . . . . . . . . . . . . -0.3V to (VCC + 0.3V)

Input Current

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mA

Gnd, All Other Inputs . . . . . . . . . . . . . . . . . . . . 25mA

Operating Temperature Range

MIC1832_ . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C

Storage Temperature Range . . . . . . . . . . . . .-65°C to 150°C

Lead Temperature (Soldering - 10 sec.) . . . . . . . . . . . 300°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 700mW

Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.

MIC1832

P Supervisory Circuit

Note 1: ICC is measured with PBRST and all outputs open and inputs within 0.5V of supply rails.
Note 2: Measured with VCC

2.7V.

Note 3: Measured with VCC < 2.7V.
Note 4: PBRST has an internal pull-up resistor to VCC (typ. 40k

Note 5: Guaranteed by design at TA = 25

Note 6: PBRST must be held low for a minimum of 20ms to guarantee a reset.
Note 7: VCC falling at 8.5mv/

A.C. Electrical Characteristics

VCC = 3 to 5.5 V, T

= Operating Temperature Range, unless otherwise noted.

Parameter

Conditions

Min

Typ

Max

Units

PBRST Min. Pulse Width, tPB

PBRST = VIL (see note 6)

PBRST Delay, tPBD

Reset Active Time, tRST

250

610

1000

ST Pulse Width, tST

ST Timeout Period, tTD

TD = 0V

62.5

150

250

TD = Open

250

600

1000

TD = VCC

500

1200

2000

VCC Fall Time, tF

VCC Rise Time, tR

VCC Detect to RST Low

VCC Falling (see note 7)

and RST High, tRPD

VCC Detect to RST High

VCC Rising

250

610

1000

and RST Low, tRPU

Pin 1: PBRST - Pushbutton reset input. This input is debounced and can be driven with external logic signals or by

means of a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the
PBRST pin are ignored, whereas, any pulse with a duration of 20ms or greater is guaranteed to cause a
reset. PBRST has an internal pull-up resistor to VCC of 40k

typical.

Pin 2: TD - Time delay input. This input selects the timebase used by the watchdog timer. When TD = 0V, the

watchdog timeout period is set to a nominal value of 150ms and when TD = open, the watchdog timeout
period is set to a nominal value of 600ms and when TD = VCC, the watchdog timeout period is 1.2sec

nominally.

Pin 3: TOL - Tolerance select input. Selects whether 5% or 10% of VCC is used as the reset threshold voltage.

When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10% tolerance level is selected.

Pin 4: GND - IC ground pin, 0V reference.

Pin 5: RST - RST is asserted high if either VCC goes below the reset threshold, the watchdog times out or PBRST is

pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the

reset threshold or after the watchdog times out or after PBRST goes high.

Pin 6: RST - RST is asserted low if either VCC goes below the reset threshold, the watchdog times out or PBRST is

pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the

reset threshold or after the watchdog times out or after PBRST goes high.

Pin 7: ST - Input to the watchdog timer. If ST does not see a transition from high to low within the watchdog timeout

period, RST and RST will be asserted.

Pin 8: VCC - Primary supply input.

Pin Functions

MIC1832

P Supervisory Circuit

+
-

REF

WATCHDOG

TIMER

VCC (8)

GND (4)

RST (5)

TD (2)

RST (6)

RESET

GENERATOR

ST (7)

TIMEOUT

SELECT

PBRST (1)

MANUAL RESET

DEBOUNCE

TRIP POINT

SELECT

TOL (3)

Block Diagram

Table 1. Watchdog Timeout Period

Circuit Description

TD Pin

Min.

Typ.

Max.

Gnd

62.5ms

150ms

250ms

Open

250ms

600ms

1000ms

500ms

1200ms

2000ms

MIC1832

P Supervisory Circuit

Power Monitor
The RST and RST pins are asserted whenever VCC
falls below the reset threshold voltage as determined by
the TOL pin. A 5% tolerance level (2.88V reset
threshold voltage) can be selected by connecting the
TOL pin to ground and a 10% tolerance (2.55V reset
threshold voltage) can be selected by connecting the
TOL pin to VCC. The reset pins will remain asserted for
a period of 250ms after VCC has risen above the reset
threshold voltage. The reset function ensures the
microprocessor is properly reset and powers up into a
known condition after a power failure. RST will remain
valid with VCC as low as 1.4V.

Watchdog Timer
The microprocessor can be monitored by connecting
the ST pin (watchdog input) to a bus line or I/O line. If a
high-to-low transition doesn't occur on the ST pin within
the watchdog timeout period (determined by TD pin, see
Table 1), the RST and RST pins will be asserted
resulting in a microprocessor reset. RST and RST will
remain asserted for at least 250ms when this occurs. A
minimum pulse of 75ns or any transition high-to-low on
the ST pin will reset the watchdog timer. The watchdog
timer will be reset if ST sees a valid transition within the
watchdog timeout period.

Pushbutton Reset Input
The PBRST input can be driven with a manual
pushbutton switch or with external logic signals. The
input is internally debounced and requires an active low
signal to force the reset outputs into their active states.
The PBRST input will recognize any pulse that is 20ms
in duration or greater and will ignore all pulses that are
less than 1ms in duration.

Figure 1. Power-Up/Power-Down Sequence

Circuit Description

456

427

++62

42,

++62

Figure 3. Pushbutton Reset

Figure 2. Watchdog Input

RST

PDLY

PBRST

Note: The maximum time between high-to-low transitions (t

) on the

watchdog input (ST) is determined by the voltage applied to the
TD pin. If the watchdog input sees a high-to-low transition prior to
the timeout period, the watchdog timer will be reset.

MIC1832

P Supervisory Circuit

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