MIC8030
8-16
October 1998
MIC8030
Micrel
General Description
The MIC8030 is a CMOS high voltage liquid crystal display
driver. Up to 38 segments can be driven from four CMOS level
inputs (CLOCK, DATA IN, LOAD and CHIP SELECT). The
MIC8030 is rated at 50V. Data is loaded serially into a shift
register, and transferred to latches which hold the data until
new data is received.
The backplane can be driven from external source, or the
internal oscillator can be used. If the internal oscillator is
used, the frequency of the backplane will be determined by an
external resistor and capacitor. The oscillator need not be
used if a DC output is desired.
Ordering Information
Part Number
Temperature Range Package
MIC8030-01CV
0
C to +70
C
44-pin PLCC
MIC8030
High-Voltage Display Driver
Features
High Voltage Outputs capable of a driving up to 100 volt
outputs from 5 to 15 volt logic
Drives 30, 32, or 38 segments
Cascadable
On chip Oscillator or External Backplane Input
CMOS construction for wide supply range and low
power consumption
Schmitt Triggers on all inputs
CMOS, PMOS, and NMOS compatible
Applications
Dichroic and Standard Liquid Crystal Displays
Flat Panel Displays
Print Head Drives
Vacuum Fluorescent Displays
Functional Diagram
Data
S
Clock
S
CS
S
Load
S
38 Bit Static Shift Register
38 Bit Latch
LCD0
LCD0 Opt
Oscillator
Voltage Translators
Voltage
Translator
HV Output
Driver
Back Plane
HV Output Drivers
Segments
Data Out 38
Data Out 32
Data Out 30
October 1998
8-17
MIC8030
MIC8030
Micrel
8
For displays with more than 38 segments, two or more
MIC8030 may be cascaded by connecting DATA OUT of the
previous stage with DATA IN of the next stage; CLOCK,
LOAD and CHIP SELECT of all following stages should be
tied to the control lines of the first MIC8030. The backplane
output of the first stage should be tied to LCD
of all following
stages, the LCD
OPT must be left unconnected on those
stages. If the internal oscillator is used, and V
BB
> 50V then
an external 330 k
resistor must be used between the
BACKPLANE of the first stage and LCD
of all following
stages.
Packaging options available include DATA OUT 30, 32 or 38
with the corresponding number of segments, and the avail-
ability of LCD
OPT. Types of packages include plastic and
ceramic DIPs, surface mount packages, plastic and ceramic
Leadless Chip Carriers and custom packaging.
Pin Configuration
Functional Description
With CHIP SELECT tied low, serial data is clocked into the
shift register at each falling edge of the CLOCK input. Pulling
LOAD high will cause a parallel loading of the shift register
contents into the latches. If load is left high, the latches are
transparent.
A logic "1" clocked into the shift register corresponds to that
segment being on, and that segment is out of phase with the
backplane.
The backplane may be externally driven or the internal
oscillator can be used. If LCD
is externally driven, the
backplane will be in phase with the input; LCD
OPT is not
connected. The internal oscillator is used by shorting LCD
OPT to LCD
, connecting a capacitor to ground, and a
resistor to V
CC
. The frequency of the backplane will be 1/256
of the input frequency, and is given as: f = 10/[R(C + .0002)]
at V
DD
= 5V, R in k
, C in
F.
Example: R = 150 k
, C = 420 pF: f = 108 Hz
1
2
3
4
5
6
7
44
43
42
41
8
Seg 20
MIC8030-01
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
28
27
26
25
Chip Select
Data In
LCD
LCD
Opt.
Seg 2
Seg 3
Seg 21
Seg 22
Seg 23
Seg 24
Seg 25
Seg 28
Seg 29
Seg 30
Seg 31
Seg 32
SS
V
CC
V
Data Out 32
Back Plate
Seg 17
Seg 16
Seg 15
Seg 14
Seg 13
Seg 12
Seg 11
Seg 10
Seg 9
Seg 8
Seg 7
Seg 6
Seg 5
Seg 4
BB
V
Seg 19
N/C
Seg 18
39
38
37
36
35
34
33
32
31
30
29
Seg 1
Clock
Load
Seg 27
Seg 26
44-Pin PLCC (-V)
MIC8030
8-18
October 1998
MIC8030
Micrel
Load Clock CS
Data In
Data Out
MIC8030
LCD0
BP
Load Clock CS
Data In
Data Out
MIC8030
LCD0
BP
Load Clock CS
Data In
Data Out
MIC8030
LCD0
BP
Data
Chip Select
Clock
Load
Segments
1-32
Segments
33-64
Segments
65-96
Back Plane
LCD0 Opt
150k
470pF
*330k
*Required if using MIC8031 with V > 50V.
BB
Internal Oscillator Circuit
Typical Application
External Oscillator
Internal Oscillator
200k
LCD0
LCD0 Opt
+
+
+
200k
200k
200k
30
k
V
35V
Z
V
65V
Z
1k
Clock
Reset
Divide by
256
Counter
Q
Q
O
V
CC
Load Clock
CS
Data In
Data Out
MIC8030
LCD0
BP
Load Clock
CS
Data In
Data Out
MIC8030
LCD0
BP
Load Clock
CS
Data In
Data Out
MIC8030
LCD0
BP
Data
Chip Select
Clock
Load
Segments
1-32
Segments
33-64
Segments
65-96
Back Plane
October 1998
8-19
MIC8030
MIC8030
Micrel
8
DC Electrical Characteristics:
V
CC
= 5V, V
SS
= 0V, V
BB
= 50V, 55
C
T
A
+125
C, unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
Power Supply
V
CC
Logic Supply Voltage
4.5
5
5.5
V
V
BB
Display Supply Voltage
20
35
50
V
I
CC
Supply Current (external oscillator)
Note 1
35
250
A
Supply Current (internal oscillator)
Note 1
35
250
A
I
BB
Display Driver Current
f
BP
= 100Hz, no loads
7
100
A
Inputs (CLK, DATA IN, LOAD, CS)
V
IH
Input High Level
V
CC
-1.5 V
CC
-1.8
V
CC
V
V
IL
Input Low Level
0
2.5
2.0
V
I
L
Input Leakage Current
<1
5
A
C
I
Input Capacitance
Note 2
5
10
pF
Input LCD0
V
IH
LCD0 Input High Level
Externally driven
0.9V
CC
V
CC
50
V
V
IL
LCD0 Input Low Level
Externally driven
0.5V
0
0.1V
CC
V
I
LCD0
LCD0 Leakage Current
V
LCD0
= 15V
2
10
A
I
LCD0
LCD0 Leakage Current
V
LCD0
= 35V
6
100
A
I
LCD0
LCD0 Leakage Current
V
LCD0
= 50V
1
mA
Capacitance Loads (typical)
C
LSEG
Segment Output
f
BP
< 100Hz
100
pF
C
LBP
Backplane Output
f
BP
< 100Hz
4000
pF
V
OAVG
DC Bias (Average) Any Segment
f
BP
< 100Hz, Note 2
+25
mV
Output to Backplane
R
SEG
Segment Output Impedance
I
L
= 100
A
1.4
10
k
R
BP
Backplane Output Impedance
I
L
= 100
A
170
312
R
DATA OUT
Data Out Output Impedance
I
L
= 100
A
1.8
3
k
Note 1: CMOS input levels. No loads.
Note 2: Guaranteed by design but not tested on a production basis.
Absolute Maximum Ratings
V
CC
18V
V
BB
(MIC8030)
75V
Inputs (CLK, DATA IN, LOAD, CS)
0.5V to 18V
Inputs (LCD0)
0.5V to 50V
Storage Temperature
65
C to +150
C
Operating Temperature
55
C to +125
C
Maximum Current into and out of
any segment
20 mA
Maximum Power Dissipation,
any segment
50 mW
Maximum Total power dissipation
600 mW
MIC8030
8-20
October 1998
MIC8030
Micrel
AC Electrical Characteristics:
V
CC
= 5V, V
SS
= 0V, V
BB
= 50V, 55
C
T
A
+125
C
Symbol
Parameter
Min
Typ
Max
Units
t
CYC
Cycle Time
500
ns
t
OL
, t
OH
Clock Pulse Width low/high
250
ns
t
r
, t
f
Clock rise/fall
1
s
t
DS
Data In Setup
100
ns
t
CSC
CS Setup to Clock
100
ns
t
DH
Data Hold
10
ns
t
CCS
CS Hold
220
ns
t
CL
Load Pulse Setup
250
ns
t
LCS
CS Hold (rising load to rising CS)
200
ns
t
LW
Load Pulse Width
300
ns
t
LC
Load Pulse Delay (falling load to
0
ns
falling clock)
t
CDO
Data Out Valid from Clock
220
ns
t
CSL
CS Setup to LOAD
0
ns
F
BP
Backplane Frequency
50
100
2000
Hz
Timing Diagram
Clock
tf
3.5V
1.5V
tCYC
tOH
tDH
tDS
tOL
tCSC
tCCS
tLCS
tCSL
tCL
tLW
tLC
tCDO
Data
In
CS
Load
Data
Out
*
*
* The CS high-to-low transition will generate a clock pulse.
tr
Logic Truth Table
Data
Chip
In
Clock Select Load Q
1(SR)
Q
N(SR)
Q
N(DRIVER)
X
X
1
X
NC
NC
Q
N(L)
0
0
0
NC
NC
Q
N(L)
0
0
1
NC
NC
Q
N(L)
0
0
0
0
Q
N
- 1
Q
N
Q
N(L)
0
0
1
0
Q
N
- 1
Q
N
Q
N(SR)
1
0
0
NC
NC
Q
N(L)
1
0
1
NC
NC
Q
N(L)
1
0
0
1
Q
N
- 1
Q
N
Q
N(L)
1
0
1
1
Q
N
- 1
Q
N
Q
N(SR)
= Rising Edge,
= Falling Edge
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