SY87721L

Micrel, Inc.

M9999-072705
hbwhelp@micrel.com or (408) 955-1690

3.3V 28Mbps-2.7Gbps AnyRate

CLOCK AND DATA RECOVERY WITH
INTEGRATED CLOCK MULTIPLIER UNIT

DESCRIPTION

FEATURES

SY87721L

Recovers any data and clock from 28Mbps to
2.7Gbps
· OC-1, OC-3, OC-12, OC-48, ATM
· Gigabit Ethernet, Fast Ethernet
· Fibre Channel, 2x Fibre Channel
· P1394, Infiniband
· SMPTE-259, SMPTE-292
· Proprietary optical transport

Integrated clock multiplier unit with low jitter
generation

Complies with Bellcore, ITU/CCITT and ANSI
specifications

Selectable mux for pass through; avoids jitter
accumulation when switching through backplanes

Available in 64-Pin EPAD-TQFP package

The SY87721L is a complete Clock Recovery and Data

retiming integrated circuit for data rates from 28Mbps up to
2.7Gbps NRZ including SONET FEC data rates. Included
in the device, is a fully integrated Clock Multiplier Unit (CMU)
that is capable of generating frequencies that cover the
same data rate range as the CDR. The device is ideally
suited for SONET/SDH/ATM, Fibre Channel, and Gigabit
Ethernet applications, as well as other high-speed data
transmission applications.

Clock recovery and data retiming is performed by

synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio.
On-chip clock generation is performed through the use of a
frequency multiplier PLL with a byte rate or code group rate
source as reference.

Rev.: B

Amendment: /0

Issue Date: July 2005

SIMPLIFIED BLOCK DIAGRAM

SY87721L

AnyRate
Data In

Reference
Clock

AnyRate

Data Out

Transmit

Clock

CDR

Recovered

Clock

CMU

APPLICATIONS

SONET/SDH/ATM-based transmission systems,
modules, and test equipment

Transponders and section repeaters

Multiplexers: access, add drop (ADM), and terminal (TM)

Terabit routers and broadband cross-connects

Fiber optic test equipment

AnyRate is a registered trademark of Micrel, Inc.

SY87721L

Micrel, Inc.

M9999-072705
hbwhelp@micrel.com or (408) 955-1690

normally by the Receive PLL. When this input is LOW, the
data on the RDOUT output will be internally forced to a
constant LOW, the Link Fault Indicator output LFIN forced
LOW, and the clock recovery PLL forced to lock onto the
synthesized clock frequency generated from REFCLK.

VCOSEL1, VCOSEL2 [VCO Select] TTL Inputs

These inputs select the output clock frequency range via

either one of three PLLs, or a SONET/SDH specific PLL.
Only the selected PLL is enabled. All other PLLs are
disabled. Refer to Table 3 for more details.

FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs

These inputs select the post divide ratio of the VCO.

Refer to Table 3 for more details.

DIVSEL1, ..., DIVSEL3 [Divider Select] TTL Inputs

These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 4. Please note that the divide by 32
selection, "011", is only available for use when FREQSEL
are set to "000."

REFCLK

DIVSEL1

DIVSEL2

DIVSEL3

Multiplier

Table 2

(1)

. Reference Clock Multiplier Truth Table

Note:

1. Some combinations of FREQSEL and DIVSEL result in undefined behavior.

Refer to Table 3 for more details.

PIN NAMES

INPUTS

BRDMX [BRD Mux] PECL Input

This signal indicates what data appears at the BRD

output. When logic HIGH, BRD

is a direct copy of what

appears at RDOUTC

. When logic low, BRD

is a copy of

what appears at RDIN

. Unlike RDOUTC

, BRD

conveys

valid data even when ENPECL is logic LOW. Please refer
to Table 1.

BRDMX (Input)

BRD

(Output)

RDIN

RDOUTC

Table 1. BRDMX Truth Table

RDIN

[Serial Data Input] Differential PECL Input

This differential input accepts the receive serial data

stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN pin has an
internal 75K

resistor tied to V

REFCLK

[Reference Clock] Differential PECL Input

This input is used as the reference for the internal

frequency synthesizer and the "training" frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 340MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK pin has an
internal 75K

resistor tied to V

CD [Carrier Detect] PECL Input

This input controls the recovery function of the Receive

PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered

BRD+

VCOSEL2

FREQSEL1

FREQSEL2

FREQSEL3

GND

VCC

GND

BRDMX

VCC

VCCO

BRD

LFIN

RDIN

RDIN+

VCOSEL1

PLLRN+
PLLRN--

PLLRW+
PLLRW--

VCCA

GNDA

PLLSW--
PLLSW+

PLLSN--
PLLSN+

NC
NC

GND
ENPECL
RDOUTE+
RDOUTE--
RDOUTC+
RDOUTC--
VCCO
RCLKE+
RCLKE--
RCLKC+
RCLKC--
VCCO
TCLKE+
TCLKE--
TCLKC+
TCLKC--

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64-Pin

EPAD-TQFP

DIVSEL3

GND

REFCLK+

REFCLK

VCC

GND

VCC

GND

CLKSEL

ALRSEL

DIVSEL2

DIVSEL1

PACKAGE/ORDERING INFORMATION

Ordering Information

(1)

Package

Operating

Package

Lead

Part Number

Type

Range

Marking

Finish

SY87721LHI

H64-1

Industrial

SY87721LHI

Sn-Pb

SY87721LHITR

(2)

H32-1

Industrial

SY87721LHI

Sn-Pb

SY87721LHG

(3)

H32-1

Industrial

SY87721LHG with

Pb-Free

Pb-Free bar-line indicator

NiPdAu

SY87721LHG

(2, 3)

H32-1

Industrial

SY87721LHG with

Pb-Free

Pb-Free bar-line indicator

NiPdAu

Notes:

1. Contact factory for die availability. Dice are guaranteed at T

= 25

C, DC electricals only.

2. Tape and Reel.

3. Recommended for new designs.

SY87721L

Micrel, Inc.

M9999-072705
hbwhelp@micrel.com or (408) 955-1690

CLKSEL [Clock Select] TTL Input

This input is used to select either the recovered clock of

the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs. Do not use for skew matching.

ENPECL [Enable ECL] TTL Input

This input, when HIGH (ENPECL = 1), enables the

differential PECL outputs TCLKE

, RDOUTE

, and RCLKE

It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC,
RDOUTC, and RCLKC logic LOW.

When set LOW (ENPECL = 0), this signal enables the

differential CML outputs TCLKC

, RDOUTC

, and RCLKC

It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE,
RDOUTE and RCLKE logic LOW.

ALRSEL [Auto Lock Range Select] TTL Input

This pin defines the frequency difference, and the

frequency difference hysteresis at which `in-lock' and `out of
lock' conditions are declared. Please refer to the "AC
Characteristics" for more details.

OUTPUTS

BRD

[Buffered Recovered Data] Differential CML Output

The signal is either a buffered RDIN

or RDOUTC

depending on the state of the BRDMX input. This allows a
user to selectively bypass the CDR or not, as warranted by
architecture. This CML output has a voltage swing of 400mV
loaded.

LFIN [Link Fault Indicate] O.C. TTL Output

This output indicates the status of the input data stream

RDIN. Active HIGH indicates that the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range
of the Receive PLL (as per ALRSEL). LFIN is an
asynchronous output.

RDOUTE

[Receive Data Out] Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

the recovered data from the input data stream (RDIN). It is
specified on the rising edge of RCLK.

RDOUTC

[Receive Data Out] Differential CML Output

This is the CML version of RDOUTE

RCLKE

[Receive Clock Out] Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

the recovered clock used to sample the recovered data
(RDOUT).

RCLKC

[Receive Clock Out] Differential CML Output

This is the CML version of RCLKE

TCLKE

[Transmit Clock Out] Differential PECL Output

These ECL 100K outputs (+3.3V referenced) represent

either the recovered clock (CLKSEL = HIGH) used to sample
the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).

TCLKC

[Transmit Clock Out] Differential CML Output

This is the CML version of TCLKE

PLLSN+, PLLSN [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis narrow

band PLL.

PLLSW+, PLLSW [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis wide band

PLL.

PLLRN+, PLLRN [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery narrow

band PLL.

PLLRW+, PLLRW [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery wide band

PLL.

OTHERS

VCC

Supply Voltage

VCCO

Output Supply Voltage

VCCA

Analog Supply Voltage

GND

Ground

GNDA

Analog Ground

These pins are for factory test, and are to be
left unconnected during normal use.

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