1
Precision Edge
SY89542U
Micrel, Inc.
M9999-071505
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
Dual 2:1 multiplexer
Guaranteed AC performance over temp and voltage:
DC-to > 3.2Gbps data rate throughput
< 600ps In-to-Out t
pd
< 150ps t
r
/t
f
Ultra-low jitter design:
< 1ps
RMS
random jitter
< 10ps
PP
deterministic jitter
< 10ps
PP
total jitter (clock)
< 0.7ps
RMS
crosstalk-induced jitter
Unique input isolation design minimizes crosstalk
Internal input termination
Unique input termination and V
T
pin accepts
DC-Coupled and AC-coupled inputs (LVDS, LVPECL,
CML)
350mV LVDS output swing
CMOS/TTL compatible MUX select
Power supply 2.5V
5%
40
C to +85
C temperature range
Available in 32-pin (5mm
5mm) MLFTM package
FEATURES
2.5V, 3.2Gbps DUAL, DIFFERENTIAL
2:1 LVDS MULTIPLEXER WITH
INTERNAL TERMINATION
Precision Edge
SY89542U
APPLICATIONS
Redundant clock/data switchover
SONET/SDH multi-channel select applications
Fibre Channel applications
GigE applications
Rev.: B
Amendment: /0
Issue Date:
July 2005
The SY89542U includes two precision, high-speed 2:1
differential Muxes with LVDS (350mV) compatible outputs
with a guaranteed data rate throughput of 3.2Gbps over
temperature and voltage.
The SY89542U differential inputs include a unique, 3-pin
internal termination that allows access to the termination
network through a V
T
pin. This feature allows the device to
easily interface to different logic standards, both AC- and
DC-coupled without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution.
The SY89542U operates from a single 2.5V supply, and
is guaranteed over the full industrial temperature range
(40
C to +85
C). For applications that require a 3.3V supply,
consider the SY89543L. The SY89542U is part of Micrel's
Precision Edge
product family.
All support documentation can be found on Micrel's web
site at www.micrel.com.
Precision Edge
LVDS
QA
/QA
INA0
/INA0
V
TA0
50
50
0
MUX A
2:1 MUX
1
INA1
/INA1
V
TA1
50
50
S
SELA (CMOS/TTL)
LVDS
QB
/QB
INB0
/INB0
V
TB0
50
50
0
MUX B
2:1 MUX
1
INB1
/INB1
V
TB1
50
50
S
SELB (CMOS/TTL)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
2
Precision Edge
SY89542U
MicreL, Inc.
M9999-071505
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Pin Number
Pin Name
Pin Function
4, 2, 32, 30,
INA0, /INA0,
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
27, 25, 23, 21
INA1, /INA1,
accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally
INB0, /INB0,
terminates to a V
T
pin through 50
. Note that these inputs will default to an indeterminate
INB1, /INB1
state if left open. Unused differential input pairs can be terminated by connecting one input
to V
CC
and the complementary input to GND through a 1k
resistor. The V
T
pin is to be
left open in this configuration. Please refer to the "Input Interface Applications" section for
more details.
3, 31, 26, 22
VTA0 , VTA1,
Input Termination Center-Tap: Each side of the differential input pair, terminates to a V
T
VTB0, VTB1
pin. The V
TA0
, V
TA1
, V
TB0
, V
TB1
pins provide a center-tap to a termination network for
maximum interface flexibility. See "Input Interface Applications" section for more details.
6, 19
SELA, SELB
These single-ended TTL/CMOS compatible inputs select the inputs to the multiplexers.
Note that these inputs are internally connected to a 25k
pull-up resistor and will default to
logic HIGH state if left open. Input switching threshold is V
CC
/2.
1, 5, 8, 17, 20,
VCC
Positive Power Supply: Bypass with 0.1
F||0.01
F low ESR capacitors. The 0.01
F
24, 28, 29
capacitor should be as close to V
CC
pin as possible.
10, 11, 14, 15
QA, /QA,
Differential Outputs: This differential LVDS output pair provides a copy of the selected
QB, /QB
input. It is a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs.
Please refer to the "Truth Table" for details. Unused output pairs must be terminated with
100
across the differential pair.
7, 9, 12, 13, 16, 18
GND,
Ground: Ground pin and exposed pad must be connected to the same ground plane.
Exposed pad
PIN DESCRIPTION
24
23
22
21
20
19
18
17
VCC
INB1
VTB 1
/INB1
VCC
SELB
GND
VCC
VCC
/INA0
VTA0
INA0
VCC
SELA
GND
VCC
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
VCC
VCC
INA1
VTA1
INA1
INB0
VTB0
/INB0
GND
GND
/QA
QA
GND
QB
/QB
GND
32-Pin MLFTM
Ordering Information
(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89542UMI
MLF-32
Industrial
SY89542U
Sn-Pb
SY89542UMITR
(2)
MLF-32
Industrial
SY89542U
Sn-Pb
SY89542UMG
(3)
MLF-32
Industrial
SY89542U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY89542UMGTR
(2,3)
MLF-32
Industrial
SY89542U with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25
C, DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.
3
Precision Edge
SY89542U
Micrel, Inc.
M9999-071505
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ................................. 0.5V to +4.0V
Input Voltage (V
IN
) ........................................ 0.5V to V
CC
Termination Current
(3)
Source or sink current on V
T .....................................
100mA
Input Current
Source or sink current on IN, /IN ..........................
50mA
Lead Temperature (soldering, 20 sec.) ................... +260
C
Storage Temperature (T
S
) ....................... 65
C to +150
C
Operating Ratings
(2)
Supply Voltage (V
CC
) ............................. 2.375V to 2.625V
Ambient Temperature (T
A
) ........................ 40
C to +85
C
Package Thermal Resistance
(4)
MLFTM (
JA
)
Still-Air ................................................................ 35
C/W
500lfpm .............................................................. 28
C/W
MLFTM (
JB
)
Junction-to-Board ................................................ 20
C/W
T
A
= 40
C to +85
C; Unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
CC
Power Supply
2.375
2.5
2.625
V
I
CC
Power Supply Current
No Load, Max. V
CC
(6)
70
95
mA
R
DIFF_IN
Differential Input Resistance
80
100
120
(IN-to-/IN)
R
IN
Input Resistance
40
50
60
(IN-to-VT, /IN-to-VT)
V
IH
Input High Voltage (IN, /IN)
Note 7
V
CC
1.6
V
CC
V
V
IL
Input Low Voltage (IN, /IN)
Note 7
0
V
IH
0.1
V
V
IN
Input Voltage Swing (IN, /IN)
Notes 7, 8
100
V
CC
mV
V
DIFF_IN
Differential Input Voltage Swing
Notes 7, 8
200
2
V
CC
mV
|IN - /IN|
IN-to-V
T
Voltage from Input to V
T
1.8
V
Notes:
1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to "Absolute Maximum Ratings" conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
JB
uses 4-layer
JA
in still-air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. Includes current through internal 50
pull-ups.
7. V
IH
(min) not lower than 1.2V.
8. See "Single-Ended and Differential Swings" section for V
IN
and V
DIFF_IN
definition.
DC ELECTRICAL CHARACTERISTICS
(5)
4
Precision Edge
SY89542U
MicreL, Inc.
M9999-071505
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 2.5V
5%; T
A
= 40
C to +85
C; R
L
= 100
across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
OH
Output HIGH Voltage (Q, /Q)
See Figure 5a
1.475
V
V
OL
Output LOW Voltage (Q, /Q)
See Figure 5a
0.925
V
V
OUT
Output Voltage Swing (Q, /Q)
See Figures 1a, 5a
250
350
mV
V
DIFF-OUT
Differential Output Voltage Swing
See Figure 1b
500
700
mV
|Q - /Q|
V
OCM
Output Common Mode Voltage
See Figure 5b
1.125
1.275
V
(Q, /Q)
V
OCM
Change in Common Mode Voltage
See Figure 5b
50
+50
mV
(Q, /Q)
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS
(9)
V
CC
= 2.5V
5%; T
A
= 40
C to +85
C; unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input HIGH Voltage
2.0
V
CC
V
V
IL
Input LOW Voltage
0.8
V
I
IH
Input HIGH Current
40
A
I
IL
Input LOW Current
300
A
Note:
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(9)
5
Precision Edge
SY89542U
Micrel, Inc.
M9999-071505
hbwhelp@micrel.com or (408) 955-1690
V
CC
= 2.5V
5%; T
A
= 40
C to +85
C; R
L
= 100
across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Operating Frequency
NRZ Data
3.2
Gbps
V
OUT
> 200mV
Clock
4
GHz
t
pd
Differential Propagation Delay
IN-to-Q
250
350
450
ps
SEL-to-Q
200
350
600
ps
t
SKEW
Input-to-Input Skew
Note 11
20
ps
Bank-to-Bank Skew
Note 12
25
ps
Part-to-Part Skew
Note 13
200
ps
t
JITTER
Data
Random Jitter (RJ)
Note 14
1
ps
RMS
Deterministic Jitter (DJ)
Note 15
10
ps
PP
Clock
Total Jitter (TJ )
Note 16
10
ps
PP
Cycle-to-Cycle Jitter
Note 17
1
ps
RMS
Crosstalk-Induced Jitter
Note 18
0.7
ps
RMS
t
r
, t
f
Output Rise / Fall Time
At full output swing
35
80
150
ps
(20% to 80%)
Notes:
10. Measured with 100mV input swing. See "Timing Diagrams " section for definition of parameters. High frequency AC-parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in time from an input-to-output in comparison to any other input-to-output. In addition, the input-to-input skew
does not include the output skew.
12. Bank-to-bank skew is the difference in time from input to the output between banks.
13. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. Total skew is calculated as the RMS (Root Mean Square) of the input skew and output skew.
14. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
15. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 2
23
1 PRBS pattern.
16. Total jitter definition: with an ideal clock input of frequency
f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
17. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
-T
n-1
where T is the time between rising edges of the output signal.
18. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the
inputs.
AC ELECTRICAL CHARACTERISTICS
(10)
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