May 1997
ML2252
*
, ML2259
**
P Compatible 8-Bit A/D Converters
with 2- or 8-Channel Multiplexer
GENERAL DESCRIPTION
The ML2252 and ML2259 combine an 8-bit A/D
converter, 2- or 8-channel analog multiplexer, and a
microprocessor compatible 8-bit parallel interface and
control logic in a single monolithic CMOS device.
Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and a
double buffered three-state data bus. These analog-to-
digital converters allow the microprocessor to operate
completely asynchronous to the converter clock.
The built in sample and hold function provides the ability
to digitize a 5V, 50kHz sinewave to 8-bit accuracy. The
differential comparator design provides low power supply
sensitivity to DC and AC variations. The voltage reference
can be externally set to any value between ground and
V
CC
, thus allowing a full conversion over a relatively
small span. All parameters are guaranteed over
temperature with a power supply voltage of 5V 10%.
The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.
FEATURES
s
Conversion time (f
CLK
= 1.46MHz); 6.6s
s
Total unadjusted error; 1/2LSB or 1LSB
s
No missing codes
s
Sample and hold; 390ns acquisition
s
Capable of digitizing a 5V, 50kHz sinewave
s
2- or 8-channel input multiplexer
s
0V to 5V analog input range with single 5V
power supply
s
Operates ratiometrically or with up to 5V
voltage reference
s
No zero or full scale adjust required
s
Analog input protection; 25mA per input min
s
Continuous conversion mode
s
Low power dissipation; 15mW max
s
TTL and CMOS compatible digital inputs and outputs
ML2252 BLOCK DIAGRAM
CONTROL
& TIMING
2-CHANNEL
MULTIPLEXER
ADDRESS
LATCH
AND
DECODER
THREE
STATE
OUTPUT
BUFFER
SUCCESSIVE
APPROXIMATION
REGISTER
D/A
CONVERTER
V
CC
A/D WITH
SAMPLE-AND-HOLD FUNCTION
8pF
8pF
CLOCK
+
+
DB7
COMP
CH0
CH1
ALE
A0
GND
+V
REF
V
REF
DB6
DB5
DB4
DB3
DB2
DB1
DB0
EOC
START
OE
1
* This Part Is Obsolete
** This Part Is End of Life As Of August 1, 2000
ML2252, ML2259
2
ML2259 BLOCK DIAGRAM
ADDR0
ADDR1
ADDR2
ALE
DB7
DB6
DB5
CH7
START
EOC
DB3
OE
CLK
V
CC
12
13 14
15
16
CH6
CH5
CH4
CH3
CH2
CH1
CH0
+V
REF
GND
DB1
DB2
V
REF
DB0
DB4
17
18
5
6
7
8
9
10
11
4
3
2
1
28
25
24
23
22
21
20
19
27
26
TOP VIEW
ML2259
28-Pin PLCC (Q28)
ML2259
28-Pin DIP(P28W)
CH3
CH4
CH5
CH6
CH7
START
EOC
DB3
OE
CLK
V
CC
+V
REF
GND
DB1
CH2
CH1
CH0
ADDR0
ADDR1
ADDR2
ALE
DB7
DB6
DB5
DB4
DB0
V
REF
DB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
ML2252
20-Pin PLCC (Q20)
PIN CONFIGURATION
ML2252
20-Pin DIP (P20)
CH1
START
EOC
DB3
OE
CLK
V
CC
+V
REF
GND
DB1
CH0
ADDR0
ALE
DB7
DB6
DB5
DB4
DB0
V
REF
DB2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
CONTROL
& TIMING
8-CHANNEL
MULTIPLEXER
ADDRESS
LATCH
AND
DECODER
THREE
STATE
OUTPUT
BUFFER
SUCCESSIVE
APPROXIMATION
REGISTER
D/A
CONVERTER
A/D WITH
SAMPLE-AND-HOLD FUNCTION
8pF
8pF
+
+
COMP
CH0
CH1
V
CC
CLK
CH2
CH3
CH4
CH5
CH6
CH7
GND
+V
REF
V
REF
DB3
DB2
DB1
DB6
DB7
DB5
DB4
DB0
EOC
START
OE
ALE
A0
A1
A2
ALE
DB7
DB6
DB5
DB4
DB3
OE
CLK
V
CC
+V
REF
9
10 11
12
13
EOL
START
CH1
CH0
ADDR0
GND
DB1
DB2
V
REF
DB0
4
5
6
7
8
3
2
1
20
19
18
17
16
15
14
TOP VIEW
ML2252, ML2259
3
Pin Number
ML2252
ML2259
Name
Function
1
CH3
Analog input 3.
2
CH4
Analog input 4.
3
CH5
Analog input 5.
4
CH6
Analog input 6.
5
CH7
Analog input 7.
2
6
START
Start of conversion. Active high digital input pulse initiates conversion.
3
7
EOC
End of conversion. This output goes low after a START pulse occurs, stays
low for the entire A/D conversion, and goes high after conversion is
completed. Data on DB0DB7 is valid on rising edge of EOC and stays valid
until next EOC rising edge.
4
8
DB3
Data output 3.
5
9
OE
Output enable input. When OE = 0, DB0DB7 are in high impedance state;
OE = 1, DB0DB7 are active outputs.
6
10
CLK
Clock. Clock input provides timing for A/D converter, S/H, and digital
interface.
7
11
V
CC
Positive supply. 5V 10%.
8
12
+V
REF
Positive reference voltage.
9
13
GND
Ground. 0V, all analog and digital inputs or outputs are referenced to this
point.
10
14
DB1
Data output 1.
11
15
DB2
Data output 2.
12
16
V
REF
Negative reference voltage.
13
17
DB0
Data output 0.
14
18
DB4
Data output 4.
15
19
DB5
Data output 5.
16
20
DB6
Data output 6.
17
21
DB7
Data output 7.
18
22
ALE
Address latch enable. Input to latch in the digital address (ADDR2-0) on the
rising edge of the multiplexer.
23
ADDR2
Address input 2 to multiplexer. Digital input for selecting analog input.
24
ADDR1
Address input 1 to multiplexer. Digital input for selecting analog input.
19
25
ADDR0
Address input 0 to multiplexer. Digital input for selecting analog input.
20
26
CH0
Analog input 0.
1
27
CH1
Analog input 1.
28
CH2
Analog input 2.
PIN DESCRIPTION
ML2252, ML2259
4
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= +V
REF
= 5V 10%, V
REF
= GND, f
CLK
= 1.46MHz,
T
A
= Operating temperature range (Note 1)
ML2252B, ML2259B
ML2252C, ML2259C
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Converter and Multiplexer Characteristics
Total Unadjusted Error
V
REF
= V
CC,
(Note 2)
1/2
1
LSB
+V
REF
Voltage Range
V
REF
V
CC
+ 0.1
V
REF
V
CC
+ 0.1
V
V
REF
Voltage Range
GND 0.1
+V
REF
GND 0.1
+V
REF
V
Reference Input Resistance
14
20
35
14
20
28
k
Analog Input Range
(Note 3)
GND 0.1
V
CC
+ 0.1 GND 0.1
V
CC
+ 0.1
V
Power Supply Sensitivity
DC, V
CC
= 5V 10%
1/32
1/4
1/32
1/4
LSB
100mVp-p, 100kHz
1/16
1/16
LSB
Sine on V
CC
, V
IN
= 0
I
OFF
, Off Channel Leakage
On Channel = V
CC,
(Note 4)
1
1
A
Current (Note 9)
Off Channel = 0V
On Channel = 0V, (Note 4)
1
1
A
Off Channel = V
CC
I
ON
, On Channel Leakage
On Channel = 0V, (Note 4)
1
1
A
Current (Note 9)
Off Channel = V
CC
On Channel = V
CC,
(Note 4)
1
1
A
Off Channel = 0V
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Voltage, V
CC ..............................................................
6.5V
Logic Inputs ....................................... 0.3V to V
CC
0.3V
Analog Inputs ..................................... 0.3V to V
CC
0.3V
Input Current per Pin ............................................ 25mA
Storage Temperature ................................ 65C to 150C
Lead Temperature (Soldering 10 sec.) .................... 260C
OPERATING CONDITIONS
Supply Voltage, V
CC ..............................................
4.5V to 6.3V
Temperature Range ........................................ 0C to 70C
Thermal Resistance (
q
JA
)
20-Pin PDIP ..................................................... 67C/W
20-Pin PLCC .................................................... 78C/W
28 Pin PDIP ..................................................... 48C/W
28-Pin PLCC .................................................... 68C/W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital and DC
V
IN(1)
Logical "1" Input Voltage
2.0
V
V
IN(0)
Logical "0" Input Voltage
0.8
V
I
IN(1)
Logical "1" Input Current
V
IN
= V
CC
1
A
I
IN(0)
Logical "0" Input Current
V
IN
= 0V
1
A
V
OUT(1)
Logical "1" Output Voltage
I
OUT
= 2mA
4.0
V
V
OUT(0)
Logical "0" Output Voltage
I
OUT
= 2mA
0.4
V
I
OUT
Three-State Output Current
V
OUT
= 0V
1
A
V
OUT
= V
CC
1
A
I
CC
Supply Current
1.5
3
mA
ML2252, ML2259
5
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC and Dynamic Performance Characteristics (Note 5)
t
ACQ
Sample and Hold Acquisition
1/2
1/f
CLK
f
CLK
Clock Frequency
10
1460
kHz
t
C
Conversion Time
8.5
8.5 + 250ns
1/f
CLK
SNR
Signal to Noise Ratio
V
IN
= 51kHz, 5V sine.
47
dB
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of f
SAMPLING
THD
Total Harmonic Distortion
V
IN
= 51kHz, 5V sine.
60
dB
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz).
THD is sum 2, 3, 4, 5 harmonics
relative to fundamental
IMD
Intermodulation Distortion
V
IN
= f
A
+ f
B
. f
A
= 49kHz, 2.5V sine.
60
dB
f
B
= 47.8kHz, 2.5V sine,
f
CLK
= 1.46MHz
(f
SAMPLING
> 150kHz). IMD is (f
A
+ f
B
),
(f
A
f
B
), (2f
A
+ f
B
), (2f
A
f
B
), (f
A
+ 2f
B
),
(f
A
2f
B
) relative to fundamental
FR
Frequency Response
V
IN
= 0 to 50kHz. 5V sine relative
0.1
dB
to 1kHz
t
DC
Clock Duty Cycle
(Note 6)
40
60
%
t
EOC
End of Conversion Delay
1/2
1/2 + 250ns
1/f
CLK
t
WS
Start Pulse Width
50
ns
t
SS
Start Pulse Setup Time
Synchronous only, (Note 7)
40
ns
t
WALE
Address Latch Enable
50
ns
Pulse Width
t
S
Address Setup
0
ns
t
H
Address Hold
50
ns
t
H1, H0
Output Enable for DB0DB7
Figure 1, C
L
= 50pF
100
ns
Figure 1, C
L
= 10pF
50
ns
t
1H, 0H
Output Disable for DB0DB7
Figure 1, C
L
= 50pF
100
ns
Figure 1, C
L
= 10pF
50
ns
C
IN
Capacitance of Logic Input
5
pF
C
OUT
Capacitance of Logic Outputs
10
pF
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
Note 3: For V
REF
V
IN
(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5V) can
cause this input diode to conduct -- especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog V
IN
or V
REF
does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an
absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage of 4.900V
DC
over temperature variations, initial tolerance and loading.
Note 4: Leakage current is measured with the clock not switching.
Note 5: C
L
= 50pF, timing measured at 50% point.
Note 6: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,
the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60s.
Note 7: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,
start conversion will have an uncertainty of one clock pulse.
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