CAT
17
FB A
22
FB B
23
FB C
24
BACK
EMF
SAMPLER
CRT
19
+
+
1.5V
750nA
+
1.5V
750nA
VDD
VDD
CRR
21
500nA
VDD
SPEED
FB
20
CVCO
15
16
RVCO
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
13
2
4
3
9
10
HA
HB
HC
LA
LB
GATING
LOGIC
&
OUTPUT
DRIVERS
+
SPEED SET
8
5
SPEED COMP
3.9V
1.7V
20kHz
6
CT
+
1.4V
1
ISENSE
5
UVLO
12
ILIMIT
+
1.7V
VREF
26
CIOS
16k
8k
ILIMIT
1-SHOT
25
BRAKE
VDD
4k
14
VDD
28
GND
27
RREF
11
LC
REFERENCE
VCO
OUT
VCO
OUT
18
UV FAULT
7
VREF
A
B
C
D
E
F
R
COMMUTATION
STATE MACHINE
July 2000
ML4425
Sensorless BLDC Motor Controller
GENERAL DESCRIPTION
The ML4425 PWM motor controller provides all of the
functions necessary for starting and controlling the speed
of delta or wye wound Brushless DC (BLDC) motors
without Hall Effect sensors. Back EMF voltage is sensed
from the motor windings to determine the proper
commutation phase sequence using a PLL. This patented
sensing technique will commutate a wide range of 3-
Phase BLDC motors and is insensitive to PWM noise and
motor snubbing circuitry.
The ML4425 limits the motor current using a constant off-
time PWM control loop. The velocity loop is controlled
with an onboard amplifier. The ML4425 has circuitry to
ensure that there is no shoot-through in directly driven
external power MOSFETs.
The timing of the start-up sequence is determined by the
selection of three timing capacitors. This allows
optimization for a wide range of motors and loads.
FEATURES
s
Stand-alone operation
s
Motor starts and stops with power to IC
s
On-board start sequence: Align
Ramp Set Speed
s
Patented Back-EMF commutation technique provides
jitterless torque for minimum "spin-up" time
s
Onboard speed control loop
s
PLL used for commutation provides noise immunity
from PWM spikes, compared to noise sensitive zero
crossing technique
s
PWM control for maximum efficiency
s
Direct FET drive for 12V motors; drives high voltage
motors with IC buffers from IR, IXYS, Harris, Power
Integrations, Siliconix, etc.
BLOCK DIAGRAM
(Pin Configuration Shown for 28 Pin Version)
1
2
ML4425
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ISENSE
HA
HB
HC
SPEED COMP
CT
VREF
SPEED SET
LA
LB
LC
ILIMIT
VCO/TACH
VDD
GND
RREF
CIOS
BRAKE
FB C
FB B
FB A
CRR
SPEED FB
CRT
UV FAULT
CAT
RVCO
CVCO
TOP VIEW
ML4425
28-Pin Narrow PDIP (P28N)
28-Pin SOIC (S28)
FB C
FB B
FB A
CRR
SPEED FB
CRT
UV FAULT
CAT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
H3
NC
SPEED COMP
CT
VREF
SPEED SET
LA
LB
LC
I LIMIT
VCO/TACH
V
DD
NC
NC
C
VCO
R
VCO
HB
HA
I SENSE
NC
GND
R
REF
C
IOS
BRAKE
TOP VIEW
ML4425
32-Pin TQFP (H32-7)
3
ML4425
PIN
NAME
FUNCTION
1(30)
I
SENSE
Motor current sense input. When
I
SENSE
exceeds 0.2
I
LIMIT,
the
output drivers LA, LB, and LC are
shut off for a fixed time
determined by C
IOS
2(31)
HA
Active low output driver for the
phase A high-side switch
3(32)
HB
Active low output driver for the
phase B high-side switch
4(1)
HC
Active low output driver for the
phase C high-side switch
5(3)
SPEED COMP Speed control loop compensation is
set by a series resistor and capacitor
from SPEED COMP to GND
6(4)
C
T
A capacitor from C
T
to GND sets
the PWM oscillator frequency
7(5)
V
REF
6.9V reference voltage output
8(6)
SPEED SET
Speed loop input which ranges
from 0 (stopped) to V
REF
(maximum speed)
9(7)
LA
Active high output driver for the
phase A low-side switch
10(8)
LB
Active high output driver for the
phase B low-side switch
11(9)
LC
Active high output driver for the
phase C low-side switch
12(10) I
LIMIT
Voltage on this pin sets the I
SENSE
threshold voltage at 0.2
I
LIMIT
,
leaving this pin unconnected
selects an internally set threshold
13(11) VCO/TACH
This TTL level output corresponds
to the signal used to clock the
commutation state machine. The
output frequency is proportional to
the motor speed when the back-
EMF sensing loop is locked onto
the rotor position
14(12) V
DD
12V power supply input
15(15) C
VCO
A capacitor to GND sets the
voltage-to-frequency ratio of the
VCO
16(16) R
VCO
An resistor to GND sets up a
current proportional to the input
voltage of the VCO
PIN
NAME
FUNCTION
17(17) C
AT
A capacitor to GND sets the time
that the controller stays in the
align mode
18(18) UV FAULT
This output goes low when V
DD
drops below the UVLO threshold,
and indicates that all output
drivers have been disabled
19(19) C
RT
A capacitor to GND sets the time
that the controller stays in the
ramp mode
20(20) SPEED FB
Output of the back-EMF sampling
circuit and input to the VCO. An
RC network connected to SPEED
FB sets the compensation for the
PLL loop formed by the back-EMF
sampling circuit, the VCO, and
the commutation state machine
21(21) C
RR
A capacitor to between C
RR
and
SPEED FB sets the ramp rate
(acceleration) of the motor when
the controller is in ramp mode
22(22) FB A
The motor feedback voltage from
phase A is monitored through a
resistor divider for back-EMF
sensing at this pin
23(23) FB B
The motor feedback voltage from
phase B is monitored through a
resistor divider for back-EMF
sensing at this pin
24(24) FB C
The motor feedback voltage from
phase C is monitored through a
resistor divider for back-EMF
sensing at this pin
25(25) BRAKE
A logic low input activates motor
braking by shutting off the high-
side output drivers and turning on
the low-side output drivers
26(26) C
IOS
A capacitor to GND sets the time
that the low-side output drivers
remain off after I
SENSE
exceeds its
threshold
27(27) R
REF
An 137k
W resistor to GND sets a
current proportional to V
REF
that is
used to set all the internal bias
currents except for the VCO
28(28) GND
Signal and power ground
PIN DESCRIPTION
(Pin number in parenthesis is for TQFP package)
4
ML4425
ELECTRICAL CHARACTERISTICS
Unless otherwise specified,V
DD
= 12V 10%, R
SENSE
= 1
W, C
VCO
= 10nF, C
IOS
= 100pF, R
REF
= 137k
W,
T
A
= Operating Temperature Range (Notes 1, 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE
V
REF
Total Variation
Line, Temp
6.5
6.9
7.5
V
PWM OSCILLATOR
Total Variation
C
T
= 1nF
28
kHz
Ramp Peak
3.9
V
Ramp Valley
1.7
V
Ramp Charging Current
?
A
SPEED CONTROL LOOP
SPEED SET Input Voltage Range
0
V
REF
V
SPEED FB Input Voltage Range
0
V
REF
V
SPEED COMP Output Current
5
20
A
SPEED SET Error Amp Transconductance
V
SPEED SET
= xV, V
SPEED FB
= yV
144
W
START-UP
C
AT
Charging Current
C Suffix
0.68
0.98
A
I Suffix
0.5
1.1
A
C
AT
Threshold Voltage
1.4
1.7
V
C
RT
Charging Current
C Suffix
0.68
0.98
A
I Suffix
0.5
1.1
A
C
RT
Threshold Voltage
1.4
1.7
V
VOLTAGE CONTROLLED OSCILLATOR
Frequency Range
R
VCO
= 5V, SPEED FB = 6V
1.5
1.85
2.2
kHz
Frequency vs. SPEED FB
R
VCO
= 5V, 0.5V
SPEED FB 7V
300
Hz/V
CURRENT LIMIT
I
SENSE
Gain
V(I
LIMIT
)
2.5V
4.5
5.0
5.5
V/V
One Shot OFF-Time
C
IOS
= 100pF
C Suffix
9
18
s
I Suffix
9
20
s
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
DD
.......................................................................... 14V
Logic Inputs (, SPEED FB, BRAKE) .......... GND - 0.3 to 7V
All Other Inputs and Outputs .. GND -0.3V to V
DD
+ 0.3V
Output Current (LA, LB, LC, HA, HB, HC) ............ 50mA
Junction Temperature .............................................. 150C
Storage Temperature Range ...................... 65C to 150C
Lead Temperature (Soldering 10 sec.) ..................... 260C
Thermal Resistance (
q
JA
)
28-Pin Narrow PDIP ......................................... 48C/W
28-Pin SOIC ..................................................... 75C/W
32-Pin TQFP ..................................................... 80C/W
OPERATING CONDITIONS
Temperature Range
ML4425CX................................................. 0C to 70C
ML4425IX ............................................... 40C to 85C
V
DD
......................................................... 10.8V to 13.2V
5
ML4425
ELECTRICAL CHARACTERISTICS
(Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (BRAKE) (Note 3)
V
IH
Input High Voltage
2
V
V
IL
Input Low Voltage
0.8
V
I
IH
Input High Current
V
IH
= 2.4V
2.4
mA
I
IL
Input Low Current
V
IL
= 0.4V
2.9
mA
LOGIC OUTPUTS (VCO/TACH, UV FAULT) (Note 3)
VCO/TACH Output High Voltage
I
OUT
= 100A
2.2
V
VCO/TACH Output Low Voltage
I
OUT
= 400A
0.6
V
UV FAULT Output High Voltage
I
OUT
= 10A
C Suffix
3.4
4.5
5.4
V
I Suffix
3.2
5.6
V
UV FAULT Output Low Voltage
I
OUT
= 400A
0.6
V
BACK-EMF SAMPLER
SPEED FB Align Mode Voltage
125
250
mV
SPEED FB Ramp Mode Current
C Suffix
500
720
nA
I Suffix
500
750
nA
SPEED FB Run Mode Current
State A, C
RT
= 5V,
C Suffix
30
90
A
V
PHB
= V
DD
/3
I Suffix
27
90
A
State A, C
RT
= 5V, V
PHB
= V
DD
/2
15
15
A
State A, C
RT
= 5V,
C Suffix
90
30
A
V
PHB
= 2
V
DD
/3
I Suffix
90
27
A
OUTPUT DRIVERS
High Side Driver Output Low Current
V
HX
= 2V
0.5
1.2
mA
High Side Driver Output High Voltage
I
HX
= 10A
V
CC
1.3
V
Low Side Driver Output Low Voltage
I
LX
= 1mA
0.2
0.7
V
Low Side Driver Output High Voltage
V(I
SENSE
) = 0V
C Suffix V
DD
2.2
V
I Suffix V
DD
2.9
V
Phase C Cross-conduction Lockout Threshold
V
DD
3.0
V
SUPPLY
I
DD
V
DD
Current
32
50
mA
UVLO Threshold
C Suffix
8.8
9.5
10.2
V
I Suffix
8.6
10.3
V
UVLO Hysteresis
150
mV
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2: For explanation of states, see Figure 4 and Table 1.
Note 3: The BRAKE and UV FAULT pins each have an internal 4k
W resistor to the internal reference.
6
ML4425
FUNCTIONAL DESCRIPTION
GENERAL
The ML4425 provides all the circuitry for sensorless speed
control of 3-phase Brushless DC (BLDC) motors. Controller
functions include start-up circuitry, back-EMF
commutation control, Pulse Width Modulation (PWM)
speed control, fixed OFF-time current limiting, braking,
and undervoltage protection.
The start-up circuitry aligns the motor to a known position,
then ramps up the motor speed to generate a back-EMF
signal. A back-EMF sampling circuit controls
commutation timing by forming a Phase Locked Loop
(PLL). The commutation control circuitry also outputs a
speed feedback (SPEED FB) signal used in the speed
control loop. The speed control loop consists of an error
amplifier and PWM comparator that produce a PWM duty
cycle for speed regulation. Motor current is limited by a
fixed OFF-time PWM shutdown comparator that is
controlled by an external sense resistor. Commutation
control, PWM speed control, and current limiting are
combined to produce the output driver signals. Six output
drivers are used to provide gating signals to an external 3
phase bridge power stage sized for the BLDC motor
voltage and current requirements. Additional functions
include a braking function and undervoltage protection
circuit to shut down the output drivers in the event of a
low voltage condition on V
DD
of the ML4425.
COMPONENT SELECTION
Selecting external components for the ML4425 requires
calculations based on the motor's electrical and
mechanical parameters. The following is a list of the
motor parameters needed for these calculations :
DC motor supply voltage V
MOTOR
(V)
Maximum operating current I
MAX
(A)
Number of magnetic poles N
Back EMF constant K
e
(V-s/Rad)
Motor torque constant K
t
(Nm/A) (K
t
= K
e
in SI units)
Maximum speed of operation RPM
MAX
(RPM)
Moment of inertia of the motor and load J (Kg-m
2
)
Viscous damping factor of the motor and load
z
If one or more of the above values is not known, it is still
possible to pick components for the ML4425, but some
experimentation may be necessary to determine the
optimal values. All quantities are in SI units unless
otherwise specified. The following formulas should be
considered as a starting point for optimization. All
calculations for capacitors and resistors should be used as
the first approximation for selecting the closest standard
value.
POWER SUPPLY AND REFERENCE
The supply voltage (V
DD
) is nominally 12V 10%. A
100nF bypass capacitor to ground should be placed as
close as possible to V
DD
. A 6.9V voltage reference output
(V
REF
) is provided to set the speed command and current
limit of the ML4425. A 137k
W from R
REF
to GND is
required to set up a reference current for internal
functions.
OUTPUT DRIVERS
The output drivers LA, LB, LC, HA, HB, and HC provide
totem pole output drive signals for a 3 phase bridge power
stage. All control functions in the ML4425 translate to
outputs at these pins. LA, LB, and LC provide the low-side
drive signals for phases A, B, and C of the 3 phase power
stage and are 12V active high signals. HA, HB, and HC
provide the high-side signals and are 12V active low
signals.
MOTOR
PHASE C
MOTOR
PHASE B
MOTOR
PHASE A
VMOTOR
12V
RSENSE
DC SUPPLY
CAPACITOR
HA
LA
HB
LB
HC
LC
Figure 1. Using R
SENSE
in a 3-Phase 12V Power Stage
7
ML4425
CURRENT LIMITING IN THE POWER STAGE
The current sense resistor (R
SENSE
) shown in Figure 1
regulates the maximum current in the power stage and
the BLDC motor. Current regulation is accomplished by
shutting off the output drivers LA, LB, and LC for a fixed
amount of time if the voltage across R
SENSE
exceeds the
current limit threshold.
I
LIMIT
The voltage on the I
LIMIT
pin sets the current limit
threshold. The ML4425 has an internal voltage divider
from V
REF
that sets a default current limit threshold of
2.3V (see Figure 2). An external voltage divider
referenced to V
REF
can be used to override the default
I
LIMIT
setting. The external divider should have at least 10
times the current flow of the internal divider.
R
SENSE
The function of R
SENSE
is to provide a voltage
proportional to the motor current to set the current limit
trip point. The default trip voltage across R
SENSE
is
460mV, set by the internal I
LIMIT
divider ratio. The current
sense resistor should be a low inductance resistor such as
a carbon composition. For resistors in the milliohms range,
wire-wound resistors tend to have low values of
inductance. R
SENSE
should be sized to handle the power
dissipation (I
MAX2
R
SENSE
).
I
SENSE
Filter
The I
SENSE
RC lowpass filter is placed in series with the
current sense signal as shown in Figure 2. The purpose of
this filter is to remove the diode reverse recovery
shootthrough current. This current causes a voltage spike
on the leading edge of the current sense signal which
may falsely trigger the current limit. The current sense
voltage waveform is shown before and after filtering in
Figure 3. The recommended starting values for this circuit
are R = 1k
W and C = 330pF. This gives a time constant of
330ns, and will filter out spikes of shorter duration. C can
be increased to as much as 2.2nF, but should not exceed
a time constant of more than a few microseconds.
C
IOS
When I
SENSE
exceeds 0.2
I
LIMIT
, the current limit one-
shot is activated, turning off LA, LB, and LC for a fixed
amount of time (t
OFF
). t
OFF
is set by the amount of
capacitance connected to C
IOS
. C
IOS
is usually set for a
fixed off time equal to or less than the PWM period. For a
25kHz PWM frequency, the PWM period is 40s; t
OFF
should be between 20s and 40s. The lower limit of t
OFF
is dictated by the minimum on time of the power stage; a
safe approximation is 5s or less. The equation for finding
the C
IOS
capacitance value is as follows:
C
t
A
V
OS
OFF
=
50
2 4
m
.
(1)
FUNCTIONAL DESCRIPTION
(Continued)
Figure 2. Current Sense Circuitry
5
ILIMIT
ISENSE
FROM
RSENSE
PWM
ON/OFF
+
VREF
CIOS
16k
2.9V
0V
STOP
30A
START
8k
VREF
S
R
Q
Q
Figure 3. Current Sense Resistor Waveforms
(a) Without Filtering, and (b) With Filtering
(a)
0V
460mV
(b)
COMMUTATION CONTROL
A 3-phase BLDC motor requires electronic commutation
to achieve rotational motion. Electronic commutation
requires the switching on and off of the power switches of
a 3-phase half bridge. For torque production to be
achieved in one direction, the commutation is dictated by
the rotor position. Electronic commutation in the ML4425
is achieved by turning on and off, in the proper sequence,
one N output from one phase and one P output from
another phase. There are six combinations of N and P
outputs (six switching states) that constitute a full
commutation cycle. These combinations are illustrated in
Table 1 and Figure 4, and are labeled states A through F.
This sequence is programmed into the commutation state
machine. Clocking of the commutation state machine is
provided by a voltage controlled oscillator (VCO).
8
ML4425
OUTPUTS
INPUT
STATE
LA
LB
LC
HA
HB
HC
SAMPLING
R
OFF
ON
OFF
ON
OFF
ON
N/A
A
OFF
OFF
ON
ON
OFF
OFF
FB B
B
OFF
OFF
ON
OFF
ON
OFF
FB A
C
ON
OFF
OFF
OFF
ON
OFF
FB C
D
ON
OFF
OFF
OFF
OFF
ON
FB B
E
OFF
ON
OFF
OFF
OFF
ON
FB A
F
OFF
ON
OFF
ON
OFF
OFF
FB C
Table 1. Commutation State Functions
Figure 4. Output Commutation Sequence Timing Diagram
Cycle 1 - Full Commutation, Cycle 2 - Commutation with 50% PWM Duty Cycle
HIGH
SIDE
DRIVE
OUTPUTS
HA
HB
HC
LOW
SIDE
DRIVE
OUTPUTS
LA
A
B
C
D
E
F
A
B
C
D
E
F
LB
LC
Voltage Controlled Oscillator (VCO)
The VCO provides a TTL compatible clock output on the
VCO/TACH pin proportional to the VCO input voltage at
the SPEED FB pin. The proportion of frequency to voltage
(VCO constant, K
v
) is set by an 80.6k
W resistor on R
VCO
and a capacitor on C
VCO
as shown in Figure 5. R
VCO
sets
up a current proportional the VCO input voltage at SPEED
FB. This current is used to charge and discharge C
VCO
between the threshold voltages of 2.3V and 4.3V. The
resulting triangle wave on C
VCO
corresponds to the clock
on VCO. K
v
should be set so that the VCO output
frequency corresponds to the maximum commutation
frequency or maximum motor speed when the VCO input
is equal to or slightly less than V
REF
. C
VCO
is calculated
using the following equation:
C
V
Hz Farad
V
Hz
RPM
N SPEED
VCO
MAX
=
-
6 5
3101 10
0 05
6
.
.
.
(2)
The closest standard value that is equal to or less than the
calculated C
VCO
should be used.
FUNCTIONAL DESCRIPTION
(Continued)
9
ML4425
The maximum frequency on the VCO pin is found by:
f
N RPM
MAX
MAX
=
0 05
.
(3)
The voltage at the VCO/TACH pin is equal to the rotor
speed. The voltage at SPEED FB is controlled by the back
EMF sampler.
BACK EMF SAMPLER
The input to the voltage controlled oscillator is the back
EMF sampler. The back EMF sense pins FB A, FB B, and
FB C inputs to the back EMF sampler require a signal
from the motor phase leads that is below the V
DD
of the
ML4425. The phase sense input impedance is 8k
W. This
requires a series resistor RES1 from the motor phase lead
as shown in Figure 6 based on the following equation:
RES
V
V
V
MOTOR
1 670
10
=
-
W
/
1
6
(4)
The back EMF sampler takes the motor phase voltages
divided down to signals that are less than V
DD
(12V
nominal) and calculates the neutral point of the motor by
the following equation:
Neutral
PH
PH
PH
=
+
+
1
2
3
3
(5)
This allows the ML4425 to compare the back EMF signal
to the motor's neutral point without the need for bringing
out an extra wire on a WYE wound motor. For DELTA
wound motors there is no physical neutral to bring out, so
this reference point must be calculated in any case.
The back EMF sampler measures the motor phase that is
not driven (i.e. if LA and HB are on, then phase A is
driven low, phase B is driven high, and phase C is
FUNCTIONAL DESCRIPTION
(Continued)
Figure 5. External VCO Component Connections
CVCO
CVCO
4.3V
0V
5V
2.3V
RVCO
SPEED
FB
CVCO
RVCO
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
VCO/TACH
RESET
(FROM CAT)
FROM
BACK EMF
SAMPLER
& RAMP
GENERATOR
NEUTRAL
SIMULATOR
A +
B +
C
6
MULTIPLEXER
COMMUTATION
STATE MACHINE
gm =
1
8k
4k
4k
4k
4k
4k
4k
+
SIGN
CHANGER
TO
SPEED FB
FB A
RES1
RES2
RES3
FB B
FB C
F/R
MOTOR
C
F/R
MOTOR
B
MOTOR
A
Figure 6. Back EMF Sampler Detailed Block Diagram
sampled). The sampled phase provides a back EMF signal
that is compared against the neutral of the motor. The
sampler is controlled by the commutation state machine.
The sampled back EMF is compared to the neutral through
an error amplifier. The output of the error amplifier outputs
a charging or discharging current to SPEED FB, which
provides the control voltage to the VCO.
10
ML4425
FB A
22
FB B
23
FB C
24
BACK
EMF
SAMPLER
VDD
500nA
SPEED
FB
C
SPEEDFB1
C
SPEEDFB2
R
SPEEDFB
20
VOLTAGE
CONTROLLED
OSCILLATOR
PHASE
LOCKED
LOOP
VCO/TACH
13
A
B
C
D
E
F
R
COMMUTATION
STATE MACHINE
BACK EMF SENSING PLL COMMUTATION CONTROL
Three blocks form a phase locked loop that locks the
commutation clock onto the back EMF signal: the
commutation state machine, the voltage controlled
oscillator, and the back EMF sampler. The complete phase
locked loop is illustrated in Figure 7. The phased locked
loop requires a lead lag filter that is set by external
components on SPEED FB. The components are selected
as follows:
C
K
M
N
d
f
SPEEDFB
O
S
VCO
1
1
2
2
2
0 25
100
=
.
ln
(6a)
R
M
d
f
N
K
M
SPEEDFB
VCO
S
O
=
-
2
100
1
1
ln
0 5
(6b)
C
C
M
SPEEDFB
SPEEDFB
2
1
1
=
-
0 5
(6c)
START-UP SEQUENCE
When power is first applied to the ML4425 and the motor
is at rest, the back EMF is equal to zero. The motor needs
to be rotating for the back EMF sampler to lock onto the
rotor position and commutate the motor. The ML4425 uses
an open loop start-up technique to bring the rotor from rest
up to a speed fast enough to allow back EMF sensing.
Start-up is comprised of three modes: align mode, ramp
mode, and run mode.
Align Mode (RESET)
Before the motor can be started, the rotor must be in a
known position. When power is first applied to the
ML4425, the controller is reset into the align mode. Align
mode turns on the output drivers LB, HA, and HC which
aligns the motor into a position 30 electrical degrees
before the center of the first commutation state. This is
shown as state R in the commutation states of Table 1.
Align mode must last long enough to allow the motor and
its load to settle into this position. The align mode time is
set by a capacitor connected to the C
AT
pin as shown in
Figure 8. C
AT
is charged by a constant 750A current from
GND to 1.5 V until the align comparator trips to end the
align mode. A starting point for C
AT
is calculated as
follows:
C
t
amp
V
AT
S
=
-
7 5 10
15
7
.
.
(7)
If the align time is not long enough to allow the rotor to
settle for reliable starting, then increase C
AT
until the
desired performance is achieved.
FUNCTIONAL DESCRIPTION
(Continued)
Ramp Mode
At the end of align mode the controller goes into ramp
mode. Ramp mode starts commutating through the states
A through F as shown in Table 1. This ramps up the
commutation frequency, and therefore the motor speed,
for a fixed length of time. This allows the motor to reach a
sufficient speed for the back EMF sampler to lock
commutation onto the motor's back EMF. The amount of
time the ML4425 stays in ramp mode is determined by a
capacitor connected to the C
RT
pin as shown in Figure 8.
C
RT
is charged by a constant 750A current from GND to
1.5 V until the ramp comparator trips to end the ramp
mode. This gives a fixed ramp time. C
RT
is calculated as
follows:
C
J
amp K
I
K
N
RT
V
MAX
t
=
-
2
5 10
3
7
p
(8)
The rate at which the ML4425 ramps up the motor speed
is determined by a fixed 500A current source on the
SPEED FB pin. The current sources charges up the PLL
filter components causing the VCO frequency to ramp up.
During ramp mode, the back EMF sampler is disabled to
allow control of the ramping to be set only by the 500A
current source. The ramp based on the SPEED FB filter is
generally too fast for the motor to keep up, so a capacitor
from C
RR
to SPEED FB can be added to slow down the
ramping rate. The optimal ramp rate is based on the motor
and load parameters and is can be adjusted by varying
the value of C
RR
.
Figure 7. Back EMF Commutation Phase Locked Loop
11
ML4425
CAT
CAT
FB A
FB B
FB C
BACK
EMF
SAMPLER
CRT
CRT
CRR
+
1.5V
750nA
+
1.5V
750nA
VDD
VDD
CRR
500nA
VDD
SPEED
FB
TO
SPEED FB
FILTER
CVCO
RVCO
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run
mode. In run mode, the back EMF sensing is enabled and
commutation is now under the control of the phase locked
loop. Motor speed is now regulated by the speed control
loop.
PWM SPEED CONTROL
Speed control is accomplished by setting a speed
command at SPEED SET with an input voltage from 0 to
6.9V (V
REF
). The accuracy of the speed command is
determined by the external components R
VCO
and C
VCO
.
There are a number of methods that can be used to control
the speed command of the ML4425. One is to use a 10k
W
potentiometer from V
REF
to ground with the wiper
connected to SPEED SET. If SPEED SET is controlled from
a microcontroller, one of its DACs can be used with V
REF
as its input reference.
The speed command is compared with the sensed speed
from SPEED FB through a transconductance error
amplifier. The output of the speed error amplifier is SPEED
COMP. SPEED COMP is clamped between one diode drop
above 3.9V (approximately 4.6V) and one diode drop
below 1.7V (approximately 1V) to prevent speed loop
"wind-up". Speed loop compensation components are
connected to this pin as shown in Figure 9. The speed loop
compensation components are calculated as follows:
C
N V
C
f
K
m
f
SC
MOTOR
VCO
SB
e
SB
=
+
26 9
25 98 696
2
2
.
.
.
t
(9a)
R
f
C
SC
SB
SC
=
10
2
p
(9b)
Where f
SB
is the speed loop bandwidth in Hz.
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
+
+
SPEED SET
SPEED COMP
3.9V
1.7V
10k
20kHz
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
FROM
SPEED FB
TO
GATING
LOGIC &
OUTPUT
DRIVERS
CT
CT
CSC
RSC
1.7V
VREF
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp
oscillator creates a sawtooth function from 1.7V to 3.9V
as shown in Figure 9. A negative clamp at one diode drop
below 1.7V (approximately 1V) starts the oscillator on
power up. The frequency of the ramp oscillator is set by a
capacitor to ground C
IOS
and is selected using the
following equation:
C
f
A
V
T
PWM
=
1
50
2 4
m
.
(10)
Where f
PWM
is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current
limit one shot that controls the LA, LB, and LC output
drivers.
Figure 9. Speed Control Loop Component Connections
12
ML4425
CROSS CONDUCTION COMPARATOR
When the ML4425 goes from align mode into ramp mode,
there is a possibility of cross conduction in phase 3 of the
bridge power stage. This cross conduction can happen
when HC is on in the align mode shown as state R in
Table 1, and the controller transitions to state A in ramp
mode where HC is turned off and LC is turned on. Cross
conduction can appear due to the differences in turn on
and turn off times of the power devices. To solve this
problem, the LC output driver is gated off until the HC is
equal to V
DD
3V as shown in Figure 10.
BRAKING
When the BRAKE pin is pulled below 1.4V, the low side
output drivers LA, LB, and LC are turned on and the high
side output drivers HA, HB, HC are turned off. Braking
causes rapid deceleration of the motor and current
limiting is de-activated, and care should be taken when
using the BRAKE pin. BRAKE is has an internal 4k
W pull-
up as shown in Figure 10, and can be driven by a switch
to ground, an open collector or drain logic signal, or a TTL
logic signal.
UNDERVOLTAGE LOCKOUT
Undervoltage lockout is used to protect the 3-phase
bridge power stage from a low V
DD
condition.
Undervoltage is triggered at V
DD
of 9.5V or less and is
indicated by a TTL low output on the UV FAULT pin.
Undervoltage lockout also turns off all output drivers (LA,
LB, LC, HA, HB, and HC). The comparator that triggers
undervoltage lockout has 150mV of hystresis.
DESIGN CONSIDERATIONS
INTERFACING TO A 3-PHASE BRIDGE POWER STAGE
The ML4425 output drivers are configured to drive a 3
phase bridge power stage. For applications with buss
voltages from 12V up to 80V, level shifting circuitry can
be used to drive higher voltage P-channel MOSFETS for
the high side switches as shown in Figure 11.
The most flexible configuration is to use high side drivers
to control N-Channel MOSFETs (or IGBTs) which allows
applications from less than 12V up to 600V. Figure 12
shows the interface between the ML4425 and IR2118 high
side drivers from International Rectifier. This configuration
is capable of driving motors from busses of up to 320V.
The BRAKE pin can be pulsed prior to startup with an RC
circuit. This charges the bootstrap capacitors (C19, C20,
and C21) for the three high side drivers, allowing the reset
phase to operate normally. These capacitors must be sized
so that they stay sufficiently charged during the align
mode. Refer to AN-43 for additional applications
information on the ML4425.
FUNCTIONAL DESCRIPTION
(Continued)
2
4
3
9
10
HA
HB
HC
LA
LB
GATING
LOGIC
&
OUTPUT
DRIVERS
+
1.4V
9.5V
25
BRAKE
VDD
4k
14
VDD
28
GND
27
RREF
11
LC
REFERENCE
18
UV FAULT
7
VREF
FROM
COMMUTATION
STATE MACHINE
FROM
SPEED CONTROL LOOP
& CURRENT LIMIT
+
Figure 10. Cross Conduction, Brake, and UVLO Circuits
13
ML4425
Figure 11. Driving Lower Voltage Motors (12 to 80V)
R19
80.5k
BRAKE
RUN
R10 (RES1)
R9 (RES1)
R8 (RES1)
S1
C16
330pF
MOTOR
C5
2.2nF
R16
10k
R14
2k
C17
1nF
C9
100nF
C12
R18
10k
R21
787
R6
100
R5
100
R7
100
C14
1F
C13
100nF
Q7
IRFR120
Q8
IRFR120
Q9
IRFR120
R1
470m
2W
VBUSS
24V80V
C1
100nF
100V
C2
330F
100V
R2
10k
Q1
2N6718
C15
470nF
12V
Q4
IRFR9120
R3
10k
Q2
2N6718
Q5
IRFR9120
R4
10k
Q3
2N6718
R15
1k
R13
2k
R12
2k
Q6
IRFR9120
C3
1F
ML4425
ISENSE
HA
HB
HC
SPEED COMP
CT
VREF
SPEED SET
LA
LB
LC
ILIMIT
VCO/TACH
VDD
GND
RREF
CIOS
BRAKE
FB C
FB B
FB A
CRR
SPEED FB
CRT
UV FAULT
CAT
RVCO
CVCO
R20
137k
C4
C8
1F
C14
R17
10k
C7
100nF
C6
1F
12V
14
ML4425
R16
80.6k
BRAKE
RUN
R13 (RES1)
R14 (RES1)
R15 (RES1)
S1
C14
330pF
MOTOR
C1
2.2nF
R5
10k
C4
1nF
C3
100nF
C15
100nF
R20
10k
R19
787
R11
100
R10
100
R9
100
D4
D5
D6
(3
1N5819)
C7
100nF
Q2
IRF720
Q4
IR720
Q6
IRF720
R12
470m
2W
VBUSS
24V80V
C9
470nF
12V
R6
100
Q1
IRF720
Q3
IRF720
R1
1k
Q5
IRF720
ML4425
R18
137k
C6
1F
C8
10nF
C10
1F
C19
2.2F
25V
C13*
R17
10k
C11
100nF
C12
1F
12V
IR2118
VCC
IN
COM
NC
VB
HO
VS
NC
C16
100nF
25V
D1
MUR150
C5
330F
400V
C20
2.2F
25V
C17
100nF
25V
D2
MUR150
C21
2.2F
25V
C18
100nF
25V
D3
MUR150
R7
100
R8
100
IR2118
VCC
IN
COM
NC
VB
HO
VS
NC
IR2118
VCC
IN
COM
NC
VB
HO
VS
NC
ISENSE
HA
HB
HC
SPEED COMP
CT
VREF
SPEED SET
LA
LB
LC
ILIMIT
VCO/TACH
VDD
GND
RREF
CIOS
BRAKE
FB C
FB B
FB A
RAMP COMP
SPEED FB
CRT
UV FAULT
CAT
RVCO
CVCO
BOOTSTRAP
PRE-CHARGE
CAPACITOR
Figure 12. ML4425 High Voltage Motor Drive Application Circuit
15
ML4425
PHYSICAL DIMENSIONS
inches (millimeters
0.048 MAX
(1.20 MAX)
SEATING PLANE
0.354 BSC
(9.00 BSC)
0.276 BSC
(7.00 BSC)
1
0.276 BSC
(7.00 BSC)
0.354 BSC
(9.00 BSC)
9
25
17
0.032 BSC
(0.8 BSC)
PIN 1 ID
0.012 - 0.018
(0.29 - 0.45)
0.037 - 0.041
(0.95 - 1.05)
0.018 - 0.030
(0.45 - 0.75)
0.003 - 0.008
(0.09 - 0.20)
0 - 8
Package: H32-7
32-Pin (7 x 7 x 1mm) TQFP
Package: P28N
28-Pin Narrow PDIP
SEATING PLANE
0.280 - 0.296
(7.11 - 7.52)
PIN 1 ID
0.299 - 0.325
(7.60 - 8.26)
1.355 - 1.365
(34.42 - 34.67)
0.015 - 0.021
(0.38 - 0.53)
0.100 BSC
(2.54 BSC)
0.008 - 0.012
(0.20 - 0.31)
0.020 MIN
(0.51 MIN)
28
0 - 15
1
0.045 - 0.055
(1.14 - 1.40)
0.180 MAX
(4.57 MAX)
0.125 - 0.135
(3.18 - 3.43)
16
ML4425
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4425CP
0C to 70C
28-Pin PDIP (P28N)
ML4425CS
0C to 70C
28-Pin SOIC (S28)
ML4425CH (Obsolete)
0C to 70C
32-Pin TQFP (H32-7)
ML4425IP
40C to 85C
28-Pin PDIP (P28N)
ML4425IS
40C to 85C
28-Pin SOIC (S28)
ML4425IH (Obsolete)
40C to 85C
32-Pin TQFP (H32-7)
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
www.microlinear.com
7/6/98 Printed in U.S.A.
Micro Linear 1998.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653;. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
PIN 1 ID
0.398 - 0.412
(10.11 - 10.47)
0.699 - 0.713
(17.75 - 18.11)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.022 - 0.042
(0.56 - 1.07)
0.095 - 0.107
(2.41 - 2.72)
0.005 - 0.013
(0.13 - 0.33)
0.090 - 0.094
(2.28 - 2.39)
28
0.009 - 0.013
(0.22 - 0.33)
0 - 8
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
Package: S28
28-Pin SOIC
DS4425-01
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