June 1997

ML4826

PFC and Dual Output PWM Controller Combo

GENERAL DESCRIPTION

The ML4826 is a high power controller for power factor
corrected, switched mode power supplies. PFC allows the
use of smaller, lower cost bulk capacitors, reduces power
line loading and stress on the switching FETs, and results
in a power supply that fully complies with IEC1000-3-2
specifications. The ML4826 includes circuits for the
implementation of a leading edge, average current "boost"
type power factor correction and a trailing edge, pulse
width modulator (PWM) with dual totem-pole outputs.

The device is available in two versions; the ML4826-1
(f

PWM

= f

PFC

) and the ML4826-2 (f

PWM

= 2 x f

PFC

Doubling the switching frequency of the PWM allows the
user to design with smaller output components while
maintaining the optimum operating frequency for the PFC.
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brown-out protection. The PWM section can be operated
in current or voltage mode at up to 250kHz and includes a
duty cycle limit to prevent transformer saturation.

FEATURES

Internally synchronized PFC and PWM in one IC

Low total harmonic distortion

Reduced ripple current in the storage capacitor
between the PFC and PWM sections

Average current, continuous boost, leading edge PFC

High efficiency trailing edge PWM with dual
totem-pole outputs

Average line voltage compensation with brown-out
control

PFC overvoltage comparator eliminates output
"runaway" due to load removal

Current-fed multiplier for improved noise immunity

Overvoltage protection, UVLO, and soft start

BLOCK DIAGRAM

* This Part Is End Of Life As Of August 1, 2000

VCC2

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

RTCT

OSCILLATOR

OVP

PFC ILIMIT

UVLO

VREF

PULSE WIDTH MODULATOR

POWER FACTOR CORRECTOR

2.5V

7.5V

REFERENCE

VCC

VCCZ

VEA

IEA

PFC OUT

2.7V

-1V

RAMP 2

PWM 1

VDC

DC ILIMIT

VCC

DUTY CYCLE

LIMIT

2.5V

VFB

VIN OK

GAIN

MODULATOR

VCCZ

x 2

(-2 VERSION ONLY)

3.5k

1.5V

50�A

13.5V

DC ILIMIT

RAMP 1

PWM 2

VCC2

PGND

AGND

ML4826

PIN CONFIGURATION

PIN DESCRIPTION

PIN

NAME

FUNCTION

AGND

Analog signal ground

PGND

Return for the PWM totem-pole
outputs

PWM 2

PWM driver 2 output

PWM 1

PWM drive 1 output

PFC OUT

PFC driver output

CC2

Positive supply for the PWM drive
outputs

CC1

Positive supply (connected to an
internal shunt regulator).

REF

Buffered output for the internal 7.5V
reference

PFC transconductance voltage error
amplifier input

VEAO

PFC transconductance voltage error
amplifier output

PIN

NAME

FUNCTION

IEAO

PFC transconductance current error
amplifier output

PFC gain control reference input

SENSE

Current sense input to the PFC current
limit comparator

RMS

Input for PFC RMS line voltage
compensation

Connection point for the PWM soft start
capacitor

PWM voltage feedback input

Connection for oscillator frequency
setting components

RAMP 1

PFC ramp input

RAMP 2

When in current mode, this pin
functions as the current sense input;
when in voltage mode, it is the PWM
input from the PFC output (feedforward
ramp)

DC I

LIMIT

PWM current limit comparator input

IEAO

SENSE

RMS

RAMP 1

RAMP 2

DC I

LIMIT

VEAO

REF

CC2

CC1

PFC OUT

PWM 1

PWM 2

PGND

AGND

TOP VIEW

ML4826

20-Pin PDIP (P20)

20-Pin SOIC (S20)

ML4826

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Shunt Regulator Current .................................. 55mA

SENSE

Voltage ................................................... �3V to 5V

Voltage on Any Other Pin .... GND � 0.3V to V

CCZ

+ 0.3V

REF ...........................................................................................

20mA

Input Current .................................................... 10mA

Peak PFC OUT Current, Source or Sink ................ 500mA
Peak PWM OUT Current, Source or Sink ............. 500mA
PFC OUT, PWM 1, PWM 2 Energy Per Cycle .......... 1.5mJ

Junction Temperature .............................................. 150

�

Storage Temperature Range ......................�65

�

C to 150

�

Lead Temperature (Soldering, 10 sec) ..................... 260

�

Thermal Resistance (

)

Plastic DIP ....................................................... 67

�

C/W

Plastic SOIC ..................................................... 95

�

C/W

OPERATING CONDITIONS

Temperature Range

ML4826CX ................................................ 0

�

C to 70

�

ML4826IX .............................................. �40

�

C to 85

�

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, I

= 25mA, R

RAMP 1

= R

= 52.3k

, C

RAMP1

= C

= 180pF,

= Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

120

Feedback Reference Voltage

2.4

2.5

2.6

Input Bias Current

Note 2

�0.3

�1.0

�

Output High Voltage

6.0

6.7

Output Low Voltage

0.6

1.0

Source Current

�

0.5V, V

OUT

= 6V

�40

�80

�

Sink Current

�

0.5V, V

OUT

= 1.5V

�

Open Loop Gain

Power Supply Rejection Ratio

CCZ

� 3V < V

< V

CCZ

� 0.5V

CURRENT ERROR AMPLIFIER

Input Voltage Range

-1.5

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

130

195

310

Input Offset Voltage

�

Input Bias Current

�0.5

�1.0

�

Output High Voltage

6.0

6.7

Output Low Voltage

0.6

1.0

Source Current

�

0.5V, V

OUT

= 6V

�40

�90

�

Sink Current

�

0.5V, V

OUT

= 1.5V

�

Open Loop Gain

Power Supply Rejection Ratio

CCZ

� 3V < V

< V

CCZ

� 0.5V

�

ML4826

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OVP COMPARATOR

Threshold Voltage

2.6

2.7

2.8

Hysteresis

115

150

PFC I

LIMIT

COMPARATOR

Threshold Voltage

�0.8

�1.0

�1.15

(

PFC I

LIMIT

- Gain Modulator Output)

100

190

Delay to Output

150

300

DC I

LIMIT

COMPARATOR

Threshold Voltage

0.9

1.0

1.1

Input Bias Current

�

0.3

�

Delay to Output

150

300

OK COMPARATOR

Threshold Voltage

2.4

2.5

2.6

Hysteresis

0.8

1.0

1.2

GAIN MODULATOR

Gain (Note 3)

= 100

�

A, V

RMS

= V

= 0V

0.36

0.55

0.66

= 50

�

A, V

RMS

= 1.2V, V

= 0V

1.20

1.80

2.24

= 50

�

A, V

RMS

= 1.8V, V

= 0V

0.55

0.80

1.01

= 100

�

A, V

RMS

= 3.3V, V

= 0V

0.14

0.20

0.26

Bandwidth

IAC = 100

�

MHz

Output Voltage

= 250

�

A, V

RMS

= 1.15V,

0.72

0.82

0.95

= 0V

OSCILLATOR

Initial Accuracy

= 25

�

180

190

200

kHz

Voltage Stability

CCZ

� 3V < V

< V

CCZ

� 0.5V

Temperature Stability

Total Variation

Line, Temp

170

210

kHz

Ramp Valley to Peak Voltage

2.5

Dead Time

PFC Only

-1 Suffix

125

310

-2 Suffix

250

500

Discharge Current

RAMP 1

= 0V, V(R

) = 2.5V

4.5

7.5

9.5

RAMP 1 Discharge Current

REFERENCE

Output Voltage

= 25

�

C, I(V

REF

) = 1mA

7.4

7.5

7.6

Line Regulation

CCZ

� 3V < V

< V

CCZ

� 0.5V

Load Regulation

1mA < I(V

REF

) < 20mA

Total Variation

Line, Load, Temp

7.25

7.65

Long Term Stability

= 125

�

C, 1000 Hours

ML4826

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PFC

Minimum Duty Cycle

ML4826-1, V

IEAO

> 4.0V

ML4826-2, V

IEAO

> 5.7V

Maximum Duty Cycle

IEAO

< 1.2V

Output Low Voltage

OUT

= �20mA

0.4

0.8

OUT

= �50mA

0.6

3.0

OUT

= 10mA, V

= 8V

0.7

1.5

Output High Voltage

OUT

= 20mA

9.5

10.5

OUT

= 50mA

9.0

Rise/Fall Time

= 1000pF

PWM

Duty Cycle Range

0-47

0-48

0-50

Output Low Voltage

OUT

= �20mA

0.4

0.8

OUT

= �50mA

0.6

3.0

OUT

= 10mA, V

= 8V

0.7

1.5

Output High Voltage

OUT

= 20mA

9.5

10.5

OUT

= 50mA

9.0

Rise/Fall Time

= 1000pF

SUPPLY

Shunt Regulator Voltage (V

CCZ

)

12.8

13.5

14.2

CCZ

Load Regulation

25mA < I

< 55mA

�

150

�

300

CCZ

Total Variation

Load, temp

12.4

14.6

Start-up Current

= 11.2V, C

= 0

0.7

1.1

Operating Current

< V

CCZ

� 0.5V, C

= 0

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

2.65

3.0

3.35

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

pin.

Note 3: Gain = K x 5.3V; K = (I

GAINMOD

- I

OFFSET

) x I

x (VEAO - 1.5V)

-1

ML4826

FUNCTIONAL DESCRIPTION

The ML4826 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM's line regulation. In
either mode, the PWM stage uses conventional trailing-
edge duty cycle modulation, while the PFC uses leading-
edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC error
amplifier bandwidth, and can significantly reduce the size
of the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4826-1 runs at the same frequency
as the PFC. The PWM section of the ML4826-2 runs at
twice the frequency of the PFC, which allows the use of
smaller PWM output magnetics and filter capacitors while
holding down the losses in the PFC stage power
components.

In addition to power factor correction, a number of
protection features have been built into the ML4826. These
include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with, and proportional to,
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of a most
power supplies, which use a bridge rectifier and capacitive
input filter fed from the line. The peak-charging effect
which occurs on the input filter capacitor in such a supply
causes brief high-amplitude pulses of current to flow from
the power line, rather than a sinusoidal current in phase
with the line voltage. Such a supply presents a power
factor to the line of less than one (another way to state this
is that it causes significant current harmonics to appear at
its input). If the input current drawn by such a supply (or
any other non-linear load) can be made to follow the input
voltage in instantaneous amplitude, it will appear resistive
to the AC line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with, and proportional to, the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4826 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full wave
rectified AC line voltage. No filtering is applied following
the bridge rectifier, so the input voltage to the boost
converter ranges, at twice line frequency, from zero volts
to the peak value of the AC input and back to zero. By
forcing the boost converter to meet two simultaneous

conditions, it is possible to ensure that the current which
the converter draws from the power line agrees with the
instantaneous line voltage. One of these conditions is that
the output voltage of the boost converter must be set
higher than the peak value of the line voltage. A
commonly used value is 385VDC, to allow for a high line
of 270VAC

rms

. The other condition is that the current

which the converter is allowed to draw from the line at
any given instant must be proportional to the line voltage.
The first of these requirements is satisfied by establishing a
suitable voltage control loop for the converter, which in
turn drives a current error amplifier and switching output
driver. The second requirement is met by using the
rectified AC line voltage to modulate the output of the
voltage control loop. Such modulation causes the current
error amplifier to command a power stage current which
varies directly with the input voltage. In order to prevent
ripple which will necessarily appear at the output of the
boost circuit (typically about 10VAC on a 385V DC level)
from introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

, which linearizes

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4826 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4826. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage

(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
I

. Sampling current in this way minimizes ground

noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.

2) A voltage proportional to the long-term rms AC line

voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V

RMS

. The gain modulator's output is

inversely proportional to V

RMS2

(except at unusually

low values of V

RMS

where special gain contouring takes

over to limit power dissipation of the circuit
components under heavy brown-out conditions). The
relationship between V

RMS

and gain is designated as K,

and is illustrated in the Typical Performance
Characteristics.

ML4826

FUNCTIONAL DESCRIPTION

(Continued)

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

3) The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

VEAO

GAINMOD

RMS

�

More exactly, the output current of the gain modulator is
given by:

VEAO

GAINMOD

�

(

)

�

� .

1 5

(1)

where K is in units of V

-1

Note that the output current of the gain modulator is
limited to

200

�

Current Error Amplifier

The current error amplifier's output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input to
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I

SENSE

(current into I

SENSE

/3.5k

). The negative voltage

on I

SENSE

represents the sum of all currents flowing in the

PFC circuit, and is typically derived from a current sense
resistor in series with the negative terminal of the input
bridge rectifier. In higher power applications, two current
transformers are sometimes used, one to monitor the I

the boost MOSFET(s) and one to monitor the I

of the

boost diode. As stated above, the inverting input of the
current error amplifier is a virtual ground. Given this fact,
and the arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from
the gain modulator will cause the output stage to increase
its duty cycle until the voltage on I

SENSE

is adequately

negative to cancel this increased current. Similarly, if the
gain modulator's output decreases, the output duty cycle
will decrease, to achieve a less negative voltage on the
I

SENSE

pin.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be

the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

Cycle-By-Cycle Current Limiter

The I

SENSE

pin, as well as being a part of the current

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to V

. When the

voltage on V

exceeds 2.7V, the PFC output driver is shut

down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at V

drops below 2.58V.

The V

should be set at a level where the active and

passive external power components and the ML4826 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

2.5V

VEA

IEA

VREF

AGND

PFC

OUTPUT

GAIN

MODULATOR

ML4826

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 3 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation
is returned to V

REF

to produce a soft-start characteristic on

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier's
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4826's voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (V

) to deviate from its 2.5V (nominal)

value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This increases the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.

The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage
loop. It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information
for the design of this class of PFC.

Main Oscillator (R

)

The oscillator frequency is determined by the values of R

and C

, which determine the ramp and off-time of the

oscillator output clock:

OSC

RAMP

DEADTIME

(2)

The deadtime of the oscillator is derived from the
following equation:

DEADTIME

�

2 5

5 1

490

(3)

at V

REF

= 7.5V:

RAMP

�

0 51

The ramp of the oscillator may be determined using:

V
V

RAMP

REF

�

� .
� .

1 25
3 75

(4)

The deadtime is so small (t

RAMP

>> t

DEADTIME

) that the

operating frequency can typically be approximated by:

OSC

RAMP

(5)

For proper reset of internal circuits during dead time,
values of 1000pF or greater are suggested for C

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

kHz

OSC

RAMP

200

RAMP

�

= �

0 51 1 10

Solving for R

x C

yields 2 x 10

-4

. Selecting standard

components values, C

= 1000pF, and R

= 8.63k

The deadtime of the oscillator adds to the Maximum
PWM Duty Cycle (it is an input to the Duty Cycle Limiter).
With zero oscillator deadtime, the Maximum PWM Duty
Cycle is typically 45%. In many applications, care should
be taken that C

not be made so large as to extend the

Maximum Duty Cycle beyond 50%.

FUNCTIONAL DESCRIPTION

(Continued)

ML4826

FUNCTIONAL DESCRIPTION

(Continued)

PFC RAMP (RAMP1)

The intersection of RAMP1 and the boost current error
amplifier output controls the PFC pulse width. RAMP1 can
be generated in a similar fashion to the R

ramp.

The current error amplifier maximum output voltage has a
minimum of 6V. The peak value of RAMP1 should not
exceed that voltage. Assuming a maximum voltage of 5V
for RAMP1, Equation 6 describes the RAMP1 time. With a
100kHz PFC frequency, the resistor tied to V

REF

, and a

150pF capacitor, Equation 7 solves for the RAMP1 resistor.

RAMP

REF

RAMP

1 1

�

(6)

RAMP

1 1

1 1 150

�

(7)

VREF

ML4826

RAMP1

150pF

60k

Figure 3.

PMW SECTION

Pulse Width Modulator

The PWM section of the ML4826 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at the PFC frequency in the ML4826-1, and at
twice the PFC frequency in the ML4826-2). The PWM is
capable of current-mode or voltage mode operation. In
current-mode applications, the PWM ramp (RAMP2) is
usually derived directly from a current sensing resistor or
current transformer in the primary of the output stage, and
is thereby representative of the current flowing in the
converter's output stage. DC I

LIMIT

, which provides cycle-

by-cycle current limiting, is typically connected to RAMP
2 in such applications. For voltage-mode operation or
certain specialized applications, RAMP2 can be

connected to a separate RC timing network to generate a
voltage ramp against which V

will be compared. Under

these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC I

LIMIT

input would be used for output stage overcurrent
protection.

No voltage error amplifier is included in the PWM stage of
the ML4826, as this function is generally performed on the
output side of the PWM's isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM's RAMP2 input which allows
V

to command a zero percent duty cycle for input

voltages below 1.5V.

PWM Current Limit

The DC I

LIMIT

pin is a direct input to the cycle-by-cycle

current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output of the PWM
will be disabled until the output flip-flop is reset by the
clock pulse at the start of the next PWM power cycle.

OK Comparator

The V

OK comparator monitors the DC output of the PFC

and inhibits the PWM if this voltage on V

is less than its

nominal 2.5V. Once this voltage reaches 2.5V, which
corresponds to the PFC output capacitor being charged to
its rated boost voltage, the soft-start commences.

RAMP2

The RAMP2 input is compared to the feedback voltage
(V

) to set the PWM pulse width. In voltage mode it can

be generated using the same method used for the R

input. In current mode the primary current sense and
slope compensation are fed into the RAMP2 input.

Peak current mode control with duty cycles greater than
50% requires slope compensation for stability. Figure 4
displays the method used for the required slope
compensation. The example shown adds the slope
compensation signal to the current sense signal.
Alternatively, the slope compensation signal can also be
subtracted form the feedback signal (V

In setting up the slope compensation first determine the
down slope in the output inductor current. To determine
the actual signal required at the RAMP2 input, reflect 1/2
of the inductor downslope through the main transformer,
current sense transformer to the ramp input.

Internal to the IC is a 1.5V offset in series with the RAMP2
input. In the example show the positive input to the PWM
comparator is developed from V

REF

(7.5V), this limits the

RAMP2 input (current sense and slope compensation) to 6

ML4826

Volts peak. The composite waveform feeding the RAMP2
pin for the PWM consists of the reflected output current
signal along with the transformer magnetizing current and
the slope compensation signal.

Equation 8 describes the composite signal feeding
RAMP2, consisting of the primary current of the main
transformer and the slope compensation. Equation 9
solves for the required slope compensation peak voltage.

N
N

RAMP

PRI

OUT

1 5

+ �

�

� .

(8)

N
N

OUT

SENSE

�

= �

�

1
2

14
90

471

200

2 2

�

sec

(9)

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50

�

A supplies

the charging current for the capacitor, and start-up of the
PWM begins at 1.5V. Start-up delay can be programmed
by the following equation:

DELAY

�

1 5

�

(10)

where C

is the required soft start capacitance, and

DELAY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.

Solving for the minimum value of C

�

1 5

167

�

(11)

The ML4826 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying the part.

There are a number of different ways to supply V

to the

ML2826. The method suggested in Figure 5, is one which
keeps the ML4826 I

current to a minimum, and allows

for a loosely regulated bootstrap winding. By feeding
external gate drive components from the base of Q1, the
constant current source does not have to account for
variations in the gate drive current. This helps to keep the
maximum I

of the ML4826 to a minimum. Also, the

current available to charge the bootstrap capacitor from
the bootstrap winding is not limited by the constant

�

REF

PWM CMP

DC I

LIMIT

1.5V

R40

47.0k

R38

10.0k

R13

2.2k

RAMP2

AGND

DC I

LIMIT

R21
8.63k

Q14

2N2222

R16
471

C11
1000pF

C26

220pF

T3
200:1

SENSE

x Former

4 x IN4148

Figure 4. Slope Compensation and Current Sense

FUNCTIONAL DESCRIPTION

(Continued)

ML4826

current source. The circuit guarantees that the maximum
operating current is available at all times and minimizes
the worst case power dissipation in the IC.

Other methods such as a simple series resistor are
possible, but can very easily lead to excessive I

current

in the ML4826. Figures 6 and 7 show other possible
methods for feeding V

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the

trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation is
determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary "no-load" period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC's output ripple
voltage can be reduced by as much as 30% using this
method.

FUNCTIONAL DESCRIPTION

(Continued)

ML4826

RTN

RECTIFIED

20V

�

1500

�

39k

GATE

DRIVE

22k

MJE200

2N2222

ML4826

RTN

BIAS

�

ML4826

RTN

BIAS

Figure 5. V

Bias Circuitry

Figure 6.

Figure 7.

ML4826

Figure 10. 48V 300W Power Factor Corrected Power Supply

AC INPUT

85 TO 265VAC

470nF

BR1

6A, 600V

470k

420

�

IRF840

10k

1N4747

R10

10k

CR4

1N4747

HFA08TB60

R12

381k

R110

2.37k

C21

47nF

330

�

48VDC

100nH

C14

820

�

C11

�

RTN

D21A

MBR20100CT-ND

R35

43.2k

R32

2.37k

R25

TL431

R22

3.3k

100nF

C19

100nF

C20

100nF

C12

�

OUT A

OUT B

IN A

S RTN

IN B

FERRITE

BEAD

1N5818

R116

10k

R113

47k

IRF840

R38

10k

D17A

1N4747

D20

1N5818

R41

D19

1N5819

D25

BYM26C

R44

200

IRF840

R43

10k

D23A

1N4747

D23B

1N4747

D22

1N5818

R42

D18

1N5819

D24

BYM26C

R37

200

Q11

2N2907

IRF840

R26

10k

D10

1N4747

D16

1N5818

R29

D12

1N5819

D25

BYM26C

R46

200

IRF840

D27

1N5818

R30

D11

1N5819

D15

BYM26C

R24

200

2N2907

IEAO

I AC

I SENSE

RMS

RAMP 1

RAMP 2

DC I

LIMIT

VEAO

REF

CC2

PFC OUT

PWM 1

PWM 2

P GND

A GND

TC4427

C109

1nF

R11

�

C114

220pF

R112

471

R23

2.2k

MJE200

Q12

2N2222

100

�

Q10

2N2907

D14

1N4747

R33

10k

R45

20k

C13

820

�

R27

C10

10nF

�

R36

D26

1N5818

D13

20V

1nF

R28

330

C15

4.7

�

D21B

C17

470pF

R40

220

C18

470pF

R39

220

C104

1nF

R104

2.2k

R21

200

D105

1N5818

R20

200

D104

1N5818

�

1nF

R31

150

R16

500k

R17

500k

R103

100

2N2222

R34

2N2222

2N2907

C16

�

R14A

39k

R14B

39k

3300

�

R105

10k

C106

3.3nF

C105

100pF

C110

�

200:1

BR2

4x1N4148

C102

100nF

R19

453k

R18

453k

C103

2.2nF

R102

100k

C101

470nF

R101

10.2k

C108

680nF

R106

225k

C107

66nF

C116

470nF

1N4148

Q104

2N2222

R115

8.63k

C112

1nF

R114

52.3k

C113

150pF

R15

100m

FERRITE

BEAD

D17B

1N4747

C111

�

ML4826

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no
responsibility or liability for use of any application herein. The customer is urged to consult with appropriate
legal counsel before deciding on a particular application.

DS4826-01

2092 Concourse Drive

San Jose, CA 95131

Tel: 408/433-5200

Fax: 408/432-0295

PART NUMBER

PWM FREQUENCY

TEMPERATURE RANGE

PACKAGE

ML4826CP-1

1 x PFC

�

C to 70

�

20-Pin PDIP (P20)

(Obsolete)

ML4826CP-2

2 x PFC

�

C to 70

�

20-Pin PDIP (P20)

(EOL)

ML4826CS-1

1 x PFC

�

C to 70

�

20-Pin SOIC (S20)

(Obsolete)

ML4826CS-2

2 x PFC

�

C to 70

�

20-Pin SOIC (S20)

(EOL)

ML4826IP-1

1 x PFC

�40

�

C to 85

�

20-Pin PDIP (P20)

(Obsolete)

ML4826IP-2

2 x PFC

�40

�

C to 85

�

20-Pin PDIP (P20)

(Obsolete)

ML4826IS-1

1 x PFC

�40

�

C to 85

�

20-Pin SOIC (S20)

(Obsolete)

ML4826IS-2

2 x PFC

�40

�

C to 85

�

20-Pin SOIC (S20)

(Obsolete)

ORDERING INFORMATION

� Micro Linear 1997

is a registered trademark of Micro Linear Corporation

Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.

Электронный компонент: ML4826CP-2