May 1997

ML4841

Variable Feedforward PFC/PWM Controller Combo

GENERAL DESCRIPTION

The ML4841 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-2-3 specifications. The ML4841 includes
circuits for the implementation of a leading edge, average
current, "boost" type power factor correction, and a
trailing edge, pulse width modulator (PWM).

The PFC frequency of the ML4841 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the
optimum operating frequency for the PFC. An over-voltage
comparator shuts down the PFC section in the event of a
sudden decrease in load. The PFC section also includes
peak current limiting and input voltage brown-out
protection.

FEATURES

Internally synchronized PFC and PWM in one IC

Low total harmonic distortion

Reduced ripple current in the storage capacitor

between the PFC and PWM sections

Average current, continuous mode, boost type,

leading edge PFC

High efficiency trailing edge PWM can be configured

for current mode or voltage mode operation

Average line voltage compensation with brown-out

control

PFC overvoltage comparator eliminates output

"runaway" due to load removal

Current-fed multiplier for improved noise immunity

Overvoltage protection, UVLO, and soft start

BLOCK DIAGRAM

*Some Packages Are End Of Life Or Obsoete

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

RAMP 1

OSCILLATOR

OVP

PFC ILIMIT

UVLO

VREF

PULSE WIDTH MODULATOR

POWER FACTOR CORRECTOR

2.5V

7.5V

REFERENCE

VCC

VCCZ

VEA

IEA

PFC OUT

2.7V

-1V

RAMP 2

PWM OUT

VDC

RTCT

VCC

DUTY CYCLE

LIMIT

2.5V

VFB

VIN OK

GAIN

MODULATOR

VCCZ

÷2

3.5k

1.25V

50µA

13.5V

DC ILIMIT

ML4841

PIN CONFIGURATION

PIN DESCRIPTION

PIN

NAME

FUNCTION

RAMP 2

PWM ramp current sense input

GND

Ground

PWM OUT PWM driver output

PFC OUT

PFC driver output

Positive supply (connected to an
internal shunt regulator).

REF

Buffered output for the internal 7.5V
reference

PFC transconductance voltage error
amplifier input

VEAO

PFC transconductance voltage error
amplifier output

PIN

NAME

FUNCTION

IEAO

PFC transconductance current error
amplifier output

PFC gain control reference input

SENSE

Current sense input to the PFC current
limit comparator

RMS

Input for PFC RMS line voltage
compensation

Connection point for the PWM soft start
capacitor

PWM voltage feedback input

Connection for oscillator frequency
setting components

RAMP 1

PFC ramp input

IEAO

IAC

ISENSE

VRMS

VDC

RT/CT

RAMP 1

VEAO

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

RAMP 2

TOP VIEW

ML4841

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

ML4841

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Shunt Regulator Current .................................. 55mA

SENSE

Voltage .................................................... -3V to 5V

Voltage on Any Other Pin ...... GND - 0.3V to V

CCZ

+ 0.3V

REF ...........................................................................................

20mA

Input Current .................................................... 10mA

Peak PFC OUT Current, Source or Sink ................ 500mA
Peak PWM OUT Current, Source or Sink .............. 500mA
PFC OUT, PWM OUT Energy Per Cycle .................. 1.5mJ

Junction Temperature .............................................. 150

Storage Temperature Range ......................65

C to 150

Lead Temperature (Soldering, 10 sec) ..................... 260

Thermal Resistance (

)

Plastic DIP ....................................................... 80

C/W

Plastic SOIC ................................................... 105

C/W

OPERATING CONDITIONS

Temperature Range

ML4841CX ................................................ 0

C to 70

ML4841IX ............................................... -40

C to 85

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, I

= 25mA, R

= 23k

, R

RAMP1

= 28.7k

, C

= 400pF, C

RAMP1

= 270pF,

= Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VOLTAGE ERROR AMPLIFIER

Input Voltage Range

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

100

Feedback Reference Voltage

2.4

2.5

2.6

Input Bias Current

Note 2

-0.5

-1.0

Output High Voltage

6.0

6.7

Output Low Voltage

0.65

1.0

Source Current

0.5V, V

OUT

= 6V

-40

-90

Sink Current

0.5V, V

OUT

= 1.5V

Open Loop Gain

PSRR

CCZ

- 3V < V

< V

CCZ

- 0.5V

CURRENT ERROR AMPLIFIER

Input Voltage Range

-1.5

Transconductance

NON INV

= V

INV

, VEAO = 3.75V

130

195

310

Input Offset Voltage

Input Bias Current

-0.5

-1.0

Output High Voltage

6.0

6.7

Output Low Voltage

0.65

1.0

Source Current

0.5V, V

OUT

= 6V

-40

-90

Sink Current

0.5V, V

OUT

= 1.5V

Open Loop Gain

PSRR

CCZ

- 3V < V

< V

CCZ

- 0.5V

ML4841

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

OVP COMPARATOR

Threshold Voltage

2.6

2.7

2.8

Hysteresis

125

PFC I

LIMIT

COMPARATOR

Threshold Voltage

-0.8

-1.0

-1.15

(

PFC I

LIMIT

- Gain Modulator Output)

100

190

Delay to Output

150

300

DC I

LIMIT

COMPARATOR

Threshold Voltage

0.9

1.0

1.1

Input Bias Current

0.3

Delay to Output

150

300

OK COMPARATOR

Threshold Voltage

2.4

2.5

2.6

Hysteresis

0.8

1.0

1.2

GAIN MODULATOR

Gain (Note 3)

= 100

A, V

RMS

= V

= 0V

0.35

0.50

0.65

= 50

A, V

RMS

= 1.2V, V

= 0V

1.15

1.65

2.15

= 50

A, V

RMS

= 1.8V, V

= 0V

0.52

0.74

0.96

= 100

A, V

RMS

= 3.3V, V

= 0V

0.14

0.20

0.26

Bandwidth

IAC = 100

MHz

Output Voltage

= 250

A, V

RMS

= 1.15V,

0.74

0.82

0.90

= 0V

OSCILLATOR

Initial Accuracy

= 25ºC

188

200

212

kHz

Voltage Stability

CCZ

- 3V < V

< V

CCZ

- 0.5V

Temperature Stability

Total Variation

Line, Temp

182

218

kHz

Ramp Valley to Peak Voltage

2.5

Dead Time

PFC Only

260

400

Discharge Current

RAMP 2

= 0V, V

RAMP 1

= 2.5V

4.5

7.5

9.5

REFERENCE

Output Voltage

= 25ºC, I(V

REF

) = 1mA

7.4

7.5

7.6

Line Regulation

CCZ

- 3V < V

< V

CCZ

- 0.5V

Load Regulation

1mA < I(V

REF

) < 20mA

Temperature Stability

0.4

Total Variation

Line, Load, Temp

7.25

7.65

Long Term Stability

= 125ºC, 1000 Hours

ML4841

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PFC

Minimum Duty Cycle

IEAO

> 6.7V

Maximum Duty Cycle

IEAO

< 1.2V

Output Low Voltage

OUT

= -20mA

0.4

0.8

OUT

= -100mA

0.7

2.0

OUT

= 10mA, V

= 8V

0.8

1.5

Output High Voltage

OUT

= 20mA

10.5

OUT

= 100mA

9.5

Rise/Fall Time

= 1000pF

PWM

Duty Cycle Range

0-44

0-47

0-50

Output Low Voltage

OUT

= -20mA

0.4

0.8

OUT

= -100mA

0.7

2.0

OUT

= 10mA, V

= 8V

0.8

1.5

Output High Voltage

OUT

= 20mA

10.5

OUT

= 100mA

9.5

Rise/Fall Time

= 1000pF

SUPPLY

CCZ

Shunt Regulator Voltage

12.8

13.5

14.2

CCZ

Load Regulation

25mA < I

< 55mA

100

200

CCZ

Total Variation

Load, Temp

12.4

14.6

Start-up Current

= 11.2V, C

= 0

0.7

1.0

Operating Current

< V

CCZ

- 0.5V, C

= 0

Undervoltage Lockout Threshold

CCZ

- 1.0 V

CCZ

- 0.7 V

CCZ

- 0.4

Undervoltage Lockout Hysteresis

2.7

3.0

3.3

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

Note 2: Includes all bias currents to other circuits connected to the V

pin.

Note 3: Gain = K x 5.3V; K = (I

GAIN MOD

OFFSET

) x I

x (VEAO 1.5V)

ML4841

FUNCTIONAL DESCRIPTION

The ML4841 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM section uses current mode control. The
PWM stage uses conventional trailing-edge duty cycle
modulation, while the PFC uses leading-edge modulation.
This patented leading/trailing edge modulation technique
results in a higher useable PFC error amplifier bandwidth,
and can significantly reduce the size of the PFC DC buss
capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4841 runs at twice the frequency
of the PFC, which allows the use of smaller PWM output
magnetics and filter capacitors while holding down the
losses in the PFC stage power components.

In addition to power factor correction, a number of
protection features have been built into the ML4841. These
include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of a most
power supplies, which use a bridge rectifier and capacitive
input filter fed from the line. The peak-charging effect
which occurs on the input filter capacitor in such a supply
causes brief high-amplitude pulses of current to flow from
the power line, rather than a sinusoidal current in phase
with the line voltage. Such a supply presents a power
factor to the line of less than one (another way to state this
is that it causes significant current harmonics to appear at
its input). If the input current drawn by such a supply (or
any other non-linear load) can be made to follow the input
voltage in instantaneous amplitude, it will appear resistive
to the AC line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4841 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full wave
rectified AC line voltage. No filtering is applied following
the bridge rectifier, so the input voltage to the boost
converter ranges, at twice line frequency, from zero volts
to the peak value of the AC input and back to zero. By
forcing the boost converter to meet two simultaneous
conditions, it is possible to ensure that the current which
the converter draws from the power line agrees with the

instantaneous line voltage. One of these conditions is that
the output voltage of the boost converter must be set
higher than the peak value of the line voltage. A
commonly used value is 385VDC, to allow for a high line
of 270VAC. The other condition is that the current which
the converter is allowed to draw from the line at any given
instant must be proportional to the line voltage. The first
of these requirements is satisfied by establishing a suitable
voltage control loop for the converter, which in turn drives
a current error amplifier and switching output driver. The
second requirement is met by using the rectified AC line
voltage to modulate the output of the voltage control loop.
Such modulation causes the current error amplifier to
command a power stage current which varies directly
with the input voltage. In order to prevent ripple which
will necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level) from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

, which linearizes

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4841 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4841. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage

(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
I

. Sampling current in this way minimizes ground

noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.

2) A voltage proportional to the long-term rms AC line

voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at V

RMS

. The gain modulator's output

is inversely proportional to V

RMS2

(except at unusually

low values of V

RMS

where special gain contouring takes

over to limit power dissipation of the circuit
components under heavy brown-out conditions). The
relationship between V

RMS

and gain is designated as K,

and is illustrated in the Typical Performance
Characteristics.

ML4841

FUNCTIONAL DESCRIPTION

(Continued)

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

3) The output of the voltage error amplifier, VEAO. The

gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

VEAO

GAINMOD

RMS

More exactly, the output current of the gain modulator is
given by:

VEAO

GAINMOD

(

)

1 5

(1)

where K is in units of V

-1

Note that the output current of the gain modulator is
limited to

200

Current Error Amplifier

The current error amplifier's output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input to
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I

SENSE

(current into I

SENSE

/3.5k

). The negative voltage

on I

SENSE

represents the sum of all currents flowing in the

PFC circuit, and is typically derived from a current sense
resistor in series with the negative terminal of the input
bridge rectifier. In higher power applications, two current
transformers are sometimes used, one to monitor the I

the boost MOSFET(s) and one to monitor the I

of the

boost diode. As stated above, the inverting input of the
current error amplifier is a virtual ground. Given this fact,
and the arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from
the gain modulator will cause the output stage to increase
its duty cycle until the voltage on I

SENSE

is adequately

negative to cancel this increased current. Similarly, if the
gain modulator's output decreases, the output duty cycle
will decrease, to achieve a less negative voltage on the
I

SENSE

pin.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

VEAO

IEAO

VFB

IAC

VRMS

ISENSE

2.5V

VEA

IEA

VREF

PFC

OUTPUT

GAIN

MODULATOR

Cycle-By-Cycle Current Limiter

The I

SENSE

pin, as well as being a part of the current

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to V

. When the

voltage on V

exceeds 2.7V, the PFC output driver is shut

down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at V

drops below 2.58V.

The V

should be set at a level where the active and

passive external power components and the ML4841 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for

ML4841

FUNCTIONAL DESCRIPTION

(Continued)

the voltage and current error amplifiers, along with their
respective return points. The current loop compensation
is returned to V

REF

to produce a soft-start characteristic on

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier's
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4841's voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (V

) to deviate from its 2.5V (nominal)

value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This increases the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.

The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage
loop. It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.

Oscillator (R

)

The oscillator frequency is determined by the values of R

and C

, which determine the ramp and off-time of the

oscillator output clock:

OSC

RAMP

DISCHARGE

(2)

The ramp-charge time of the oscillator is derived from the
following equation:

V
V

RAMP

REF

-
-

1 25
3 75

.
.

(3)

at V

REF

= 7.5V:

RAMP

0 51

The discharge time of the oscillator may be determined
using:

DISCHARGE

2 5

5 1

490

(4)

The deadtime is so small (t

RAMP

>> t

DEADTIME

) that the

operating frequency can typically be approximated by:

OSC

RAMP

(5)

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

kHz

OSC

RAMP

200

RAMP

= ×

0 51

5 10

Solving for R

x C

yields 1 x 10

-5

. Selecting standard

components values, C

= 390pF, and R

= 24.9k

RAMP 1

The ramp voltage on this pin serves as a reference to
which the PFC's current error amp output is compared in
order to set the duty cycle of the PFC switch. The external
ramp voltage is derived from a RC network similar to the
oscillator's. The PWM's oscillator sends a synchronous
pulse every other cycle to reset this ramp.

The ramp voltage should be limited to no more than the
output high voltage (6V) of the current error amplifier. The
timing resistor value should be selected such that the
capacitor will not charge past this point before being reset.
In order to ensure the linearity of the PFC loop's transfer
function and improve noise immunity, the charging
resistor should be connected to the 13.5V V

rather than

the 7.5V reference. This will keep the charging voltage
across the timing cap in the "linear" region of the charging
curve.

The component value selection is similar to oscillator RC
component selection.

OSC

CHARGE

DISCHARGE

(6)

The charge time of Ramp 1 is derived from the following
equations:

CHARGE

OSC

(7)

Ramp Valley

Ramp Peak

CHARGE

(8)

ML4841

FUNCTIONAL DESCRIPTION

(Continued)

Figure 3. External Component Connections to V

At V

= 13.5V and assuming Ramp Peak = 5V to allow

for component tolerances:

CHARGE

0 463

(9)

The capacitor value should remain small to keep the
discharge energy and the resulting discharge current
through the part small. A good value to use is the same
value used in the PWM timing circuit (C

For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields R

1 10

0 463 390 10

56 2

( .

)(

)

(10)

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In
applications utilizing current mode control, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of
the output stage, and is thereby representative of the
current flowing in the converter's output stage. The DC
I

LIMIT

comparator provides cycle-by-cycle current limiting

and is connected to RAMP 2 internally. If the current sense
signal exceeds the 1V threshold, the PWM switch is
disabled until the protection flip-flop is rest by the clock
pulse at the start of the next PWM power cycle.

PWM Current Limit

The DC I

LIMIT

comparator is a cycle-by-cycle current

limiter for the PWM section. Should the input voltage at
this pin ever exceed 1V, the output of the PWM will be
disabled until the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle.

OK Comparator

The V

OK comparator monitors the DC output of the

PFC and inhibits the PWM if this voltage on V

is less

than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.

PWM Control (RAMP 2)

The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM's
output transformer, derived either by a current sensing
resistor or a current transformer.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50

A supplies

the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:

DELAY

1 25

(11)

where C

is the required soft start capacitance, and

DELAY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power
for the PWM section. The PWM start-up delay should be
at least 5ms.

Solving for the minimum value of C

1 25

200

ML4841

VCC

GND

VBIAS

10nF

ceramic

1µF

ceramic

ML4841

Generating V

The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with
a single resistor in series with the Vcc pin, returned to a
bias supply of typically 18V to 20V. The resistor's value
must be chosen to meet the operating current requirement
of the ML4841 itself (19mA max) plus the current required
by the two gate driver outputs.

EXAMPLE:
With a V

BIAS

of 20V, a V

limit of 14.6V (max) and

driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:

kHz

GATEDRIVE

(

)

(

)

100

200

(12)

BIAS

14 6

160

(13)

To check the maximum dissipation in the ML4841, check
the current at the minimum V

(12.4V):

12 4

160

47 5

(14)

The maximum allowable I

is 55mA, so this is an

acceptable design.

The ML4841 should be locally bypassed with a 10nF and
a 1

F ceramic capacitor. In most applications, an

electrolytic capacitor of between 100

F and 330

F is also

required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control technique is that
it requires only one system clock. Switch 1 (SW1) turns
off and switch 2 (SW2) turns on at the same instant to
minimize the momentary "no-load" period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC's output
ripple voltage can be reduced by as much as 30% using
this method.

Figure 4. Typical Trailing Edge Control Scheme

RAMP

VEAO

TIME

VSW1

TIME

REF

OSC

DFF

CLK

RAMP

CLK

SW2

SW1

VIN

FUNCTIONAL DESCRIPTION

(Continued)

ML4841

AC INPUT

85 TO 265VAC

680nF

ML4841

3.15A

300m

56.2k

BR1

4A, 600V

D12

1A, 50V

D13

1A, 50V

R2A

453k

R2B

453k

75k

13k

R1A

499k

R1B

499k

R12

27k

1nF

220pF

R11

750k

C19

1µF

470nF

R27

22k

C18

390pF

24.9k

R10

6.2k

C11

10nF

390pF

100nF

C30

330µF

R21

10nF

8A, 600V

100µF

R14

D10

1A, 20V

R7A

178k

R7B

178k

C12

10µF

50V

IRF840

IRF830

C13

100nF

C14

1µF

IEAO

IAC
ISENSE
VRMS
SS

VDC
RAMP 1

RAMP 2

VEAO

VFB

VREF

VCC

PFC OUT

PWM OUT

GND

DC ILIMIT

IRF830

R15

C20

1µF

R28

160

12VDC

3.1mH

33µH

C21

1800µF

C24

1µF

RTN

D11

MBR2545CT

600V

C25

100nF

R17

R30

4.7k

15V

R22

8.66k

R25

2.26k

R20

1.1

C15

10nF

C16

1µF

C31

1nF

2.37k

82nF

8.2nF

C17

220pF

R19

220

R23

1.5k

R24

1.2k

C22

4.7µF

TL431

R26

10k

C23

100nF

R18

220

Figure 6. 100W Power Factor Corrected Power Supply.

TYPICAL APPLICATIONS

Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the

general methods and topology suggested in Application
Note 33.

ML4841

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no
responsibility or liability for use of any application herein. The customer is urged to consult with appropriate
legal counsel before deciding on a particular application.

DS4841-01

2092 Concourse Drive

San Jose, CA 95131

Tel: 408/433-5200

Fax: 408/432-0295

is a registered trademark of Micro Linear Corporation.

Products described herein may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565761; 5,592,128; 5,594,376. Other patents are pending

PART NUMBER

TEMPERATURE RANGE

PACKAGE

ML4841CP

C to 70

16-Pin Plastic DIP (P16)

ML4841CS

C to 70

16-Pin Wide SOIC (S16W)

(EOL)

ML4841IP

-40

C to 85

16-Pin Plastic DIP (P16)

(OBS)

ML4841IS

-40

C to 85

16-Pin Wide SOIC (S16W)

(EOL)

ORDERING INFORMATION

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