ML4851
*
Low Current, Voltage Boost Regulator
BLOCK DIAGRAM
1
GENERAL DESCRIPTION
The ML4851 is a low power boost regulator designed for
DC to DC conversion in 1 to 3 cell battery powered
systems. The maximum switching frequency can exceed
100kHz, allowing the use of small, low cost inductors.
The combination of BiCMOS process technology, internal
synchronous rectification, variable frequency operation,
and low supply current make the ML4851 ideal for 1 cell
applications. The ML4851 is capable of start-up with input
voltages as low as 1V and is available in 5V and 3.3V
output versions with output voltage accuracy of 3%.
An integrated synchronous rectifier eliminates the need
for an external Schottky diode and provides a lower
forward voltage drop, resulting in higher conversion
efficiency. In addition, low quiescent battery current and
variable frequency operation result in high efficiency
even at light loads. The ML4851 requires only one
inductor and two capacitors to build a very small
regulator circuit capable of achieving conversion
efficiencies in excess of 90%.
The circuit also contains a RESET output which goes low
when the IC can no longer function due to low input
voltage, or when the DETECT input drops below 200mV.
*Some Packages Are Obsolete
FEATURES
n
Guaranteed full load start-up and operation at 1V input
n
Maximum switching frequency > 100kHz
n
Pulse Frequency Modulation (PFM) and internal
synchronous rectification for high efficiency
n
Minimum external components
n
Low ON resistance internal switching FETs
n
Micropower operation
n
5V and 3.3V output versions
FEATURING
Extended Commercial Temperature Range
-20C to 70C
for Portable Handheld Equipment
VREF
VOUT
VL
5
VIN
1
DETECT
4
PWR
GND
8
VREF
6
RESET
VREF
+
+
S
R
Q
Q
5s
ONE SHOT
START-UP
REFERENCE
2
GND
3
VREF
+
COMP
7
July, 2000
DATASHEET
2
ML4851
July, 2000
DATASHEET
PIN CONFIGURATION
PIN
NAME
FUNCTION
1
V
IN
Battery input voltage
2
V
REF
200mV reference output
3
GND
Analog signal ground
4
DETECT
Pulling this pin below V
REF
causes the
RESET pin to go low
PIN
NAME
FUNCTION
5
V
OUT
Boost regulator output
6
V
L
Boost inductor connection
7
RESET
Output goes low when regulation
cannot be achieved, or when DETECT
goes below V
REF
8
PWR GND
Return for the NMOS output transistor
PIN DESCRIPTION
ML4851
8-Pin SOIC (S08)
1
2
3
4
8
7
6
5
VIN
VREF
GND
DETECT
PWR GND
RESET
VL
VOUT
TOP VIEW
3
ML4851
July 2000
DATASHEET
OPERATING CONDITIONS
Temperature Range
ML4851CS-X .............................................. 0C to 70C
ML4851ES-X ........................................... 20C to 70C
V
IN
Operating Range
ML4851CS-X ................................ 1.0V to V
OUT
0.2V
ML4851ES-X ................................ 1.1V to V
OUT
0.2V
Thermal Resistance (
q
JA
) .................................... 160C/W
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
OUT
.......................................................................... 7V
Voltage on any other pin ..... GND 0.3V to V
OUT
+ 0.3V
Peak Switch Current, I
(PEAK) ...................................................
1A
Average Switch Current, I
(AVG) .....................................
250mA
Junction Temperature .............................................. 150C
Storage Temperature Range ...................... 65C to 150C
Lead Temperature (Soldering 10 sec.) ..................... 260C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
IN
= Operating Voltage Range, T
A
= Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
I
IN
V
IN
Current
V
IN
= V
OUT
0.2V
50
60
A
I
OUT(Q)
V
OUT
Quiescent Current
8
10
A
I
L
V
L
Quiescent Current
1
A
REFERENCE
V
REF
Output Voltage
0 < I
REF
< 5A
190
200
210
mV
PFM REGULATOR
t
ON
Pulse Width
4.5
5
5.5
s
OUTPUT VOLTAGE
V
OUT
Output Voltage
-3 Suffix
3.2
3.3
3.4
V
t
ON
= 0 at V
OUT(MAX)
,
4.5s
t
ON
5.5s
-5 Suffix
4.85
5.0
5.15
V
at V
OUT(MIN)
Load Regulation
See Figure 1, -3 Suffix
3.2
3.3
3.4
V
V
IN
= 1.2V, I
OUT
10mA
See Figure 1, -3 Suffix
3.2
3.3
3.4
V
V
IN
= 2.4V, I
OUT
65mA
See Figure 1, -5 Suffix
4.85
5.0
5.15
V
V
IN
= 1.2V, I
OUT
18mA
See Figure 1, -5 Suffix
4.85
5.0
5.15
V
V
IN
= 2.4V, I
OUT
85mA
Undervoltage Lockout Threshold
0.85
0.95
V
RESET COMPARATOR
DETECT Threshold
194
200
206
mV
DETECT Bias Current
100
100
nA
RESET Output High Voltage
I
OH
= 100A
V
OUT
0.2
V
RESET Output Low Voltage
I
OL
= -100A
0.2
V
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
4
ML4851
July, 2000
DATASHEET
VREF
VOUT
VOUT
+
VL
VIN
L1
Q1
Q2
5
6
+
+
S
R
Q
Q
5s
ONE SHOT
START-UP
A2
A1
R1
R2
C1
Figure 1. Application Test Circuit
Figure 2. PFM Regulator Block Diagram
Figure 3. PFM Inductor Current Waveforms and Timing
ML4851
I
OUT
100
F
1
F
100
F
V
IN
27
H
(Sumida CD75)
V
OUT
V
IN
V
REF
GND
DETECT
PWR GND
RESET
V
L
V
OUT
R
A
R
B
Q(ONE SHOT)
Q1 ON
Q1 ON
Q2
ON
Q2
ON
INDUCTOR
CURRENT
Q1 & Q2 OFF
5
ML4851
July 2000
DATASHEET
FUNCTIONAL DESCRIPTION
The ML4851 combines Pulse Frequency Modulation (PFM)
and synchronous rectification to create a boost converter
that is both highly efficient and simple to use. A PFM
regulator charges a single inductor for a fixed period of
time and then completely discharges before another cycle
begins, simplifying the design by eliminating the need for
conventional current limiting circuitry. Synchronous
rectification is accomplished by replacing an external
Schottky diode with an on-chip PMOS device, reducing
switching losses and external component count.
REGULATOR OPERATION
A block diagram of the boost converter is shown in Figure
2. The circuit remains idle when V
OUT
is at or above the
desired output voltage, drawing 50A from V
IN
, and 8A
from V
OUT
through the feedback resistors R1 and R2.
When V
OUT
drops below the desired output level, the
output of amplifier A1 goes high, signaling the regulator
to deliver charge to the output. Since the output of
amplifier A2 is normally high, the flip-flop captures the
A1 set signal and creates a pulse at the gate of the NMOS
transistor Q1. The NMOS transistor will charge the
inductor L1 for 5s, resulting in a peak current given by:
(1)
For reliable operation, L1 should be chosen so that I
L(PEAK)
does not exceed 1A.
When the one-shot times out, the NMOS transistor
releases the V
L
pin, allowing the inductor to fly-back and
momentarily charge the output through the body diode of
PMOS transistor Q2. But, as the voltage across the PMOS
transistor changes polarity, its gate will be driven low by
the current sense amplifier A2, causing Q2 to short out its
body diode. The inductor then discharges into the load
through Q2. The output of A2 also serves to reset the flip-
flop and one-shot in preparation for the next charging
cycle. A2 releases the gate of Q2 when its current falls to
zero. If V
OUT
is still low, the flip-flop will immediately
initiate another pulse. The output capacitor (C1) filters the
inductor current, limiting output voltage ripple. Inductor
current and one-shot waveforms are shown in Figure 3.
RESET COMPARATOR
An additional comparator is provided to detect low V
IN
,
or any other error condition that is important to the user.
The inverting input of the comparator is internally
connected to V
REF
, while the non-inverting input is
provided externally at the DETECT pin. The output of the
comparator is the RESET pin, which swings from V
OUT
to
GND when an error is detected. (Refer to Block Diagram)
DESIGN CONSIDERATIONS
INDUCTOR
Selecting the proper inductor for a specific application
usually involves a trade-off between efficiency and
maximum output current. Choosing too high a value will
keep the regulator from delivering the required output
current under worst case conditions. Choosing too low a
value causes efficiency to suffer. It is necessary to know
the maximum required output current and the input
voltage range to select the proper inductor value. The
maximum inductor value can be estimated using the
following formula:
(2)
where
h is the efficiency, typically between 0.8 and 0.9.
Note that this is the value of inductance that just barely
delivers the required output current under worst case
conditions. A lower value may be required to cover
inductor tolerance, the effect of lower peak inductor
currents caused by resistive losses, and minimum dead
time between pulses.
Another method of determining the appropriate inductor
value is to make an estimate based on the typical
performance curves given in Figures 4 and 5. Figure 4
shows maximum output current as a function of input
voltage for several inductor values. These are typical
performance curves and leave no margin for inductance
and ON-time variations. To accommodate worst case
conditions, it is necessary to derate these curves by at
least 10% in addition to inductor tolerance.
For example, a two cell to 5V application requires 60mA
of output current while using an inductor with 15%
tolerance. The output current should be derated by 25% to
80mA to cover the combined inductor and ON-time
tolerances. Assuming that 2V is the end of life voltage of
a two cell input, Figure 4 shows that with a 2V input, the
ML4851-5 delivers 80mA with an 18H inductor.
Figure 5 shows efficiency under the conditions used to
create Figure 4. It can be seen that efficiency is mostly
independent of input voltage and is closely related to
inductor value. This illustrates the need to keep the
inductor value as high as possible to attain peak system
efficiency. As the inductor value goes down to 10H, the
efficiency drops to around 75%. With 33H, the
efficiency exceeds 90% and there is little room for
improvement. At values greater than 33H, the operation
of the synchronous rectifier becomes unreliable at low
input voltages because the inductor current is so small
that it is difficult for the control circuitry to detect. The
data used to generate Figures 4 and 5 is provided in Table
1.
I
t
V
L
s V
L
L PEAK
ON
IN
IN
(
)
=
=
1
5
1
L
V
t
V
I
MAX
IN MIN
ON MIN
OUT
OUT MAX
=
(
)
(
)
(
)
2
2
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