October 1996
ML4961
Adjustable Output Low Voltage
Boost Regulator with Detect
1
GENERAL DESCRIPTION
The ML4961 is a boost regulator designed for DC to DC
conversion in 1 to 3 cell battery powered systems. The
combination of BiCMOS process technology, internal
synchronous rectification, variable frequency operation,
and low supply current make the ML4961 ideal for 1 cell
applications. The ML4961 is capable of start-up with input
voltages as low as 1V, and the output voltage can be set
anywhere between 2.5V and 6V by an external resistor
divider connected to the SENSE pin.
An integrated synchronous rectifier eliminates the need for
an external Schottky diode and provides a lower forward
voltage drop, resulting in higher conversion efficiency. In
addition, low quiescent battery current and variable
frequency operation result in high efficiency even at light
loads. The ML4961 requires a minimum number of
external components to build a very small adjustable
regulator circuit capable of achieving conversion
efficiencies in excess of 90%.
The circuit also contains a RESET output which goes low
when the IC can no longer function due to low input
voltage, or when the DETECT input drops below 200mV.
FEATURES
s
Guaranteed full load start-up and operation at 1V input
s
Pulse Frequency Modulation and Internal Synchronous
Rectification for high efficiency
s
Minimum external components
s
Low ON resistance internal switching FETs
s
Micropower operation
s
Adjustable output voltage (2.5V to 6V)
BLOCK DIAGRAM
+
+
5
8
2
1
4
6
L1
DETECT
SENSE
V
IN
GND
UVLO
RESET
V
L
C
OUT
+
V
OUT
PWR
GND
*R
B
*R
A
*OPTIONAL
TO MICROPROCESSOR
7
C
IN
*
R1
R2
C
FF
*
V
REF
3
BOOST
CONTROL
2
ML4961
PIN CONNECTION
PIN DESCRIPTION
PIN
NO.
NAME
FUNCTION
1
V
IN
Battery input voltage
2
GND
Analog signal ground
3
SENSE
Programming pin for setting the
output voltage
4
DETECT
Pulling this pin below V
REF
, causes
the RESET pin to go low
ML4961
8-Pin SOIC (S08)
PIN
NO.
NAME
FUNCTION
5
V
OUT
Boost regulator output
6
V
L
Boost inductor connection
7
RESET
Output goes low when regulation
cannot be achieved, or when DETECT
goes below 200mV
8
PWR GND Return for the NMOS output transistor
V
IN
GND
SENSE
DETECT
PWR GND
RESET
V
L
V
OUT
1
2
3
4
TOP VIEW
8
7
6
5
3
ML4961
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
IN
= Operating Voltage Range, T
A
= Operating Temperature Range (Note 1)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
Supply
V
IN
Current
V
IN
= V
OUT
0.2V
45
55
A
V
OUT
Quiescent Current
3
5
A
V
L
Quiescent Current
1
A
PFM Regulator
Pulse Width (T
ON
)
V
IN
= 2.4V
C/E Suffix
9
10
11
s
I Suffix
8.5
10
11.5
s
SENSE Comparator
194
200
206
mV
Threshold Voltage (V
SENSE
)
Load Regulation
See Figure 1
V
IN
= 1.2V, I
OUT
25mA
4.85
5.0
5.15
V
V
IN
= 2.4V, I
OUT
135mA
4.85
5.0
5.15
V
Undervoltage Lockout Threshold
C/E Suffix
0.85
0.95
V
I Suffix
0.95
1.05
V
RESET Comparator
DETECT Threshold
190
200
210
mV
DETECT Bias Current
100
100
nA
RESET Output High Voltage (V
OH
)
I
OH
= 100
A
V
OUT
0.2
V
RESET Output Low Voltage (V
OL
)
I
OL
= 100
A
0.2
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
OPERATING CONDITIONS
Temperature Range
ML4961CS ................................................. 0
C to 70
C
ML4961ES .............................................. 20
C to 70
C
ML4961IS ............................................... 40
C to 85
C
V
IN
Operating Range
ML4961CS ..................................... 1.0V to V
OUT
0.2V
ML4961ES, ML4961IS ....................1.1V to V
OUT
0.2V
V
OUT
Operating Range ................................. 2.5V to 6.0V
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Voltage on any pin ....................................................... 7V
Peak Switch Current, I
(PEAK)
......................................... 2A
Average Switch Current, I
(AVG)
.............................. 500mA
Junction Temperature .............................................. 150
C
Storage Temperature Range ...................... 65
C to 150
C
Lead Temperature (Soldering 10 sec.) ...................... 260
C
Thermal Resistance (
JA
) ..................................... 160
C/W
4
ML4961
Figure 1. PFM Regulator Block Diagram.
ML4961
I
OUT
100
F
100
F
V
IN
27
H
(Sumida CD75)
V
IN
GND
SENSE
DETECT
PWR GND
RESET
V
L
V
OUT
97.6K
0.1%
4.02K
0.1%
Figure 2. PFM Regulator Block Diagram.
+
VIN
10
s
ONE SHOT
START-UP
R
S
Q
VL
L1
Q2
A2
A1
VREF
Q1
5
+
VOUT
+
VOUT
6
C1
R1
R2
5
ML4961
FUNCTIONAL DESCRIPTION
The ML4961 combines Pulse Frequency Modulation
(PFM) and synchronous rectification to create a boost
converter that is both highly efficient and simple to use.
A PFM regulator charges a single inductor for a fixed
period of time and then completely discharges before
another cycle begins, simplifying the design by
eliminating the need for conventional current limiting
circuitry. Synchronous rectification is accomplished by
replacing an external Schottky diode with an on-chip
PMOS device, reducing switching losses and external
component count.
REGULATOR OPERATION
A block diagram of the boost converter is shown in Figure
2. The circuit remains idle when V
OUT
is at or above the
desired output voltage, drawing 45
A from V
IN
, and 8
A
from V
OUT
through the feedback resistors R1 and R2.
When V
OUT
drops below the desired output level, the
output of amplifier A1 goes high, signaling the regulator to
deliver charge to the output. Since the output of amplifier
A2 is normally high, the flip-flop captures the A1 set signal
and creates a pulse at the gate of the NMOS transistor Q1.
The NMOS transistor will charge the inductor L1 for 10
s,
resulting in a peak current given by:
I
T
V
L
s V
L
L PEAK
ON
IN
IN
(
)
=
1
10
1
(1)
For reliable operation, L1 should be chosen so that I
L(PEAK)
does not exceed 2A.
When the one-shot times out, the NMOS FET releases the
V
L
pin, allowing the inductor to fly-back and momentarily
charge the output through the body diode of PMOS
transistor Q2. But, as the voltage across the PMOS
transistor changes polarity, its gate will be driven low by
the current sense amplifier A2, causing Q2 to short out its
body diode. The inductor then discharges into the load
through Q2. The output of A2 also serves to reset the flip-
flop and one-shot in preparation for the next charging
cycle. A2 releases the gate of Q2 when its current falls to
zero. If V
OUT
is still low, the flip-flop will immediately
initiate another pulse. The output capacitor (C1) filters the
inductor current, limiting output voltage ripple. Inductor
current and one-shot waveforms are shown in Figure 3.
Q(ONE SHOT)
Q1 ON
Q1 ON
Q2
ON
Q2
ON
INDUCTOR
CURRENT
Q1 & Q2 OFF
Figure 3. PFM Inductor Current Waveforms and Timing.
RESET COMPARATOR
An additional comparator is provided to detect low V
IN
,
or any other error condition that is important to the user.
The inverting input of the comparator is internally
connected to V
REF
, while the non-inverting input is
provided externally at the DETECT pin. The output of the
comparator is the RESET pin, which swings from V
OUT
to
GND when an error is detected.
DESIGN CONSIDERATIONS
INDUCTOR
Selecting the proper inductor for a specific application
usually involves a trade-off between efficiency and
maximum output current. Choosing too high a value will
keep the regulator from delivering the required output
current under worst case conditions. Choosing too low a
value causes efficiency to suffer. It is necessary to know
the maximum required output current and the input
voltage range to select the proper inductor value. The
maximum inductor value can be estimated using the
following formula:
L
V
T
V
I
MAX
IN MIN
ON MIN
OUT
OUT MAX
=
(
)
(
)
(
)
2
2
(2)
where
is the efficiency, typically between 0.8 and 0.9.
Note that this is the value of inductance that just barely
delivers the required output current under worst case
conditions. A lower value may be required to cover
inductor tolerance, the effect of lower peak inductor
currents caused by resistive losses, and minimum dead
time between pulses.
Another method of determining the appropriate inductor
value is to make an estimate based on the typical
performance curves given in Figures 4 and 5. Figure 4
shows maximum output current as a function of input
voltage for several inductor values. These are typical
performance curves and leave no margin for inductance
and ON-time variations. To accommodate worst case
conditions, it is necessary to derate these curves by at
least 10% in addition to inductor tolerance. Interpolation
between the different curves will give a reasonable
starting point for an inductor value.
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