March 1997

ML6510

Series Programmable Adaptive

Clock Manager (PACManTM)

SYSTEM BLOCK DIAGRAM

GENERAL DESCRIPTION

The ML6510 (Super PACManTM) is a Programmable
Adaptive Clock Manager which offers an ideal solution for
managing high speed synchronous clock distribution in
next generation, high speed personal computer and
workstation system designs. It provides eight channels of
deskew buffers that adaptively compensate for clock skew
using only a single trace. The input clock can be either
TTL or PECL, selected by a bit in the control register.
Frequency multiplication or division is possible using the
M&N divider ratio, within the maximum frequency limit.
0.5X, 1X, 2X and 4X clocks can be easily realized.
The ML6510 is implemented using a low jitter PLL with
on-chip loop filter. The ML6510 deskew buffers adaptively
compensate for clock skew on PC boards. An internal
skew sense circuit is used to sense the skew caused by the
PCB trace and load delays. The sensing is done by
detecting a reflection from the load and the skew is
corrected adaptively via a unique phase control delay
circuit to provide low load-to-load skew, at the end of the
PCB traces. Additionally, the ML6510 supports PECL
reference clock outputs for use in the generation of clock
trees with minimal part-to-part skew. The chip configuration
can be programmed to generate the desired output
frequency using the internal ROM or an external serial
EEPROM or a standard two-wire serial microprocessor
interface.

*Some Packages Are Obsolete

FEATURES

Input clocks can be either TTL or PECL with low
input to output clock phase error

8 independent, automatically deskewed clock
outputs with up to 5ns of on-board deskew range
(10ns round trip)

Controlled edge rate TTL-compatible CMOS clock
outputs capable of driving 40

PCB traces

10 to 80MHz (6510-80) or 10 to 130MHz (6510-130)
input and output clock frequency range

Less than 500ps skew between inputs at the
device loads

Small-swing reference clock outputs for minimizing
part-to-part skew

Frequency multiplication or division is possible using
the M&N divider ratio

Lock output indicates PLL and deskew buffer lock

Test mode operation allows PLL and deskew buffer
bypass for board debug

Supports industry standard processors like Pentium,TM
Mips, SPARC,TM PowerPC,TM Alpha,TM etc.

CPU

CACHE

RAM

LOCAL BUS

MEMORY BUS

CACHE

CONTROLLER

MEMORY BUS

CONTROLLER

ML6510

CLK

CLOCK OUT TO
COMPONENTS

CLOCK SUBSYSTEM

CLOCK IN

ML6510

BLOCK DIAGRAM

CLK

INL

PLL

PHASE

DETECTOR

CLK0

(to remote chip)

FB0

(from remote chip)

CLK1

FB1

FB7

CLK7

ZERO DELAY

MAX DELAY

DESKEW BUFFER 0

DESKEW BUFFER 1

DESKEW BUFFER 7

MAXIMUM

DELAY

PROGRAMMING AND

CONTROL LOGIC

RESET

LOCK

R0MMSB

MCLK

OUT

MAX DELAY

ZERO DELAY

VOLTAGE

CONTROLLED

DELAY

DRIVE

CIRCUIT

SENSE

CIRCUIT

CLK

INH

REF

CLOCK

RCLKH RCLKL

FB6

DGND6

CLK6

DVCC67

CLK7

DGND7

FB7

ROMMSB

AVCC2

AGND2

CLK

INL

CLK3

DVCC23

CLK2

DGND2

FB2

FB1

DGND1

CLK1

DVCC01

CLK0

DGND0

19 20

DGND3

FB3

AGND1

AVCC1

FB4

DGND4

CLK4

DVCC45

CLK5

DGND5

FB5

FB0

OUT

MCLK

RESET

LOCK

AGND3

AVCC3

RCLKL

RCLKH

CLK

INH

ML6510

44-LEAD PLCC (Q44)

TOP VIEW

PIN CONNECTION

ML6510

PIN DESCRIPTION

PIN NUMBER

NAME

DESCRIPTION

ROMMSB

MSB of the internal ROM address. Tie to GND if not used. See section on
Programming the ML6510.

OUT

Programming pin. See section on Programming the ML6510.

MCLK

Programming pin. See section on Programming the ML6510.

RESET

Reset all internal circuits. Asserted polarity is low.

LOCK

Indicates when the PLL and deskew buffers have locked. Asserted polarity is
high.

CLK

INH

Input clock pins. For TTL clock reference use CLK

INH

CLK

INL

shorted to the CLK

INL

pin. For PECL clock reference drive pins differentially.

Input clock type is selected by the CS bit in the shift register.

16,14,9,7,

CLK[07]

Clock outputs

44, 42, 37, 35

18,12,11,5,

FB[07]

Clock feedback inputs for the deskew buffers

2, 40, 39, 33

3,31

AVCC[13]

Analog circuitry supply pins, separated from noisy digital supply pins to

provide isolation. All supplies are nominally +5V.

4, 30, 24

AGND[13]

Analog circuitry ground pins

DVCC01

Digital supply pin for CLK0 and CLK1 output buffers. Nominally +5V.

DVCC23

Digital supply pin for CLK2 and CLK3 output buffers. Nominally +5V.

DVCC45

Digital supply pin for CLK4 and CLK5 output buffers. Nominally +5V.

DVCC67

Digital supply pin for CLK6 and CLK7 output buffers. Nominally +5V.

17, 13, 10, 6,

DGND[07]

Digital ground pins for CLK [07] output buffers. Each clock output buffer has

1, 41, 38, 34

its own ground pin to avoid crosstalk and ground bounce problems.

RCLKL

Differential reference clock output used to minimize

RCLKH

part-to-part skew when building clock trees with other PACMan
integrated circuits.

ML6510

ABSOLUTE MAXIMUM RATINGS

VCC Supply Voltage Range ............................ 0.3V to 6V
Input Voltage Range .................................... 0.3V to VCC
Output Current

CLK[07] ........................................................ 70mA
All other outputs ............................................. 10mA

Junction Temperature .............................................. 150

Storage Temperature ................................ 65

C to 150

Thermal Resistance (

) ....................................... 54

C/W

ELECTRICAL CHARACTERISTICS

The following specifications apply over the recommended operating conditions of DVCC = AVCC = 5V

5% and ambient

temperature between 0

C and 70

C. Loading conditions are specified individually (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

DVCCXX Supply Current for each pair

CLKX

= 0

of clock outputs

= 20pF, Z

= 50

OUT

= 80MHz

IAVCC1

Static supply current, AVCC1 pin

100

120

IAVCC2

Static supply current, AVCC2 pin

IAVCC3

Static supply current, AVCC3 pin

LOW FREQUENCY INPUTS AND OUTPUTS (ROMMSB, MD

OUT

, MD

, MCLK, RESET, LOCK)

High level input voltage

DVCC

0.5

Low level input voltage

DGND + 0.5

High level output voltage,

= 100

DVCC 0.5

MCLK and MDIN

Low level output voltage,

= +200

DGND + 0.5

MCLK and MDIN

High level output voltage,

= 100

2.4

LOCK output

= 10

DVCC 0.5

Low level output voltage,

= +1 mA

0.4

LOCK output

Static input current

Input capacitance

HIGH FREQUENCY INPUTS AND OUTPUTS (CLK

INH

, CLK

INL

, FB[0-7], CLK[0-7])

High level input voltage

CS = 0 (TTL Input Clock)

2.0

CS = 1 (PECL Input Clock)

AVCC 1.165

AVCC 0.88

Low level input voltage

CS = 0 (TTL Input Clock)

0.8

CS = 1 (PECL Input Clock)

AVCC 1.810

AVCC 1.475

ICM

Common mode input voltage

CS = 1 (PECL Input Clock)

2.0

AVCC 0.4

range for PECL reference clocks

High level input current

= 2.4V

100

Low level input current

= 0.4V

400

High level output voltage

= 60mA

2.4

Low level output voltage

= +60mA

0.4

ML6510

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

AC CHARACTERISTICS rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).

Rise time, LOAD [0-7] output

0.8

2.0V, 80MHz

150

1500

Fall time, LOAD [0-7] output

2.0

0.8V, 80MHz

150

1500

Input frequency, CLK

MHz

OUT

Output frequency , CLK [0-7]

ML6510-80

MHz

output

ML6510-130 (Note 2)

130

MHz

VCO

PLL VCO operating frequency

160

MHz

Output duty cycle

Measured at device load, at 1.5V

JITTER

Output jitter

Cycle-to-cycle

Peak-to-peak

150

LOCK

PLL and deskew lock time

After programming is complete

SKEW CHARACTERISTICS All skew measurements are made at the load, at 1.5V threshold each output load can vary independently

within the specified range for a generic load (see Load Conditions section).

SKEWR

Output to output rising

500

edge skew, all clocks

SKEWF

Output to output

Output clock frequency

50MHz

1.5

falling edge skew

SKEWIO

CLK

input to any

N = M = 0

600

LOAD [0-7] output
rising edge skew

2, M

1.25

RANGE

Round trip delay CLKX to FBX

Output frequency < 50MHz

pin; output CLK period = t

CLK

Output frequency

50MHz

CLK

SKEWB

Output-to-output rising

Providing first (see LOAD

250

edge skew, between matched

conditions) order matching

loads

order matching between outputs

PART-TO-PART SKEW CHARACTERISTICS Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock

input pins of another ML6510.

PP1

Total load-to-load skew between

Slave chip CS = 1, CM = 1 and

multiple chips interfaced with

N = 0, M = 0; RCLK outputs to

reference clock pins.

CLK

inputs distance less than 2"

PP2

Total load-to-load skew between

Slave chip CS = 1, CM = 1 and

multiple chips interfaced with

2, M

2; RCLK outputs to

reference clock pins.

CLK

inputs distance less than 2"

PROGRAMMING TIMING CHARACTERISTICS

tRESET

RESET assertion pulse

width

AUX mode MCLK high time

2000

AUX mode MCLK low time

2000

AUX mode MD

OUT

data

hold time

AUX mode MD

OUT

data

setup time

AUX mode MCLK period

5000

ML6510

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

PROGRAMMING TIMING CHARACTERISTICS (continued)

MAIN mode MCLK high time

900

MAIN mode MCLK low time

900

MAIN mode MCLK period

1800

MAIN mode

900

MCLK to MD

OUT

valid

(EEPROM read time)

Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Note 2: If ML6510-130 is used in a master-slave mode, the maximum operating frequency is 120MHz.

ML6510 configured with bit CM = 0:

TTL INPUT CLOCK

LOAD [0-7]

1st Order Match

LOAD [0-7] with

no 1st order match

tSKEWF

tSKEWB

tSKEWIO

tSKEWR

PECL INPUT CLOCKS

CLK

INH

CLK

INL

ICM

AVCC 0.4V

2.0 V

Note:

All skew is measured at the device load input pin, NOT at the ML6510 clock output pin. Skew is always a positive number, regardless of which edge is leading and
which is trailing.

ML6510

LOAD[0-7]

LOAD[8-15]

pp1

or t

pp2

SKEWR

(or t

SKEWB

)

SKEWR

(or t

SKEWB

)

RCLKH

RCLKL

ML6510

CLK

INH

CLK

INL

ML6510

SLAVE CHIP

(CM=1, CS=1)

DISTANCE <2"

LOAD[0-7]

LOAD[8-15]

PCB trace impedance

= 50

Lumped

20pF

FBX

CLKX

ML6510-130

FIRST-ORDER

MATCHED LOADS

ML6510-130

GENERIC

LOAD

One way trip delay < t

RANGE

PCB trace impedance

= 50

Lumped

CLX

20pF

FBX

CLKX

LOAD

Length L

PCB trace impedance

= 50

Lumped

CLY

20pF

FBY

CLKY

LOAD

One way trip delay < t

RANGE

Length L

 C

| < 5pF

 L

| < 4"

= Z

PCB trace impedance

= 50

Lumped

20pF

FBX

CLKX

ML6510-80

FIRST-ORDER

MATCHED LOADS

ML6510-80

GENERIC

LOAD

One way trip delay < t

RANGE

PCB trace impedance

= 50

Lumped

CLX

20pF

FBX

CLKX

LOAD

Length L

PCB trace impedance

= 50

Lumped

CLY

20pF

FBY

CLKY

LOAD

One way trip delay < t

RANGE

Length L

 C

| < 5pF

 L

| < 4"

= Z

AC/SKEW CHARACTERISTICS LOAD CONDITIONS

ML6510

FUNCTIONAL DESCRIPTION

Micro Linear's ML6510 is the first clock chip to use a
feedback mechanism to adaptively (on a real time basis),
eliminate clock skew in high speed personal computer
and workstation system designs. Figure 1 shows a basic
configuration of the ML6510 in a system. The skew
problem results due to the delaying of clock signals in the
system, as shown in Figure 2. Clock skew results from
variation in factors like trace length, PCB trace
characteristics, load capacitance, parasitic capacitance,
temperature and supply variations, etc. Figure 2 shows a
representation of the clock skew problem from a timing
perspective. It shows a worst case example where the
clock signal is delayed so much that its rising edge
completely misses the data it is intended to strobe.
Using a clock deskew mechanism, this problem can be
eliminated and the strobe with the appropriate setup and
hold times with respect to the data bus can be generated.

The ML6510 has eight deskew buffers, each with its own
independent the reflection and error correction circuit.
The deskew buffer eliminates skew by using the reflection
from a remote chip to measure the clock error and then
corrects it by generating the appropriate skew to the clock
output to compensate.

Eight individually deskewed copies of the clock are
provided by the ML6510.

The deskew buffers compensate internally for board-level
skew caused by the PCB trace length variations and
device load variations. This is accomplished by sensing
the round trip delay via a reflected signal, and then
delaying or advancing the clock edge so that all 8 output
clocks arrive at their loads in phase. Each of the eight
clock lines can have any length PCB trace (up to 5ns each
way or 1/4th of the output clock period, whichever is
smaller) and the device loads can vary from line to line.
The ML6510 will automatically compensate for these
variations, keeping the device load clocks in phase.
Although ML6510 will compensate for skew caused by
loading, excessive capacitive loading can cause rise/fall
time degradation at the load. Cascading one ML6510 to
another ML6510 should be done using the PECL reference
clock outputs, to minimize part-to-part skew.

CLOCK REGENERATION

The programmable adaptive clock deskew can function in
a clock regeneration mode to assist in building clock trees
or to expand the number of deskewed clock lines. In this
mode, it has the ability to do clock multiplication or
division as well, while maintaining low skew between

WRITE

SIGNAL

CLOCK AT

REMOTE CHIP

DATA AT

REMOTE CHIP

WRITE

SIGNAL

CLOCK AT

REMOTE CHIP

DATA AT

REMOTE CHIP

DATA

Figure 2. The Skew Problem.

CPU

MICRO LINEAR

ML6510

CLOCK CHIP

REMOTE

CHIP

CLOCK #0

FEEDBACK #0

CLOCK #1

FEEDBACK #1

CLOCK #7

FEEDBACK #7

DATA

CLOCK

GENERATOR

CLOCK IN

Figure 1. Basic System Configuration Using the ML6510.

ML6510

PHASE

DETECTOR

(M + 1)

[

1 TO 64]

LOOP

FILTER

VCO

80-160 MHz

MAXIMUM

DELAY

CM BIT

(N + 1)

[

1 TO

128]

CLK

INH

CLK

INL

CS BIT

TTL TO ECL

SYS_CLK

TO DESKEW BUFFERS

ECL INPUT BUFFER

TEST

RCLKH
RCLKL

Example: Generating a 2x clock input frequency = 33 MHz

Set R = 01 (output range 40 80 MHz), N = 5 (0000101),
M = 2 (000010), M/S = 0

MHz

VCO

REF

( )

6 2

132

OUT

= f

VCO

= 132 MHz/2

= 66 MHz

Example: Generating a 1x clock Input frequency = 66 MHz

Set R = 01 (output range 4080 MHz), set M = 0
(000000), N = 0 (0000000), M/S = 0

MHz

VCO

× ×

1 2

132

OUT

= f

VCO

= 132 MHz/2

= 66 MHz

For doing frequency multiplication and division, keep
M

2 and N

2 for the lowest skew between input

clock and output clock. Several configurations for doing
frequency multiplication and division are included in the
8 configurations stored in the on-chip ROM (see
PROGRAMMING the ML6510).

Figure 3. ML6510 Clock Generation Block Diagram.

input clock and output clocks. It can thus generate a 2x or
4x or 0.5x frequency multiplication or division from input
to output (e.g. 33 MHz input, 66 MHz output or 66 MHz
input, 33 MHz output, etc.). It also can generate a 1x
frequency output. The VCO frequency is defined by:

VCO

REF

( )

and the output frequency is still given by:

OUT

= f

VCO

INPUT/OUTPUT RANGE

80-130 MHz

4080 MHz

2040 MHz

1020 MHz

Note: R implies R1, R0; for -80 version, Not valid: Defaults to R = 01

The VCO still must remain in the range 80160 MHz, and
the minimum phase detector input frequency is 625kHz =
(80 MHz/128). Thus the product of (N + 1) and 2

should

be limited to 128:

(N + 1) x 2

128

to make sure that the
phase detector inputs
remain above the minimum
frequency.

ML6510

ADAPTIVE DESKEW BUFFERS

Each copy of the clock is driven by an adaptive deskew
buffer. The deskew buffer compensates for skew time
automatically in accordance to the flight time delay it
senses from the reflection on the transmission line.

Figure 4 shows the simplified functional block diagram of
the deskew circuit. The phase of the sense signal and the
driver signal is presented to a three-input phase
comparator and compared with the reference signal. The
phase comparator then controls the voltage controlled
delay in the output drive line to match the delay of the
fixed reference delay line. Therefore, the sum of the delay
of the driver circuit, PCB trace delay, rise time delay at the
load and the adjustable delay will always equal the fixed
maximum delay.

The sense circuit has an internal level detect such that any
skew caused by loading is also accounted for. Since the
delay of the circuit is matched for the entire loop, the
phase of all the drivers are in close alignment at the inputs
of the load.

CLOCK IN

FIXED

MAX

DELAY

PHASE

DETECTOR

SENSE

DRIVE

VOLTAGE

CONTROLLED

DELAY

LOAD

Figure 4. Deskew Circuit Block Diagram.

LOAD CONDITIONS

The ML6510 has been designed to drive the wide range of
load conditions that are encountered in a high frequency
system. The eight output clock loads can each vary within a
range of trace length and lumped capacitive load, and the
ML6510 will maintain the low skew characteristics specified
in Electrical Characteristics. The clock skew can be further
minimized by providing some first-order matching
between any two loads that require particularly well-
matched clocks.

The ML6510-80 produces a 5V swing at the load and
requires a single external termination resistor for each
output. The ML6510-130 produces a 3V swing at the load
and requires two external termination resistors for each
output. The FB input pin is connected to the other side of
the termination resistor R1 or R2, with a short connection.
Termination resistor valves should be chosen as follows:

2 1 5

3 3

= ×

TRACE

RESISTOR

IMPEDANCE

VALUES

120

150

189

ML6510

PCB trace impedance

= 40

to 65

Lumped

20pF

FBX

CLKX

ML6510-130

FIRST-ORDER

MATCHED LOADS

ML6510-130

GENERIC

LOAD

One way trip delay < t

RANGE

PCB trace impedance

= 40

to 65

Lumped

CLX

20pF

FBX

CLKX

LOAD

Length L

PCB trace impedance

= 40

to 65

Lumped

CLY

20pF

FBY

CLKY

LOAD

One way trip delay < t

RANGE

Length L

 C

| < 5pF

 L

| < 4"

= Z

PCB trace impedance

= 40

to 65

Lumped

20pF

FBX

CLKX

ML6510-80

FIRST-ORDER

MATCHED LOADS

ML6510-80

GENERIC

LOAD

One way trip delay < t

RANGE

PCB trace impedance

= 40

to 65

Lumped

CLX

20pF

FBX

CLKX

LOAD

Length L

PCB trace impedance

= 40

to 65

Lumped

CLY

20pF

FBY

CLKY

LOAD

One way trip delay < t

RANGE

Length L

 C

| < 5pF

 L

| < 4"

= Z

EXTERNAL INPUT CLOCKS

The external input clock to the ML6510 can be either a
differential Pseudo-ECL clock or a single-ended TTL clock.
This is selected using the CS bit in the serial shift register.
For the single-ended TTL clock tie the CLK

INH

and CLK

INL

pins together. The ML6510 ensures that there is a well-
defined phase difference between the input and output
clocks.

RESET AND LOCK

When RESET is de-asserted, the internal programming
logic will become active, loading in the configuration bits
(see Programming the ML6510). Once the configuration is
loaded, the PLL will lock onto the reference signal, and
then the deskew blocks will adapt to the load conditions.
When all eight output clocks are stable and deskewed,
LOCK will be asserted. The asserted polarity of lock is
high. Thus, LOCK can be used to indicate that the system
is ready, or it can be used to drive the RESET input of
another PACMan in a clock tree.

CHIP
VCC

RESET

LOCK

tRESET

tLOCK

PROGRAM IN THE

CONFIGURATION

PROGRAM IN THE

CONFIGURATION

RESET may be reasserted at any time to reset the chip
operations. Following a RESET assertion of valid pulse
width (see Programming Electrical Characteristics), the
ML6510 must again be loaded with a configuration, then
it will re-lock and reassert lock when all eight clock
outputs are stable and deskewed.

ML6510

PROGRAMMING THE ML6510

The configuration of the ML6510 is programmed by
loading 18 (ML6510-80) or 19 (ML6510-130) bits into the
configuration shift register. To load these bits, the user has
3 options: MAIN, AUX or ROM modes. Which mode is
used is determined by the logic level on the MD

when RESET is deasserted. If MD

is tied high, the

ML6510 will assume AUX mode; if its tied low, ROM
mode. If MD

is high-impedance (i.e. tied to the input of

an EEPROM), it will assume MAIN mode.

1. MAIN Mode

In this mode, the ML6510 will read the configuration bits
from an external serial EEPROM, such as the 93C46, using
the industry standard 3-wire serial I/O protocol. The serial
EEPROM should be a 1K organized in 64 x 16 bits and the
PACMan will read the configuration bits out of the two least
significant 16-bit words. To use this mode, simply connect
the EEPROM serial data input pin to MD

(ML6510 pin 19),

the EEPROM serial data output pin to MD

OUT

(ML6510 pin

20), and the EEPROM serial data clock pin to MCLK
(ML6510 pin 21) and CS pin for the EEPROM should be tied
to the RESET signal. After power up, when RESET is
deasserted, the ML6510 will automatically generate the
address and clock to read out the configuration bits. Refer
MAIN Mode waveform in Figure 5.

1K SERIAL

EEPROM

(64 X 16 BIT)

ML6510

CLOCK

OPCODES

ADDRESS

DATA

CLK

DATA IN

DATA OUT

MCLK

OUT

RESET

ROMMSB

RESET

MAIN Mode Configuration.

2. AUX Mode

When MD

is tied to VCC, programming the ML6510

will occur via the AUX Mode. This mode shifts the
configuration bits into the shift register directly from the
MD

OUT

pin. The first 18 (ML6510-80) or 19 (ML6510-

130) clock rising edges provided externally on the MCLK
pin after RESET is deasserted will be used to load the shift
register data, which should be provided on the MD

OUT

pin. See figure 6.

PROCESSOR

ML6510

CLOCK

VCC

DATA

MCLK

OUT

ROMMSB

AUX Mode Configuration.

3. ROM Mode

When MD

is tied to GND, programming the ML6510

will occur via the ROM Mode. This mode reads the
configuration bits directly from an on chip ROM. The
selection of one of the eight preset configuration codes is
accomplished by means of the pins ROMMSB, MCLK and
MD

OUT

as shown in Tables 1 and 2. The TEST mode

configuration (code 7) is enabled when the TEST bit is set.
In this mode the PLL is bypassed for low frequency testing.
Codes 0-2 are used when the ML6510 clock inputs are
driven from another PACMan's reference clock outputs.
Code 3 is used when zero phase error is desired between
input and load clocks.

ROM

ADDRESS

BITS

ML6510

MCLK

OUT

ROMMSB

ROM

8 X 19 BIT

TO SHIFT REGISTER

SERIAL DATA IN

ROM Mode Configuration.

· · ·

MCLK

(Driven by

ML6510)

OP1

MDIN

(Driven by

ML6510)

OP0

MDOUT

(Driven by

EEPROM)

· · ·

D15

D14

D13

D15

D14

2 bits at address 1

16 bits data at adddress 0

(28)

(D13)

(3 bits for ML6510-130)

Figure 5. MAIN Mode Waveforms.

ML6510

TABLE 2: ML6510-130 ROM CODES

SELECTION BITS

INPUT OUTPUT

CONFIGURATION CODE

FREQ

CODE DESCRIPTION

ROMMSB

MCLK MD

OUT

(MHz)

CS CM R1, R0

DDSK

TEST

PECL Input Clock, 1x mode

80-130 80-130

PECL Input Clock, 0.5x mode

80-160

40-80

PECL Input Clock, 2x mode

40-65

80-130

PECL Input Clock, 1x mode

80-130 80-130

TTL Input Clock, 1x mode

80-130 80-130

TTL Input Clock, 0.5x mode

80-130

40-65

TTL Input Clock, 2x mode

40-65

80-130

TEST mode, TTL Input clock

0-50

TABLE 1: ML6510-80 ROM CODES

SELECTION BITS

INPUT

OUTPUT

CONFIGURATION CODE

FREQ

CODE DESCRIPTION

ROMMSB

MCLK MD

OUT

(MHz)

CM R1, R0

TEST

PECL Input Clock, 1x mode

40-80

PECL Input Clock, 0.5x mode

40-80

20-40

PECL Input Clock, 2x mode

20-40

40-80

PECL Input Clock, 1x mode

40-80

TTL Input Clock, 1x mode

40-80

TTL Input Clock, 0.5x mode

40-80

20-40

TTL Input Clock, 2x mode

20-40

40-80

TEST mode, TTL Input clock

0-50

Figure 6. AUX Mode Waveform.

MCLK
(Input to ML6510)

OUT

(Input to ML6510)

tA1

tA2

tA5

tA3

tA4

ML6510

REGISTER DEFINITIONS

REGISTER

SIZE

FUNCTION

7 bit

This register is used to define the ratio for the desired frequency of the primary clock.

2 bit

This register defines the frequency of the primary clocks, CLK [0-7].

1 bit

Set CM = 1 when the PECL input reference clock is from another 6510 reference clock output. Set

CM = 0 if the clock reference is TTL or PECL from an external source and minimum phase error
between input and output is desired.

1 bit

CS = 0 selects TTL input clock, CS = 1 selects PECL input clock.

TEST

1 bit

When set to 1, the PLL is bypassed for low frequency testing.

6 bit

This register is used to define the ratio for the desired frequency of the primary clock.

DDSK

1 bit

When DDSK is set to 1, deskew is disabled. The chip will provide low skew clocks at the chip output

pins, but trace length variations will not be compensated. When DDSK is set to 0, normal deskew will
provide low skew clocks at the loads. This bit is only for ML6510-130.

ML6510-80 SHIFT REGISTER CHAIN

MSB

LSB

MSB

LSB

TEST

MSB

LSB

SERIAL DATA IN
(from EEPROM,
or

Processor,

or internal ROM)

ML6510-130 SHIFT REGISTER CHAIN

MSB

LSB

MSB

LSB

TEST

MSB

LSB

SERIAL DATA IN
(from EEPROM,
or

Processor,

or internal ROM)

DDSK

ML6510

APPLICATIONS

ZERO SKEW CLOCK GENERATION

The most advantageous feature of using PACMan is its
ability to deliver multiple copies of the clock to the load
with very low skew. Because of its unique ability in
deskewing, trace length and load consideration are no
longer critical in board design.

Because of the unique deskewing scheme, neither the
trace length nor the device loads need to be equal. This is
true for loads, <20pF. Higher loads can be driven if they
are placed close to the clock chip, to guarantee signal
integrity.

CLOCK

DRIVER

ONE

DEVICE

LOAD

TWO

DEVICE

LOAD

THREE

DEVICE

LOAD

LOW SKEW CLOCK DISTRIBUTION

Clock distribution design is usually not a trivial task,
especially when multiple clock chips are needed. By
using closely grouped PACMans, 16 or more clock lines
can be created with low part-to-part skew. Additional
groups of clocks can be clustered and driven from
deskewed clock lines, to minimize the number of long-
distance clock lines.

CLK2

CLK0
CLK1

ML6510

CLK0
CLK1
CLK2

CLK2

CLK0
CLK1

ML6510

CLK3

· · ·

· ·

TO REMOTE GROUP

OF CLUSTERED LOADS

BOARD TO BOARD SYNCHRONIZATION

Distribution of the synchronous clock could present
significant difficulty at high frequency. With the system
clock generated by the ML6510, a zero skew clock
delivery to a backplane is now possible. By using the
ML6510 slave chip or the ML6510 in slave mode at the
receiver end, a near zero delay clock link can be
accomplished between the mother board and the satellite
boards.

Because the PACMan has frequency doubling capability, a
lower frequency signal can be used to route across a back
plane.

ML6510

(SLAVE MODE)

EXAMPLE CONFIGURATION

Shown in Figure 7 is an example configuration using
two ML6510-80 chips in tandem to generate eight 66
MHz clocks and eight 33MHz low-skew clocks from a
66MHz input reference. This requires only the termination
resistors. Configurations are loaded from the internal
ROM. PCB traces 0 to 15 are each 50

impedance and

the load capacitances C

-C

L15

are 0 to 20pF each. No

trace length matching is required among separate clock
outputs. All traces are shown with a series termination at
the output. If ML6510-130's are used in a master slave
mode the maximum operating frequency will be 120MHz.

LOAD[0-7]

LOAD[8-15]

33 MHz

SKEWR

(or t

SKEWB

)

pp2

SKEWR

(or t

SKEWB

)

ML6510

Figure 7. Example use of two ML6510-80 to generate multiple frequency clocks.

First ML6510-80 generates eight 66MHz clocks while second ML6510-80 takes 66MHz

small-swing reference from the first chip and generates eight 33MHz clocks.

LOAD0

CL0

66 MHz

CLK0

FB0

CLK1

FB1

CLK7

FB7

SYSTEM RESET LOW

RESET

ROMMSB

MCLK

MDIN

MDOUT

VCC

ML6510-80

TTL 1X

MODE

CLK

INH

CLK

INL

66MHz

TTL REFERENCE

LOCK

RCLKH

RCLKL

RESET

ROMMSB

MCLK

MDIN

MDOUT

LOCK

ALL_CLOCK_READY

ML6510-80

PECL 0.5X

MODE

CLK0

FB0

CLK1

FB1

CLK7

FB7

CLK

INH

CLK

INL

VCC

LOAD1

CL1

66 MHz

PCB TRACE 1

LOAD7

CL7

66 MHz

LOAD8

CL8

33 MHz

LOAD9

CL9

33 MHz

PCB TRACE 9

LOAD15

33 MHz

CL15

66MHz

PCB TRACE 15

PCB TRACE 8

PCB TRACE 7

PCB TRACE 0

ML6510

PHYSICAL DIMENSIONS

inches (millimeters)

0.100 - 0.112

(2.54 - 2.84)

PIN 1 ID

SEATING PLANE

0.685 - 0.695

(17.40 - 17.65)

0.650 - 0.656

(16.51 - 16.66)

0.013 - 0.021

(0.33 - 0.53)

0.165 - 0.180

(4.06 - 4.57)

0.650 - 0.656

(16.51 - 16.66)

0.685 - 0.695

(17.40 - 17.65)

0.590 - 0.630

(14.99 - 16.00)

0.025 - 0.045

(0.63 - 1.14)

(RADIUS)

0.050 BSC
(1.27 BSC)

0.009 - 0.011

(0.23 - 0.28)

0.042 - 0.056

(1.07 - 1.42)

0.042 - 0.048

(1.07 - 1.22)

0.026 - 0.032

(0.66 - 0.81)

0.500 BSC

(12.70 BSC)

Package: Q44

44-Pin PLCC

0.148 - 0.156

(3.76 - 3.96)

ML6510

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.

DS6510-01

2092 Concourse Drive

San Jose, CA 95131

Tel: 408/433-5200

Fax: 408/432-0295

ORDERING INFORMATION

PART NUMBER

TEMPERATURE RANGE

PACKAGE

ML6510CQ-80

C to 70

44-pin PLCC (Q44)

ML6510CQ-130

C to 70

44-pin PLCC (Q44)

(Obsolete)

is a registered trademark of Micro Linear Corporation

Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML6510

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML6510