Micro Linear
1
Micro Linear
March 1997
ML6622
*
High-Speed Data Quantizer
ECL OUT+
ECL OUT
ENABLE
LINK+
LINK
GND
V
CC
GNDA
V
CC
A
V
IN+
V
IN
V
REF
CAP
THIN
C
TIME
LINKLED
TIMER
LINK
OUT
THRESH
REF
FILTER
AMP
ECL
CMP
LINK DETECT
14
11
3
6
4
5
1
7
8
2
16
10
15
9
12
13
BLOCK DIAGRAM
FEATURES
s
200 MHz bandwidth
s
Low noise design
s
Adjustable Link Detect function
s
Low power design: 35mA typical
s
Used with the ML6633 LED driver
APPLICATIONS
s
FDDI
s
Fast Ethernet, 100BASE-FX
s
ATM (SONET), 155Mbps
s
Fibre Channel, 133 or 266Mbps
s
Proprietary high-speed fiber optic data links
GENERAL DESCRIPTION
The ML6622 high-speed data quantizer (post-amplifier) is
a low noise, wide-band, BiCMOS monolithic IC designed
for high-speed signal recovery applications, such as FDDI,
Fast Ethernet, and ATM. An internal DC restoration
feedback loop nulls any offset voltage produced in the
input stage. The limiting amplifier contributes to a high
level of sensitivity and a minimum of duty cycle
distortion.
The output of the data path is a high-speed comparator
with ECL outputs. An enable pin gates the comparator on
or off in response to the input signal level or a system
control signal.
The Link Detect circuit provides an Assert-Deassert
function with a user-selectable threshold voltage. This
circuit monitors the input signal and provides an ECL High
output within 100ms of signal acquisition and an ECL Low
output within 350ms of signal loss. The ECL discriminator
output can be used to disable the comparator when the
signal is below the user-selected threshold. LINKLED
drives an LED for a visible indication of the link status.
*Some Packages Are Obsolete
2
ML6622
Micro Linear
PIN DESCRIPTION
PIN#
NAME
FUNCTION
1
ENABLE
ECL input active low. When this input
is tied to LINKLED the ECL comparator
output is automatically enabled and
disabled by the Link Detect circuit.
This input can be tied to GND for
continuous enable. When the ECL
Comparator is disabled, ECL OUT
goes low and ECL OUT+ goes high.
2
LINKLED
Link Detect Status output. LINKLED is
an open collector active low signal. It
will be active low when the input
signal applied to V
IN+
,V
IN
exceeds
the programmed threshold level at the
THIN pin. Capable of driving a 20mA
LED indicator.
3
V
CC
Positive Power Supply. +5 volts
4 ECL OUT+
Positive and Negative ECL Comparator
5
ECL OUT
outputs. 1mA internal pull downs are
incorporated.
6
GND
Ground connection. Used for less
noise sensitive nodes.
7
LINK+
Positive ECL Link Detect output. Active
high when the input signal exceeds the
programmed Link Detect threshold.
1mA internal pull down current
sources.
8
LINK
Negative ECL Link Detect output.
Active low when the input signal
exceeds the programmed Link Detect
threshold. 1mA internal pull down
current sources.
9
V
REF
A 2.5V reference with respect to GND.
NAME PIN #
FUNCTION
10
THIN
Threshold Input. A voltage applied to
this input pin sets the minimum
amplitude of the input signal required
to cause the link detect to activate. In
most cases this can be tied to V
REF
.
11
GNDA
Ground connection for noise sensitive
circuits in the chip; the input amplifier,
DC restoration loop, part of the
Comparator and part of the link detect
circuit. In some system designs, it may
be advantageous to separate GND and
GNDA.
12
V
IN
This input pin should be capacitively
coupled to the input source or to V
CC
A.
13
V
IN+
This input pin should be capacitively
coupled to the input source or to V
CC
A.
14
V
CC
A
Positive power supply V
CC
for noise
sensitive circuits as mentioned in
GNDA. +5 volts.
15
CAP
A capacitor is tied from this pin to
V
REF
. This capacitor sets the lower
frequency rejection and helps remove
internal DC offset. This capacitor
should be 10 times larger than the
input capacitors.
16
C
TIMER
A capacitor from this pin to ground
determines the Link Detect response
time. To Meet FDDI specifications this
capacitor should be 2,000pF. This
capacitor can be removed for faster
response time.
ML6622
16-Pin Narrow SOIC (S16N)
PIN CONNECTION
TOP VIEW
ENABLE
LINKLED
V
CC
ECL OUT+
ECL OUT
GND
LINK+
LINK
CTIMER
CAP
V
CC
A
V
IN
+
V
IN
GNDA
THIN
V
REF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
3
ML6622
Micro Linear
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
V
CC
....................................................... GND 0.3V to 6V
V
CC
A ..................................................... GND 0.3V to 6V
Inputs/Outputs .......................... GND 0.3V to V
CC
+ 0.3
Junction Temperature ............................................. 150
C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= V
CC
= 5V
10%, T
A
= Operating Temperature Range. (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
V
CC
Supply Current
No load on ECL outputs
35
50
mA
V
REF
Reference Voltage
2.30
2.47
2.57
V
IV
REF
V
REF
Output Current
1
3
+5
mA
V
IN
Input Signal Range
3.5
1600
mV
P-P
V
TH
ADJ
External Voltage
0.5
V
REF
V
Range
at THIN to set V
TH
EN
Input-referred Voltage Noise
100 MHz BW
25
V
RMS
R
IN
Input Resistance
V
IN
+, V
IN
500
770
1500
I
THIN
Input Bias Current of THIN
100
+100
A
V
OL
-V
CC
ECL Output Voltage-Low
Through 50
to V
CC
2V
1.810
1.730
1.620
V
V
OH
-V
CC
ECL Output Voltage-High
Through 50
to V
CC
2V
C Suffix
1.025
0.963
0.800
V
I Suffix
1.025
0.963
0.780
V
t
r
Data Output Rise Time
0.5
1.3
ns
t
f
Data Output Fall Time
0.5
1.3
ns
Link Detect
AS_Max
Assert Time (off to on)
C
TIME
= 2000pF
0
100
s
ANS_Max Deassert Time (on to off)
C
TIME
= 2000pF
0
350
s
V
TH
Input threshold
THIN = V
REF
Assert
8
10
12
mV
Hysteresis
1.5
1.7
2
dB
BW
Bandwidth 1-3dB
200
MHz
VIPW
Minimum Input Pulse Width
5
ns
DCD
Duty Cycle Distortion
Data rate = 155Mb/s
Peak-to-peak
50% duty cycle input
0.5
ns
DDJ
Data Dependent Jitter
FDDI 56 Data Pattern
Peak-to-peak
V
IN
= 60mV, Data rate = 125Mb/s
1.2
ns
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case conditions.
Storage Temperature Range ...................... 65
C to 150
C
Lead Temperature (Soldering 10 sec.) ...................... 260
C
Thermal Resistance ........................................... 100
C/W
4
ML6622
Micro Linear
FUNCTIONAL DESCRIPTION
The ML6622 high speed data quantizer accepts a low
level analog signal from a pin diode and transimpedance
amp front end and converts it into digital ECL levels for
subsequent digital processing. The input signal, from a
transimpedance amplifier, is immediately amplified by a
two-stage video amplifier. The output of this amplifier
feeds two parallel paths.
The data path is comprised of a high speed comparator
that outputs PECL differential data on the ECL OUT
pins.
The Link Detection path monitors the magnitude of the
amplified input signal, compares it to a user-settable
threshold, and provides the result of the comparison as a
PECL differential output on the Link
pins. The timer
following the threshold block is used to set the Link
Detect output acquire and deacquire time using a
capacitor.
AMPLIFIER
The amplifier is a two stage video amplifier with a gain of
approximately 55V/V. Maximum sensitivity is achieved
through the use of the DC restoration feedback loop and
AC coupling the input. The AC coupling input capacitors,
in conjunction with the input impedance of the amplifier,
establish a high pass filter with the lower 3dB point
determined by the input resistance and the input coupling
capacitors. This cap also adds a secondary pole to the
offset loop.
Since the amplifier has a differential input, two AC
capacitors of equal value are required. If the signal driving
the input is single ended, the other coupling capacitor
should be tied to V
CC
.
A low-pass filter in the offset loop is created with the
capacitor on pin 15 (CAP). The lower 3dB point
controlled by a capacitor tied from the CAP pin to V
REF
as
shown in the application circuit. For stability reasons the
value of the capacitor on the CAP pin should be 10 times
larger than the input coupling capacitors. The 3dB point is
given by the following equation:
F
C
3
1
2
100
dB
k
=
Although the input is AC coupled, the offset voltage
within the amplifier will be present at the amplifier's
output. The removal of the dc offset in the amplifier helps
the circuit respond to small input voltages, and reduces
duty-cycle distortion. In order to reduce this error, a
negative feedback loop nulls the offset voltage. An
external capacitor connected to the CAP pin is used to
store the offset voltage. This voltage is compared to V
REF
and a difference current proportional to the result is
applied to the negative side of the input stage of the AMP
circuit block thereby nulling the DC offset.
COMPARATOR
A high speed ECL comparator with PECL outputs is used
for the quantization function. The comparator has an
Enable input pin which takes an ECL level. This Enable
pin is normally driven by LINKLED, which causes the
output to be enabled when the link is up and disabled
when the link is down. When ENABLE is low the
comparator is operational. When ENABLE is high the
comparator is disabled causing ECL OUT to go low and
ECL OUT+ to go high. The ENABLE pin can be tied to
ground to keep the comparator permanently enabled.
LINK DETECT CIRCUIT
The Link Detection Circuit is used to accurately measure
the input amplitude to determine whether it is large
enough to reliably recover the input signal. Once the Bit
Error Rate (BER) for the ML6622 receive circuit is
determined, the link detect threshold can be set so that the
Link Detect Circuit will shut off before the error rate
exceeds the link requirement.
The Link Detection Circuit consists of three functional
blocks; Thresh, Timer, and Link Out. Thresh detects the
output of Amp and compares it to a programmable
threshold input THIN. As long as the input amptitude is
greater than the programmable threshold input, the Link
Detect output remains active.
When the peak input drops below THIN, Thresh's output
changes state and Timer delays the Link Out state change
for a programmable amount of time. When using the
default C
TIME
capacitance of 2000pF, the deassert time
and the assert time values conform to the ANSI X3.166-
1990 PMD standard for FDDI.
To improve stability, the Link Detect circuit includes 1.7dB
of hysteresis.
The V
REF
output can be tied directly to THIN to set the
Link Detect threshold. For greater sensitivities, V
REF
can
be divided down before applied to THIN. The formula for
the threshold on the thin pin is as follows:
Threshold Assert
V
THIN
(
)
=
500
Threshold Deassert
V
THIN
(
)
=
750
5
ML6622
Micro Linear
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+5V
OPTIONAL
470
0.01F
0.01F
C
TIMER
CAP
V
CC
A
V
IN+
V
IN
GNDA
THIN
V
REF
ENABLE
LINKLED
V
CC
ECL OUT+
ECL OUT
GND
LINK+
LINK
+5V
1K
1K
1K
1K
4.7H
4.7H
.1
+4.7
+4.7
.1
+5V
V
RF+
V
RF
OPTIONAL
V
RF
V
RF+
V
RF
V
RF+
0.1F
APPLICATION CIRCUIT
6
ML6622
Micro Linear
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML6622CS
0
to 70
C
16-Pin Narrow SOIC (S16N)
ML6622IS
40
to 85
C
16-Pin Narrow SOIC (S16N)
(Obsolete)
DS6622-01
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
PHYSICAL DIMENSIONS
inches (millimeters)
SEATING PLANE
0.148 - 0.158
(3.76 - 4.01)
PIN 1 ID
0.228 - 0.244
(5.79 - 6.20)
0.386 - 0.396
(9.80 - 10.06)
0.012 - 0.020
(0.30 - 0.51)
0.050 BSC
(1.27 BSC)
0.015 - 0.035
(0.38 - 0.89)
0.059 - 0.069
(1.49 - 1.75)
0.004 - 0.010
(0.10 - 0.26)
0.055 - 0.061
(1.40 - 1.55)
16
0.006 - 0.010
(0.15 - 0.26)
0 - 8
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
Package: S16N
16-Pin Narrow SOIC
Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
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