2003 Microchip Technology Inc.
Preliminary
DS21673C-page 1
24AA515/24LC515/24FC515
Device Selection Table
Features
Low-power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400
A at 5.5V
- Standby current 100 nA typical at 5.5V
2-wire serial interface bus, I
2
C
TM
compatible
Cascadable for up to four devices
Self-timed ERASE/WRITE cycle
64-byte Page Write mode available
5 ms max write cycle time
Hardware write-protect for entire array
Output slope control to eliminate ground bounce
Schmitt Trigger inputs for noise suppression
100,000 erase/write cycles
Electrostatic discharge protection > 4000V
Data retention > 200 years
8-pin PDIP, SOIC packages
Temperature ranges:
Description
The Microchip Technology Inc. 24AA515/24LC515/
24FC515 (24XX515*) is a 64K x 8 (512K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device has both byte write and page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads. Reads may be
sequential within address boundaries 0000h to 7FFFh
& 8000h to FFFFh. Functional address lines allow up to
four devices on the same data bus. This allows for up
to 2 Mbits total system EEPROM memory. This device
is available in the standard 8-pin plastic DIP and SOIC
packages.
Package Type
Block Diagram
Part
Number
V
CC
Range
Max Clock
Frequency
Temp
Ranges
24AA515
1.8-5.5V
400 kHz
I
24LC515
2.5-5.5V
400 kHz
I
24FC515
2.5-5.5V
1 MHz
I
100 kHz for V
CC
< 2.5V.
- Industrial (I):
-40
C to
+85
C
A0
A1
A2
V
SS
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
2
4
AA5
1
5
/
PDIP
SOIC
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24A
A
5
15/
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1
SDA
SCL
V
CC
V
SS
WP
512K I
2
C
TM
CMOS Serial EEPROM
24XX515 is used in this document as a generic part number
for the 24AA515/24LC515/24FC515 devices.
24AA515/24LC515/24FC515
DS21673C-page 2
Preliminary
2003 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
()
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-65C to +125C
ESD protection on all pins
......................................................................................................................................................
4 kV
TABLE 1-1:
DC CHARACTERISTICS
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC CHARACTERISTICS
Industrial (I): V
CC
= +1.8V to 5.5V T
A
= -40C to +85C
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
D1
A0, A1, SCL, SDA, and
WP pins:
D2
V
IH
High-level input voltage
0.7 V
CC
--
V
V
CC
2.5V
D3
V
IL
Low-level input voltage
--
0.3 V
CC
0.2 V
CC
V
V
V
CC
2.5V
V
CC
< 2.5V
D4
V
HYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 V
CC
--
V
V
CC
2.5V (Note)
D5
V
OL
Low-level output voltage
--
0.40
V
I
OL
= 3.0 mA @ V
CC
= 4.5V
I
OL
= 2.1 mA @ V
CC
= 2.5V
D6
I
LI
Input leakage current
--
1
A
V
IN
= V
SS
or V
CC
, WP = V
SS
V
IN
= V
SS
or V
CC
, WP = V
CC
D7
I
LO
Output leakage current
--
1
A
V
OUT
= V
SS
or V
CC
D8
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
--
10
pF
V
CC
= 5.0V (Note)
T
A
= 25C, f
C
= 1 MHz
D9
I
CC
Read Operating current
--
400
A
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Write
--
3
mA
V
CC
= 5.5V
D10
Iccs
Standby current
--
5
A SCL = SDA = V
CC
= 5.5V
A0, A1, WP = V
SS
, A2 = V
CC
Note:
This parameter is periodically sampled and not 100% tested.
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 3
24AA515/24LC515/24FC515
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
V
CC
= +1.8V to 5.5V
T
A
= -40C to +85C
Param.
No.
Sym
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock frequency
--
--
--
100
400
1000
kHz
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
2
T
HIGH
Clock high time
4000
600
500
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
3
T
LOW
Clock low time
4700
1300
500
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
4
T
R
SDA and SCL rise time
(Note 1)
--
--
--
1000
300
300
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
5
T
F
SDA and SCL fall time
(Note 1)
--
--
300
100
ns
All except, 24FC515
2.5V
V
CC
5.5V (24FC515 only)
6
T
HD
:
STA
Start condition hold time
4000
600
250
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
7
T
SU
:
STA
Start condition setup time
4700
600
250
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
8
T
HD
:
DAT
Data input hold time
0
--
ns
(Note 2)
9
T
SU
:
DAT
Data input setup time
250
100
100
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
10
T
SU
:
STO
Stop condition setup time
4000
600
250
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
11
T
SU
:
WP
WP setup time
4000
600
600
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
12
T
HD
:
WP
WP hold time
4700
1300
1300
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
13
T
AA
Output valid from clock
(Note 2)
--
--
--
3500
900
400
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
500
--
--
--
ns
1.8V
V
CC
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V (24FC515 only)
15
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
10 + 0.1C
B
250
250
ns
All except, 24FC515 (Note 1)
24FC515 (Note 1)
16
T
SP
Input filter spike suppression
(SDA and SCL pins)
--
50
ns
All except, 24FC515 (Notes 1 and 3)
17
T
WC
Write cycle time (byte or page)
--
5
ms
18
Endurance
1 M
--
cycles
25C, V
CC
= 5.0V, Block mode (Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total EnduranceTM Model which can be obtained from Microchip's web site @www.microchip.com.
24AA515/24LC515/24FC515
DS21673C-page 4
Preliminary
2003 Microchip Technology Inc.
FIGURE 1-1:
BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
8
9
13
D4
4
10
11
12
14
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 5
24AA515/24LC515/24FC515
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. If left
unconnected, these inputs will be pulled down
internally to V
SS
.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5
Write-Protect (WP)
This pin can be connected to either V
SS
, V
CC
or left
floating. An internal pull-down resistor on this pin will
keep this device in the unprotected state if left floating.
If tied to V
SS
or left floating, normal memory operation
is enabled (read/write the entire memory 0000h-
FFFFh).
If tied to V
CC
, write operations are inhibited. Read
operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name PDIP SOIC
Function
A0
1
1
User Configurable Chip Select
A1
2
2
User Configurable Chip Select
A2
3
3
Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (V
CC
). Device
will not operate with this pin
left floating or held to logical 0
(V
SS
).
V
SS
4
4
Ground
SDA
5
5
Serial Data
SCL
6
6
Serial Clock
WP
7
7
Write-Protect Input
V
CC
8
8
+1.8 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+4.5 to 5.5V (24FC515)
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