2004 Microchip Technology Inc.

DS21908A-page 1

MCP6S91/2/3

Features

· Multiplexed Inputs: 1 or 2 channels

· 8 Gain Selections:

- +1, +2, +4, +5, +8, +10, +16 or +32 V/V

· Serial Peripheral Interface (SPI

)

· Rail-to-Rail Input and Output

· Low Gain Error: ±1% (max.)

· Offset Mismatch Between Channels: 0 µV

· High Bandwidth: 1 to 18 MHz (typ.)

· Low Noise: 10 nV/

Hz @ 10 kHz (typ.)

· Low Supply Current: 1.0 mA (typ.)

· Single Supply: 2.5V to 5.5V

· Extended Temperature Range: -40°C to +125°C

Typical Applications

· A/D Converter Driver

· Multiplexed Analog Applications

· Data Acquisition

· Industrial Instrumentation

· Test Equipment

· Medical Instrumentation

Block Diagram

Description

The Microchip Technology Inc. MCP6S91/2/3 are
analog Programmable Gain Amplifiers (PGAs). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to two chan-
nels through a SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high-speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single-
supply applications needing flexible performance or
multiple inputs.

The one-channel MCP6S91 and the two-channel
MCP6S92 are available in 8-pin PDIP, SOIC and MSOP
packages. The two-channel MCP6S93 is available in a
10-pin MSOP package. All parts are fully specified from
-40°C to +125°C.

Package Types

OUT

REF

SCK

CH1

CH0

MUX

SPITM

Logic

Gain

Switches

sto
r
La
dde

r (R

LA
D

)

REF

CH0

SCK

OUT

MCP6S91

PDIP, SOIC, MSOP

CH1

CH0

SCK

OUT

MCP6S92

PDIP, SOIC, MSOP

CH0

OUT

CH1

7 SI

SCK

REF

MCP6S93

MSOP

Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

2004 Microchip Technology Inc.

DS21908A-page 2

MCP6S91/2/3

1.0

ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings

........................................................................7.0V

All inputs and outputs..................... V

0.3V to V

+ 0.3V

Difference Input voltage ....................................... |V

Output Short Circuit Current ..................................continuous

Current at Input Pin

.............................................................±

2 mA

Current at Output and Supply Pins

................................ ±

30 mA

Storage temperature .....................................-65°C to +150°C

Junction temperature .................................................. +150°C

ESD protection on all pins (HBM; MM)

................

4 kV; 200V

Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.

PIN FUNCTION TABLE

Name

Function

OUT

Analog Output

CH0, CH1 Analog Inputs

REF

External Reference Pin

Negative Power Supply

SPI Chip Select

SPI Serial Data Input

SPI Serial Data Output

SCK

SPI Clock Input

Positive Power Supply

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Amplifier Inputs (CH0, CH1)

Input Offset Voltage

-4

G = +1

Input Offset Voltage Mismatch

µV

Between inputs (CH0, CH1)

Input Offset Voltage Drift

±1.8

µV/°C

= -40°C to +125°C

Power Supply Rejection Ratio

PSRR

G = +1 (Note 1)

Input Bias Current

±1

CHx = V

Input Bias Current at
Temperature

CHx = V

/2, T

= +85°C

600

CHx = V

/2, T

= +125°C

Input Impedance

||7

||pF

Input Voltage Range

IVR

0.3

+ 0.3

(Note 2)

Reference Input (V

REF

)

Input Impedance

IN_REF

(5/G)||6

||pF

Voltage Range

IVR_REF

(Note 2)

Amplifier Gain

Nominal Gains

1 to 32

V/V

+1, +2, +4, +5, +8, +10, +16 or +32

DC Gain Error

G = +1

-0.2

+0.2

OUT

0.3V to V

0.3V

-1.0

+1.0

OUT

0.3V to V

0.3V

DC Gain Drift

G = +1

±0.0002

%/°C

= -40°C to +125°C

±0.0004

%/°C

= -40°C to +125°C

Note

LAD

in Figure 4-1) connects V

REF

, V

OUT

and the inverting input of the internal amplifier. The MCP6S92 has

REF

tied internally to V

, so V

is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is

recommended that the MCP6S92's V

pin be tied directly to ground to avoid noise problems.

The MCP6S92's V

IVR

and V

IVR_REF

are not tested in production; they are set by design and characterization.

includes current in R

LAD

(typically 60 µA at V

OUT

= 0.3V). Both I

and I

Q_SHDN

exclude digital switching currents.

2004 Microchip Technology Inc.

DS21908A-page 3

MCP6S91/2/3

Ladder Resistance

Ladder Resistance

LAD

3.4

4.9

6.4

(Note 1)

Ladder Resistance across
Temperature

LAD

+0.028

%/°C

= -40°C to +125°C (Note 1)

Amplifier Output

DC Output Non-linearity G = +1

ONL

±0.18

% of FSR V

OUT

0.3V to V

0.3V, V

= 5.0V

ONL

±0.050

% of FSR V

OUT

0.3V to V

0.3V, V

= 5.0V

Maximum Output Voltage Swing

OH_ANA

OL_ANA

+ 20

100

+2; 0.5V output overdrive

+ 60

+2; 0.5V output overdrive,

REF

= V

Short Circuit Current

±25

Power Supply

Supply Voltage

2.5

5.5

Minimum Valid Supply Voltage

DD_VAL

0.4

2.0

Quiescent Current

0.4

1.0

1.6

= 0 (Note 3)

Quiescent Current, Shutdown
Mode

Q_SHDN

= 0 (Note 3)

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note

LAD

in Figure 4-1) connects V

REF

, V

OUT

and the inverting input of the internal amplifier. The MCP6S92 has

REF

tied internally to V

, so V

is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is

recommended that the MCP6S92's V

pin be tied directly to ground to avoid noise problems.

The MCP6S92's V

IVR

and V

IVR_REF

are not tested in production; they are set by design and characterization.

includes current in R

LAD

(typically 60 µA at V

OUT

= 0.3V). Both I

and I

Q_SHDN

exclude digital switching currents.

2004 Microchip Technology Inc.

DS21908A-page 4

MCP6S91/2/3

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2, C

= 60 pF, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Frequency Response

-3 dB Bandwidth

1 to 18

MHz

All gains; V

OUT

< 100 mV

P-P

(Note 1)

Gain Peaking

GPK

All gains; V

OUT

< 100 mV

P-P

Total Harmonic Distortion plus Noise

f = 20 kHz, G = +1 V/V

THD+N

0.0011

OUT

= 1.5V ± 1.0 V

, V

= 5.0V,

BW = 80 kHz, R

= 10 k

to 1.5V

f = 20 kHz, G = +1 V/V

THD+N

0.0089

OUT

= 2.5V ± 1.0 V

, V

= 5.0V,

BW = 80 kHz

f = 20 kHz, G = +4 V/V

THD+N

0.0045

OUT

= 2.5V ± 1.0 V

, V

= 5.0V,

BW = 80 kHz

f = 20 kHz, G = +16 V/V

THD+N

0.028

OUT

= 2.5V ± 1.0 V

, V

= 5.0V,

BW = 80 kHz

Step Response

Slew Rate

4.0

V/µs

G = 1, 2

V/µs

G = 4, 5, 8, 10

V/µs

G = 16, 32

Noise

Input Noise Voltage

4.5

µV

P-P

f = 0.1 Hz to 10 Hz (Note 2)

f = 0.1 Hz to 200 kHz (Note 2)

Input Noise Voltage Density

nV/

Hz f = 10 kHz (Note 2)

Input Noise Current Density

fA/

f = 10 kHz

Note

See Table 4-1 for a list of typical numbers and Figure 2-25 for the frequency response versus gain.

and e

include ladder resistance noise. See Figure 2-12 for e

versus G data.

2004 Microchip Technology Inc.

DS21908A-page 5

MCP6S91/2/3

DIGITAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= 25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2, C

= 60 pF, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

SPI Inputs (CS, SI, SCK)

Logic Threshold, Low

0.3V

Input Leakage Current

-1.0

+1.0

µA

Logic Threshold, High

0.7 V

Amplifier Output Leakage Current

-1.0

1.0

µA

In Shutdown mode

SPI Output (SO, for MCP6S93)

Logic Threshold, Low

OL_DIG

+0.4

= 2.1 mA, V

= 5V

Logic Threshold, High

OH_DIG

0.5

= -400 µA

SPI Timing

Pin Capacitance

All digital I/O pins

Input Rise/Fall Times (CS, SI, SCK)

RFI

µs

(Note 1)

Output Rise/Fall Times (SO)

RFO

MCP6S93

CS High Time

CSH

SCK Edge to CS Fall Setup Time

CS0

SCK edge when CS is high

CS Fall to First SCK Edge Setup Time

CSSC

SCK Frequency

SCK

MHz

= 5V (Note 2)

SCK High Time

SCK Low Time

SCK Last Edge to CS Rise Setup Time

SCCS

CS Rise to SCK Edge Setup Time

CS1

100

SCK edge when CS is high

SI Setup Time

SI Hold Time

SCK to SO Valid Propagation Delay

MCP6S93

CS Rise to SO Forced to Zero

SOZ

MCP6S93

Channel and Gain Select Timing

Channel Select Time

1.5

µs

CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CS = 0.7 V

to V

OUT

90% point

Gain Select Time

µs

CHx = CHy = 0.3V,
G = 5 to G = 1 select,
CS = 0.7 V

to V

OUT

90% point

Shutdown Mode Timing

Out of Shutdown mode (CS goes high)
to Amplifier Output Turn-on Time

3.5

µs

CS = 0.7 V

to V

OUT

90% point

Into Shutdown mode (CS goes high) to
Amplifier Output High-Z Turn-off Time

OFF

1.5

µs

CS = 0.7 V

to V

OUT

90% point

Note

Not tested in production. Set by design and characterization.

When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t

80 ns), data input set-up time (t

40 ns), SCK high time (t

40 ns) and SCK rise and

fall times of 5 ns. Maximum f

SCK

is therefore

5.8 MHz.

2004 Microchip Technology Inc.

DS21908A-page 6

MCP6S91/2/3

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

= +2.5V to +5.5V, V

= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

-40

+125

°C

(Note 1)

Operating Temperature Range

-40

+125

°C

Storage Temperature Range

-65

+150

°C

Thermal Package Resistances

Thermal Resistance, 8L-PDIP

°C/W

Thermal Resistance, 8L-SOIC

163

°C/W

Thermal Resistance, 8L-MSOP

206

°C/W

Thermal Resistance, 10L-MSOP

143

°C/W

Note 1:

Operation in this range must not cause T

to exceed Maximum Junction Temperature (+150°C).

2004 Microchip Technology Inc.

DS21908A-page 8

MCP6S91/2/3

FIGURE 1-5:

Detailed SPITM Serial Interface Timing; SPI 1,1 Mode.

1.1

DC Output Voltage Specs / Model

1.1.1

IDEAL MODEL

The ideal PGA output voltage (V

OUT

) is:

EQUATION 1-1:

(see Figure 1-6). This equation holds when there are
no gain or offset errors and when the V

REF

pin is tied to

a low-impedance source (<< 0.1

) at ground potential

= 0V).

1.1.2

LINEAR MODEL

The PGA's linear region of operation, including offset
and gain errors, is modeled by the line V

O_LIN

shown in

Figure 1-6.

EQUATION 1-2:

The end points of this line are at V

O_ID

= 0.3V and

0.3V. Figure 1-6 shows the relationship between

the gain and offset specifications referred to in the
electrical specifications as follows:

EQUATION 1-3:

The DC Gain Drift (

) can be calculated from the

change in g

across temperature. This is shown in the

following equation:

EQUATION 1-4:

SCK

CSSC

SCCS

(first 16 bits out are always zeros)

SOZ

1/f

SCK

CS1

CSH

CS0

Where:

G is the nominal gain

O_ID

VIN

REF

O_LIN

G 1

(

)

0.3V

-----------

0.3V

REF

100%

G V

0.6V

(

)

--------------------------------------

G 1

(

)

-------------------------

----------

2004 Microchip Technology Inc.

DS21908A-page 9

MCP6S91/2/3

FIGURE 1-6:

Output Voltage Model with

the standard condition V

REF

= V

= 0V.

1.1.3

OUTPUT NON-LINEARITY

Figure 1-7 shows the Integral Non-Linearity (INL) of the
output voltage.

EQUATION 1-5:

The output non-linearity specification in the Electrical
Specifications (with units of: % of FSR) is related to
Figure 1-7 by:

EQUATION 1-6:

The Full-Scale Range (FSR) is V

0.6V

(0.3V to V

0.3V).

FIGURE 1-7:

Output Voltage INL with the

standard condition V

REF

= V

= 0 V.

1.1.4

DIFFERENT V

REF

CONDITIONS

Some of the plots in Section 2.0 "Typical Performance
Curves", have the conditions V

REF

= V

/2 or

REF

= V

. The equations and figures above are easily

modified for these conditions. The ideal V

OUT

equation

becomes:

EQUATION 1-7:

The complete linear model is:

EQUATION 1-8:

where the new V

end points are:

EQUATION 1-9:

The equations for extracting the specifications do not
change.

0.3

OUT

(V)

0.3

0.3 V

INL

OUT

O_LIN

ONL

max V

(

)

0.6V

------------------------------- 100%

INL (V)

(V)

0.3

0.3 V

O_ID

REF

G V

REF

(

)

REF

ON_LIN

G 1

(

)

IN_L

(

)

0.3V

R EF

IN_L

0.3V

REF

------------------------------

REF

IN_H

0.3V

REF

-----------------------------------------------

REF

2004 Microchip Technology Inc.

DS21908A-page 10

MCP6S91/2/3

2.0

TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-1:

DC Gain Error, G = +1.

FIGURE 2-2:

DC Gain Error, G

+2.

FIGURE 2-3:

Ladder Resistance Drift.

FIGURE 2-4:

DC Gain Drift, G = +1.

FIGURE 2-5:

DC Gain Drift, G

+2.

FIGURE 2-6:

Crosstalk vs. Frequency

(circuit in Figure 6-4).

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

12%

14%

16%

18%

20%

22%

24%

-0

.
1

-0

.
0

-0

.
0

-0

.
0

-0

.
0

0.0

0.1

DC Gain Error (%)

r
cen

tag

f
O

ccur

r
e

nces

600 Samples
G = +1

10%

12%

14%

16%

18%

-0

.
6

-0

.
5

-0

.
4

-0

.
3

-0

.
2

-0

.
1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

DC Gain Error (%)

r
cen

tag

f
O

ccur

r
e

nce

600 Samples
G

10%

12%

14%

16%

.
019

.
020

.
021

.
022

.
023

.
024

.
025

.
026

.
027

.
028

.
029

.
030

Ladder Resistance Drift (%/°C)

r
c

ent

ge of Occu

r
r
enc

597 Samples
T

= -40 to +125°C

10%

15%

20%

25%

30%

35%

-0.

0006

-0.

0005

-0.

0004

-0.

0003

-0.

0002

-0.

0001

0000

0001

0002

0003

0004

0005

0006

DC Gain Drift (%/°C)

rce

ge o

f
O

ccur

r
e

nce

600 Samples
G = +1
T

= -40 to +125°C

10%

12%

14%

16%

18%

20%

22%

24%

26%

-0.

0020

-0.

0016

-0.

0012

-0.

0008

-0.

0004

0000

0004

0008

0012

0016

0020

DC Gain Drift (%/°C)

rce

ge o

f
O

ccur

r
e

nce

600 Samples
G

= -40 to +125°C

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

1.E+05

1.E+06

1.E+07

1.E+08

Frequency (Hz)

r
oss

t
al

k, In

t R

f
e

r
r
ed

)

= 5.0V

G = +32 V/V
CH0 selected

= 1 k

= 0

= 100

= 10 k

100k

100M

10M

2004 Microchip Technology Inc.

DS21908A-page 11

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-7:

Input Offset Voltage,

= 4.0V.

FIGURE 2-8:

Input Offset Voltage

Mismatch.

FIGURE 2-9:

Input Noise Voltage Density

vs. Frequency.

FIGURE 2-10:

Input Offset Voltage Drift.

FIGURE 2-11:

Input Offset Voltage vs.

REF

Voltage.

FIGURE 2-12:

Input Noise Voltage Density

vs. Gain.

10%

15%

20%

25%

30%

-3

-2

-1

Input Offset Voltage (mV)

r
cent

Occu

r
r
en

ces

600 Samples
G = +1
V

= 4.0V

10%

15%

20%

25%

30%

35%

-30

-20

-10

Input Offset Voltage Mismatch (µV)

r
cen

tag

Occ

r
r
en

ces

32 Samples
V

= 5.5V

= 0.3V

= 10.0 µV

RMS

Measurement
Repeatability:
10.4 µV

RMS

100

1000

0.1

100

1000

10000

100000

Frequency (Hz)

Input Noise Voltage Density

(nV/

Hz)

10k

100k

100

0.1

10%

12%

14%

16%

18%

20%

22%

24%

-10

-8

-6

-4

-2

Input Offset Voltage Drift (µV/°C)

r
cen

tag

cur

r
e

ces

600 Samples
T

= -40 to +125°C

G = +1

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

REF

Voltage (V)

t
Off

set

lta

e (

)

= 5.5V

= 2.5V

G = +1
V

= V

REF

Gain (V/V)

Input Noise Voltage Density

(nV/

Hz)

f = 10 kHz

2004 Microchip Technology Inc.

DS21908A-page 12

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-13:

PSRR vs. Ambient

Temperature.

FIGURE 2-14:

Input Bias Current vs.

Ambient Temperature.

FIGURE 2-15:

Quiescent Current in

Shutdown Mode vs. Ambient Temperature.

FIGURE 2-16:

PSRR vs. Frequency.

FIGURE 2-17:

Input Bias Current vs. Input

Voltage.

FIGURE 2-18:

Quiescent Current in

Shutdown Mode.

100

110

120

-50

-25

100

125

Ambient Temperature (°C)

wer

ly Rej

ecti

tio

(dB

)

100

1,000

100

125

Ambient Temperature (°C)

I
n

put

i
as C

r
r
e

)

= 5.5V

CH0 = 5.0V

MCP6S92/3

MCP6S91

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

-50

-25

100

125

Ambient Temperature (°C)

iesce

nt C

r
r
ent

hut

(

)

In Shutdown Mode
CH0 = V

= 2.5V

= 5.5V

100n

10n

100p

10p

100f

100

100

1000

10000

100000

1000000

Frequency (Hz)

ppl

y R

j
e

t
i
o

n R

t
i
o

)

= 5.5V

= 2.5V

10k

100

Input Referred

100k

100

1,000

10,000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

t B

i
as

r
r
ent

(

)

= +85°C

MCP6S92/3
V

= 5.5V

= +125°C

10%

15%

20%

25%

Quiescent Current in Shutdown (pA)

r
cen

tag

Occ

r
r
en

ces

39 Samples
V

= 5.5V

CH0 = V

2004 Microchip Technology Inc.

DS21908A-page 13

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-19:

Quiescent Current vs.

Supply Voltage.

FIGURE 2-20:

DC Output Non-Linearity vs.

Supply Voltage.

FIGURE 2-21:

Output Voltage Headroom

vs. Output Plus Ladder Current (circuit in
Figure 4-2).

FIGURE 2-22:

Output Short Circuit Current

vs. Supply Voltage.

FIGURE 2-23:

DC Output Non-Linearity vs.

Output Swing.

FIGURE 2-24:

Output Voltage Swing vs.

Frequency.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Supply Voltage (V)

Qui

escen

t C

r
r
ent

(

)

= +125°C

= +85°C

= +25°C

= -40°C

0.001

0.01

0.1

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Power Supply Voltage (V)

n-L

i
nea

r
i
t
y,

I
n

t R

f
e

)

OUT

= 0.3V to V

- 0.3V

ONL

/G, G = +1

G = +2
G

100

1000

0.1

Output Plus Ladder Current Magnitude (mA)

ltag

e H

ead

r
o

;

-V

)

= 5.5V

= 2.5V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

t
put

r
t
C

i
rc

t
C

r
r
e

Mag

i
t
ude

)

= +125°C

= +85°C

= +25°C

= -40°C

0.001

0.01

0.1

Output Voltage Swing (V

P-P

)

n-L

i
nea

r
i
t
y,

I
n

t R

f
e

)

= 5.5V

ONL

/G:

G = +1
G = +2
G

0.1

1.E+05

1.E+06

1.E+07

Frequency (Hz)

Out

t

V

age S

i
ng (V

P-

)

100k

10M

= 5.5V

= 2.5V

G = 1, 2

G = 4 to 10

G = 16, 32

2004 Microchip Technology Inc.

DS21908A-page 14

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-25:

Gain vs. Frequency.

FIGURE 2-26:

Bandwidth vs. Capacitive

Load.

FIGURE 2-27:

THD plus Noise vs.

Frequency, V

OUT

= 2 V

P-P

FIGURE 2-28:

Gain Peaking vs. Capacitive

Load.

FIGURE 2-29:

The MCP6S91/2/3 family

shows no phase reversal under overdrive.

FIGURE 2-30:

THD plus Noise vs.

Frequency, V

OUT

= 4 V

P-P

-20

-10

1.E+05

1.E+06

1.E+07

1.E+08

Frequency (Hz)

Gai

(

G = +2
G = +1

10M

100M

100k

G = +32
G = +16

G = +10

G = +8
G = +5
G = +4

100

1000

Capacitive Load (pF)

i
d

t
h (

)

G = +1
G = +4
G = +16

0.0001

0.001

0.01

0.1

1.E+02

1.E+03

1.E+04

1.E+05

Frequency (Hz)

HD + No

(

)

100

100k

10k

G = +1, R

= 10 k

to 1.5V

G = +4

G = +1

G = +16

Measurement BW = 80 kHz
V

OUT

= 2.0V

P-P

= 5.0V

100

1000

Capacitive Load (pF)

i
n

(
d

)

G = +16
G = +4
G = +1

-1

Time (1 µs/div)

I
n

put

,
O

Vol

t
ag

e (V

)

= 5.0V

G = +1 V/V

OUT

0.0001

0.001

0.01

0.1

1.E+02

1.E+03

1.E+04

1.E+05

Frequency (Hz)

D + No

(

)

Measurement BW = 80 kHz
V

OUT

= 4 V

P-P

= 5.0V

100

100k

10k

G = +4
G = +1

G = +16

2004 Microchip Technology Inc.

DS21908A-page 15

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-31:

Small-Signal Pulse

Response.

FIGURE 2-32:

Channel Select Timing.

FIGURE 2-33:

Output Voltage vs.

Shutdown Mode.

FIGURE 2-34:

Large-Signal Pulse

Response.

FIGURE 2-35:

Gain Select Timing.

FIGURE 2-36:

Minimum Valid Supply

Voltage (register data still valid).

-60

-50

-40

-30

-20

-10

0.000

0.200

0.400

0.600

0.800

1.000

1.200

1.400

1.600

1.800

2.000

Time (200 ns/div)

t
V

ltag

(10

iv)

-300

-250

-200

-150

-100

-50

100

150

200

250

300

r
m

lized

t V

(
50 m

/di

)

= 5.0V

OUT

G = +1
G = +5
G = +32

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

Time (500 ns/div)

tpu

t
V

age

)

-20

-15

-10

-5

ip S

l
ect V

l
t
ag

)

OUT

(CH0 = 0.6V,

G = +1)

OUT

(CH1 = 0.3V, G = +1)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.E+00

1.E+00

2.E+00

3.E+00

4.E+00

5.E+00

6.E+00

7.E+00

8.E+00

9.E+00

1.E+01

Time (1 µs/div)

t
put

l
t
a

e (

)

-15

-10

-5

lect

ltag

e (

)

OUT

is "ON"

Shutdown

= 5.0V

CH0 = 0.3V
G = +1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Time (500 ns/div)

t
V

lta

e (

)

-2.5

-1.5

-0.5

0.5

1.5

2.5

3.5

4.5

5.5

6.5

7.5

r
m

ized

t V

lta

/
d

i
v

)

= 5.0V

OUT

G = +1
G = +5
G = +32

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

Time (500 ns/div)

tpu

t
V

l
t
ag

e (V

)

-20

-15

-10

-5

l
ect

ltag

e (

)

OUT

(CH0 = 0.3V, G = +5)

OUT

(CH0 = 0.3V, G = +1)

10%

20%

30%

40%

50%

60%

70%

80%

90%

0.0

0.5

1.0

1.5

2.0

Minimum Valid Supply Voltage (V)

r
cen

tag

f
Oc

cur

r
en

ces

32 Samples

Wafer Lot

2004 Microchip Technology Inc.

DS21908A-page 16

MCP6S91/2/3

Note: Unless otherwise indicated, T

= +25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, R

= 10 k

to V

/2 and C

= 60 pF.

FIGURE 2-37:

Input Offset Voltage vs.

Input Voltage, V

= 2.5V.

FIGURE 2-38:

Output Voltage Headroom

vs. Ambient Temperature.

FIGURE 2-39:

Input Offset Voltage vs.

Input Voltage, V

= 5.5V.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.0

0.5

1.0

1.5

2.0

2.5

Input Voltage (V)

Off

set

lta

e (

)

G = 1 V/V
V

= 2.5V

= +125°C

= +85°C

= +25°C

= -40°C

-50

-25

100

125

Ambient Temperature (°C)

t
put

l
t
age

r
oom

;

and

)

= 5.5V: V

= 2.5V: V

REF

= V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Off

set

lta

e (

)

G = 1 V/V
V

= 5.5V

= +125°C

= +85°C

= +25°C

= -40°C

2004 Microchip Technology Inc.

DS21908A-page 17

MCP6S91/2/3

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

3.1

Analog Output

The output pin (V

OUT

) is a low-impedance voltage

source. The selected gain (G), selected input (CH0,
CH1) and voltage at V

REF

determine its value.

3.2

Analog Inputs (CH0, CH1)

The inputs CH0 and CH1 connect to the signal
sources. They are high-impedance CMOS inputs with
low bias currents. The internal MUX selects which one
is amplified to the output.

3.3

External Reference Voltage (V

REF

)

The V

REF

pin, which is an analog input, should be at a

voltage between V

and V

(the MCP6S92 has

REF

tied internally to V

). The voltage at this pin

shifts the output voltage.

3.4

Power Supply (V

and V

)

The Positive Power Supply Pin (V

) is 2.5V to 5.5V

higher than the Negative Power Supply Pin (V

). For

normal operation, the other pins are at voltages
between V

and V

Typically, these parts are used in a single (positive)
supply configuration. In this case, V

is connected to

ground and V

is connected to the supply. V

will

need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the V

pin. These parts can

share a bulk capacitor with analog parts (typically
2.2 µF to 10 µF) within 100 mm of the V

pin.

3.5

Digital Inputs

The SPI interface inputs are: Chip Select (CS), Serial
Input (SI) and Serial Clock (SCK). These are Schmitt-
triggered, CMOS logic inputs.

3.6

Digital Output

The MCP6S93 device has a SPI interface Serial Output
(SO) pin. This is a CMOS push-pull output and does
not ever go High-Z. Once the device is deselected (CS
goes high), SO is forced low. This feature supports
daisy-chaining, as explained in Section 5.3 "Daisy-
Chain Configuration".

MCP6S91

MCP6S92

MCP6S93

Symbol

Description

OUT

Analog Output

CH0

Analog Input

CH1

Analog Input

REF

External Reference Pin

Negative Power Supply

SPITM Chip Select

SPI Serial Data Input

SPI Serial Data Output

SCK

SPI Clock Input

Positive Power Supply

2004 Microchip Technology Inc.

DS21908A-page 18

MCP6S91/2/3

4.0

ANALOG FUNCTIONS

The MCP6S91/2/3 family of Programmable Gain
Amplifiers (PGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.

FIGURE 4-1:

PGA Block Diagram.

4.1

Input MUX

The MCP6S91 has one input, while the MCP6S92 and
MCP6S93 have two inputs (see Figure 4-1).

For the lowest input current, float unused inputs. Tying
these pins to a voltage near the active channel's bias
voltage also works well. For simplicity, they can be tied
to V

or V

, but the input current may increase.

The one-channel MCP6S91 has approximately the
same input bias current as the two-channel MCP6S92
and MCP6S93.

The input offset voltage mismatch between channels
(

) is, ideally, 0 µV. The input MUX uses CMOS

transmission gates that have drain-source (channel)
resistance, but no offset voltage. The histogram in
Figure 2-8 reflects the measurement repeatability
(i.e., noise power bandwidth) rather than the actual
mismatch. Reducing the measurement bandwidth will
produce a more narrow histogram and give an aver-
age closer to 0 µV.

4.2

Internal Op Amp

The internal op amp gives the right combination of
bandwidth, accuracy and flexibility.

4.2.1

COMPENSATION CAPACITORS

The internal op amp has three compensation capaci-
tors (comp. caps.) connected to a switching network.
They are selected to give good small-signal bandwidth
at high gains and good slew rates (full-power band-
width) at low gains. The change in bandwidth as gain
changes is between 2 and 12 MHz. Refer to Table 4-1
for more information.

TABLE 4-1:

GAIN VS. INTERNAL
COMPENSATION
CAPACITOR

4.2.2

RAIL-TO-RAIL CHANNEL INPUTS

The input stage of the internal op amp uses two differ-
ential input stages in parallel; one operates at low V

(input voltage), while the other operates at high V

With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both V

= V

0.3V and V

+ 0.3V to

ensure proper operation.

The transition between the two input stages occurs
when V

1.5V. For the best distortion and gain

linearity, avoid this region of operation.

MCP6S91 One input (CH0), no SO pin

MCP6S92 Two inputs (CH0, CH1), V

REF

tied

internally to V

, no SO pin

MCP6S93 Two inputs (CH0, CH1)

OUT

REF

SCK

CH1

CH0

MUX

SPITM

Logic

Gain

Switches

i
s

t
or

Lad

de
r (R

LA
D

)

Gain
(V/V)

Internal

Comp.

Cap.

GBWP

(MHz)

Typ.

(V/µs)

Typ.

FPBW

(MHz)

Typ.

(MHz)

Typ.

Large

4.0

0.30

Large

4.0

0.30

Medium

0.70

Medium

0.70

Medium

0.70

2.4

Medium

0.70

2.0

Small

1.6

Small

1.6

2.0

Note 1:

FPBW is the Full-Power Bandwidth.
These numbers are based on V

= 5.0V.

No changes in DC performance
(e.g., V

) accompany a change in

compensation capacitor.

BW is the closed-loop, small signal -3 dB
bandwidth.

2004 Microchip Technology Inc.

DS21908A-page 19

MCP6S91/2/3

4.2.3

RAIL-TO-RAIL OUTPUT

The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (I

OUT

) and the current through the ladder

resistance (I

LAD

); see Figure 4-2.

EQUATION 4-1:

FIGURE 4-2:

Amplifier Load Current.

See Figure 2-21 for the typical output headroom
(V

or V

) as a function of amplifier

load current.

The specification table states the output can reach
within 60 mV of either supply rail when R

= 10 k

and

REF

= V

/2.

4.2.4

INPUT VOLTAGE AND PHASE
REVERSAL

The MCP6S91/2/3 amplifier family is designed with
CMOS input devices. It is designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-29 shows an input voltage
exceeding both supplies with no resulting phase
inversion.

The maximum voltage that can be applied to the input
pins (CHx) is V

0.3V to V

+ 0.3V. Voltages on

the inputs that exceed this absolute maximum rating
can cause excessive current to flow into or out of the
input pins. Current beyond ±2 mA can cause possible
reliability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 4-3.

FIGURE 4-3:

limits the current flow

into an input pin.

4.3

Resistor Ladder

The resistor ladder shown in Figure 4-1
(R

LAD

= R

+ R

) sets the gain. Placing the gain

switches in series with the inverting input reduces the
parasitic capacitance, distortion and gain mismatch.

LAD

is an additional load on the output of the PGA and

causes additional current draw from the supplies. It is
also a load (Z

IN_REF

) on the external circuitry driving

the V

REF

pin.

In Shutdown mode, R

LAD

is still attached to the V

OUT

and V

REF

pins. Thus, these pins and the internal ampli-

fier's inverting input are all connected through R

LAD

and the output is not High-Z (unlike the internal op
amp).

While R

LAD

contributes to the output noise, its effect is

small. Refer to Figure 2-12.

Where:

Amplifier Load Current

OUT

LAD

OUT

REF

(

)

LAD

-------------------------------------

OUT

REF

LAD

OUT

LAD

MCP6S9X

CHx

 (Maximum expected V

)

2 mA

(Maximum expected V

) V

2 mA

OUT

2004 Microchip Technology Inc.

DS21908A-page 20

MCP6S91/2/3

4.4

Rail-to-Rail V

REF

Input

The V

REF

input is intended to be driven by a low-

impedance voltage source. The source driving the
V

REF

pin should have an output impedance less than

0.1

to maintain reasonable gain accuracy. The supply

voltage V

and V

usually meet this requirement.

LAD

presents a load at the V

REF

pin to the external

circuit (Z

IN_REF

(5 k

/G)||(6 pF)), which depends on

the gain. Any source driving the V

REF

pin must be

capable of driving a load as heavy as 0.16 k

||6 pF

(G = 32).

The absolute maximum voltages that can be applied to
the reference input pin (V

REF

) are V

0.3V and

+ 0.3V. Voltages on the inputs that exceed this

absolute maximum rating can cause excessive current
to flow into or out of this pin. Current beyond ±2 mA can
cause possible reliability problems. Because an
external series resistor cannot be used (for low gain
error), the external circuit must ensure that V

REF

between V

0.3V and V

+ 0.3V.

The V

IVR_REF

spec shows the region of normal

operation for the V

REF

pin (V

to V

). Staying within

this region ensures proper operation of the PGA and its
surrounding circuitry.

4.5

Shutdown Mode

These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
in a High-Z state.

The resistive ladder is always connected between
V

REF

and V

OUT

; even in shutdown. This means that the

output resistance will be on the order of 5 k

, with a

path for output signals to appear at the input.

2004 Microchip Technology Inc.

DS21908A-page 21

MCP6S91/2/3

5.0

DIGITAL FUNCTIONS

The MCP6S91/2/3 PGAs use a standard SPI
compatible serial interface to receive instructions from
a controller. This interface is configured to allow daisy-
chaining with other SPI devices.

5.1

SPI Timing

Chip Select (CS) toggles low to initiate communica-
tion with these devices. The first byte of each SI word
(two bytes long) is the instruction byte, which goes
into the Instruction register. The Instruction register
points the second byte to its destination. In a typical
application, CS is raised after one word (16 bits) to
implement the desired changes. Section 5.3 "Daisy-

Chain Configuration", covers applications using
multiple 16-bit words. SO goes low after CS goes
high; it has a push-pull output that does not go into a
high-Z state.

The MCP6S91/2/3 devices operate in SPI modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1). In 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK, while SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3 "Daisy-Chain Configuration").

FIGURE 5-1:

Serial Bus Sequence for the PGA; SPITM 0,0 Mode (see Figure 1-4).

FIGURE 5-2:

Serial Bus Sequence for the PGA; SPITM 1,1 Mode (see Figure 1-5).

bit 7

SCK

Instruction Byte

Data Byte

bit 0

bit

(first 16 bits out are always zeros)

bit

SCK

Instruction Byte

Data Byte

bit

(first 16 bits out are always zeros)

2004 Microchip Technology Inc.

DS21908A-page 22

MCP6S91/2/3

5.2

Registers

The analog functions are programmed through the SPI
interface using 16-bit words (see Figure 5-1 and
Figure 5-2). This data is sent to two of three 8-bit regis-
ters: Instruction register (Register 5-1), Gain register
(Register 5-2) and Channel register (Register 5-3).
There are no power-up defaults for these three
registers.

5.2.1

ENSURING VALID DATA IN THE
REGISTERS

After power up, the registers contain random data that
must be initialized. Sending valid gain and channel
selection commands to the internal registers puts valid
data into those registers. Also, the internal state
machine starts in an arbitrary state. Toggling the Chip
Select pin (CS) from high to low, then back to high
again, puts the internal state machine in a known, valid
condition (this can be done by entering any valid
command).

After power-up, and when the power supply voltage
dips below the minimum valid V

DD_VAL

), the inter-

nal register data and state machine may need to be
reset. This is accomplished as described before. Use
an external system supervisor to detect these events
so that the microcontroller will reset the PGA state and
registers.

A 0.1 µF bypass capacitor mounted as close as
possible to the V

pin provides additional transient

immunity.

5.2.2

INSTRUCTION REGISTER

The Instruction register has 3 command bits and 1 indi-
rect address bit; see Register 5-1. The command bits
include a

NOP

(

000

) to support daisy-chaining (see

Section 5.3 "Daisy-Chain Configuration"); the other

NOP

commands shown should not be used (they are

reserved for future use). The device is brought out of
Shutdown mode when a valid command, other than

NOP

or Shutdown, is sent and CS is raised.

REGISTER 5-1:

INSTRUCTION REGISTER

W-0

U-x

W-0

bit 7

bit 0

bit 7-5

M2-M0: Command bits

000

NOP

(Note 1)

001

PGA enters Shutdown mode as soon as a full 16-bit word is sent and CS is raised.
(Notes 1 and 2)

010

Write to register.

011

NOP

(reserved for future use) (Note 1)

1XX

NOP

(reserved for future use) (Note 1)

bit 4-1

Unimplemented: Read as `0' (reserved for future use)

bit 0

A0: Indirect Address bit

= Addresses the Channel register

= Addresses the Gain register

Note 1:

All other bits in the 16-bit word (including A0) are "don't cares."

The device exits Shutdown mode when a valid command (other than

NOP

Shutdown) is sent and CS is raised; that valid command will be executed.
Shutdown does not toggle.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

-n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2004 Microchip Technology Inc.

DS21908A-page 23

MCP6S91/2/3

5.2.3

SETTING THE GAIN

The amplifier can be programmed to produce binary
and decimal gain settings between +1 V/V and +32 V/V.
Register 5-2 shows the details. At the same time, differ-
ent compensation capacitors are selected to optimize
the bandwidth vs. slew rate trade-off (see Table 4-1).

REGISTER 5-2:

GAIN REGISTER

U-x

W-0

bit 7

bit 0

bit 7-3

Unimplemented: Read as `0' (reserved for future use)

bit 2-0

G2-G0: Gain Select bits

000

= Gain of +1

001

= Gain of +2

010

= Gain of +4

011

= Gain of +5

100

= Gain of +8

101

= Gain of +10

110

= Gain of +16

111

= Gain of +32

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

-n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2004 Microchip Technology Inc.

DS21908A-page 25

MCP6S91/2/3

5.2.5

SHUTDOWN COMMAND

The software shutdown command allows the user to
put the amplifier into a low-power mode (see
Register 5-1). In this Shutdown mode, most pins are
high-impedance (Section 4.5 "Shutdown Mode" and
Section 5.1 "SPI Timing" cover the exceptions at pins
V

REF,

OUT

and SO).

Once the PGA has entered Shutdown mode, it will
remain in this mode until either a valid command is sent
to the device (other than

NOP

or Shutdown) or the

device is powered down and back up again. The
internal registers maintain their values while in
shutdown.

Once brought out of Shutdown mode, the part returns
to its previous state (see Section 5.2.1 "Ensuring
Valid Data in the Registers" for exceptions to this
rule). This makes it possible to bring the device out of
shutdown mode using one command; send a com-
mand to select the current channel (or gain) and the
device will exit shutdown with the same state that
existed before shutdown.

5.3

Daisy-Chain Configuration

Multiple MCP6S91/2/3 devices can be connected in a
daisy-chain configuration by connecting the SO pin
from one device to the SI pin on the next device and
using common SCK and CS lines (Figure 5-3). This
approach reduces PCB layout complexity and uses
fewer PICmicro

microcontroller I/O pins.

The example in Figure 5-3 shows a daisy-chain
configuration with two devices, although any number of
devices can be configured this way. The MCP6S91 and
MCP6S92 can only be used at the far end of the daisy-
chain, because they do not have a serial data out (SO)
pin. As shown in Figure 5-4 and Figure 5-5, both SI and
SO data are sent in 16-bit (2 byte) words. These
devices abort any command that is not a multiple of 16
bits.

When using the daisy-chain configuration, the maxi-
mum clock speed possible is reduced to

5.8 MHz due

to the SO pin's propagation delay (see Electrical
Specifications).

The internal SPI shift register is automatically loaded
with zeros whenever CS goes high (a command is
executed). Thus, the first 16-bits out of the SO pin after
the CS line goes low are always zeros. This means that
the first command loaded into the next device in the
daisy-chain is a

NOP

. This feature makes it possible to

send shorter command and data byte strings when the
farthest devices do not need to change. For example, if
there were three devices on the chain, and only the
middle device needed changing, then only 32 bytes of
data need to be transmitted (for the first and middle
devices). The last device on the chain would receive a

NOP

when the CS pin is raised to execute the

command.

FIGURE 5-3:

Daisy-Chain Configuration.

PICmicro

CS
SCK
SI

SCK

Device 1

00100000 00000000

CS
SCK
SI

Device 2

00000000 00000000

Device 1

01000001 00000111

Device 2

00100000 00000000

4. Clock out the instruction and data
for Device 1 (16 clocks) to Device 1.
5. Device 1 automatically shifts data
from Device 1 to Device 2 (16 clocks).
6. Raise CS.

1. Set CS low.
2. Clock out the instruction and data
for device 2 (16 clocks) to Device 1.
3. Device 1 automatically clocks out all
zeros (first 16 clocks) to Device 2.

Microcontroller

2004 Microchip Technology Inc.

DS21908A-page 26

MCP6S91/2/3

FIGURE 5-4:

Serial Bus Sequence for Daisy-Chain Configuration; SPITM 0,0 Mode.

FIGURE 5-5:

Serial Bus Sequence for Daisy-Chain Configuration; SPITM 1,1 Mode.

1 2 3 4 5 6 7 8 9 10111213141516

t 7

SCK

Instruction Byte

Data Byte

t 0

t 7

t 0

(first 16 bits out are always zeros)

1 2 3 4 5 6 7 8 9 10111213141516

t
7

Instruction Byte

Data Byte

t
0

t
7

t
0

for Device 2

for Device 1

bit

Instruction Byte

Data Byte

bit

for Device 2

1 2 3 4 5 6 7 8 9 10111213141516

t 7

SCK

Instruction Byte

Data Byte

t 0

t 7

t 0

(first 16 bits out are always zeros)

1 2 3 4 5 6 7 8 9 10111213141516

t
7

Instruction Byte

Data Byte

t
0

t
7

t
0

for Device 2

for Device 1

bit

Instruction Byte

Data Byte

bit

for Device 2

2004 Microchip Technology Inc.

DS21908A-page 27

MCP6S91/2/3

6.0

APPLICATIONS INFORMATION

6.1

Changing External Reference
Voltage

Figure 6-1 shows a MCP6S91 with the V

REF

pin at

2.5V and V

= 5.0V. This allows the PGA to amplify

signals centered on 2.5V, instead of ground-referenced
signals. The voltage reference MCP1525 is buffered by
a MCP6021, which gives a low output impedance
reference voltage from DC to high frequencies. The
source driving the V

REF

pin should have an output

impedance less than 0.1

to maintain reasonable gain

accuracy.

FIGURE 6-1:

PGA with Different External

Reference Voltage.

6.2

Capacitive Load and Stability

Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6S91/2/3 family of
PGAs (Figure 2-26 and Figure 2-28). As the load
capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier's phase margin and bandwidth.

When driving large capacitive loads with these PGAs
(i.e., > 60 pF), a small series resistor at the output
(R

ISO

in Figure 6-2) improves the internal amplifier's

stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.

FIGURE 6-2:

PGA Circuit for Large

Capacitive Loads.

Figure 6-3 gives recommended R

ISO

values for

different capacitive loads. After selecting R

ISO

for your

circuit, double-check the resulting frequency response
peaking and step response overshoot on the bench.
Modify R

ISO

's value until the response is reasonable at

all gains.

FIGURE 6-3:

Recommended R

ISO

6.3

Layout Considerations

Good PC board layout techniques will help achieve the
performance shown in the Electrical Characteristics
and Typical Performance Curves. It will also help
minimize Electromagnetic Compatibility (EMC) issues.

6.3.1

COMPONENT PLACEMENT

Separate different circuit functions: digital from analog,
low-speed from high-speed, and low-power from high-
power. This will reduce crosstalk.

Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.

REF

OUT

MCP1525

MCP6021

1µF

MCP6S91

2.5V
REF

OUT

MCP6S9X

ISO

100

1,000

100

1,000

10,000

oad Capacitance (F)

(

)

100

2004 Microchip Technology Inc.

DS21908A-page 28

MCP6S91/2/3

6.3.2

SUPPLY BYPASS

Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the V

pin. It must connect directly to the

ground plane. A multi-layer ceramic chip capacitor, or
high-frequency equivalent, works best.

Use a bulk bypass capacitor (2.2 µF to 10 µF) within
100 mm of the V

pin. It needs to connect to the

ground plane. A multi-layer ceramic chip capacitor,
tantalum or high-frequency equivalent, works best.
This capacitor may be shared with other nearby analog
parts.

6.3.3

INPUT SOURCE IMPEDANCE

The sources driving the inputs of the PGAs need to
have reasonably low source impedance at higher
frequencies. Figure 6-4 shows how the external source
impedance (R

), PGA package pin capacitance (C

)

and PGA package pin-to-pin capacitance (C

) form a

positive feedback voltage divider network. Feedback to
the selected channel may cause frequency response
peaking and step response overshoot and ringing.
Feedback to an unselected channel will produce
crosstalk.

FIGURE 6-4:

Positive Feedback Path.

Figure 2-6 shows the crosstalk (referred to input) that
results when a hostile signal is connected to CH1, input
CH0 is selected and R

is connected from CH0 to

GND. A gain of +32 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing R

increases the crosstalk as expected. At a source
impedance of 10 k

there is noticeable peaking in the

response; this is due to positive feedback.

Most designs should use a source resistance (R

) no

larger than 10 k

. Careful attention to layout parasitics

and proper component selection will help minimize this
effect. When a source impedance larger than 10 k

must be used, place a capacitor in parallel to C

reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk) peak-
ing, yet small enough to allow a reasonable signal
bandwidth.

6.3.4

SIGNAL COUPLING

The input pins of the MCP6S91/2/3 family of PGAs are
high-impedance. This makes them especially suscepti-
ble to capacitively-coupled noise. Using a ground plane
helps reduce this problem.

When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.

Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.

6.3.5

HIGH-FREQUENCY ISSUES

Because the MCP6S91/2/3 PGAs' frequency response
reaches unity gain at 64 MHz when G = 16 and 32, it is
important to use good PCB layout techniques. Any
parasitic-coupling at high-frequency might cause
undesired peaking. Filtering high-frequency signals
(i.e., fast edge rates) can help. To minimize high-
frequency problems:

· Use complete ground and power planes

· Use HF, surface-mount components

· Provide clean supply voltages and bypassing

· Keep traces short and straight

· Try a linear power supply (e.g., a LDO)

MCP6S9X

OUT

2004 Microchip Technology Inc.

DS21908A-page 29

MCP6S91/2/3

6.4

Typical Applications

6.4.1

GAIN RANGING

Figure 6-5 shows a circuit that measures the current I

The circuit's performance benefits from changing the
gain on the PGA. Just as a hand-held multimeter uses
different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the PGA's output
is less than at its input (by up to 30 dB).

FIGURE 6-5:

Wide Dynamic Range

Current Measurement Circuit.

6.4.2

SHIFTED GAIN RANGE PGA

Figure 6-6 shows a circuit using a MCP6291 at a gain
of +10 in front of a MCP6S91. This shifts the overall
gain range to +10 V/V to +320 V/V (from +1 V/V to
+32 V/V).

FIGURE 6-6:

PGA with Higher Gain

Range.

It is also easy to shift the gain range to lower gains (see
Figure 6-7). The MCP6291 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V).

FIGURE 6-7:

PGA with Lower Gain

Range.

6.4.3

EXTENDED GAIN RANGE PGA

Figure 6-8 gives a +1 V/V to +1024 V/V gain range,
which is much greater than the range for a single PGA
(+1 V/V to +32 V/V). The first PGA provides input
multiplexing capability, while the second PGA only
needs one input. These devices can be daisy-chained
(Section 5.3 "Daisy-Chain Configuration").

FIGURE 6-8:

PGA with Extended Gain

Range.

6.4.4

MULTIPLE SENSOR AMPLIFIER

The multiple-channel PGAs (MCP6S92 and MCP6S93)
allow the user to select which sensor appears on the
output (see Figure 6-9). These devices can also change
the gain to optimize performance for each sensor.

FIGURE 6-9:

PGA with Multiple Sensor

Inputs.

OUT

MCP6S9X

OUT

MCP6291

MCP6S91

1.11 k

10.0 k

MCP6291

1.11 k

10.0 k

OUT

MCP6S91

OUT

MCP6S92

MCP6S91

Sensor # 0

OUT

MCP6S93

Sensor # 1

2004 Microchip Technology Inc.

DS21908A-page 30

MCP6S91/2/3

6.4.5

EXPANDED INPUT PGA

Figure 6-10 shows cascaded MCP6S28 and
MCP6S92s PGAs that provide up to 9 input channels.
Obviously, Sensors #1-8 have a high total gain range
available, as explained in Section 6.4.3 "Extended
Gain Range PGA". These devices can be daisy-
chained (Section 5.3 "Daisy-Chain Configuration").

FIGURE 6-10:

PGA with Expanded Inputs.

6.4.6

PICmicro

MCU WITH EXPANDED

INPUT CAPABILITY

Figure 6-11 shows a MCP6S93 driving an analog input
to a PICmicro microcontroller. This greatly expands the
input capacity of the microcontroller, while adding the
ability to select the appropriate gain for each source.

FIGURE 6-11:

Expanded Input for a

PICmicro

Microcontroller.

6.4.7

ADC DRIVER

This family of PGAs is well suited for driving Analog-to-
Digital Converters (ADCs). The binary gains (1, 2, 4, 8,
16 and 32) effectively add five more bits to the input
range (see Figure 6-12). This works well for applica-
tions needing relative accuracy more than absolute
accuracy (e.g., power monitoring).

FIGURE 6-12:

PGA as an ADC driver.

At low gains, the ADC's Signal-to-Noise Ratio (SNR)
will dominate since the PGA's input noise voltage
density is so low (10 nV/

Hz @ 10 kHz, typ.). At high

gains, the PGA's noise will dominate the SNR, but it is
low enough to support most applications. These PGAs
add the flexibility of selecting the best gain for an
application.

The low-pass filter in the block diagram reduces the
integrated noise at the MCP6S92's output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip's FilterLab

software, available at

www.microchip.com.

Sensor

OUT

MCP6S92

# 0

Sensors

MCP6S28

# 1-8

SPI

MCP6S93

PICmicro

Microcontroller

OUT

MCP3201

12-bit

ADC

MCP6S92

Low-pass

Filter

2004 Microchip Technology Inc.

DS21908A-page 31

MCP6S91/2/3

7.0

PACKAGING INFORMATION

7.1

Package Marking Information

XXXXXXXX
XXXXXNNN

YYWW

8-Lead PDIP (300 mil) (MCP6S91, MCP6S92)

Example:

8-Lead SOIC (150 mil) (MCP6S91, MCP6S92)

Example:

XXXXXXXX
XXXXYYWW

NNN

MCP6S91
E/P256

0424

MCP6S91

E/SN0424

256

8-Lead MSOP (MCP6S91, MCP6S92)

Example:

XXXXX

YWWNNN

6S91E

424256

Legend:

XX...X

Customer specific information*

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week `01')

NNN

Alphanumeric traceability code

Note:

In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office.

10-Lead MSOP (MCP6S93)

Example:

XXXXX

YWWNNN

6S93E

424256

2004 Microchip Technology Inc.

DS21908A-page 32

MCP6S91/2/3

8-Lead Plastic Dual In-line (P) 300 mil (PDIP)

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

MIN

NOM

MAX

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

.140

.155

.170

3.56

3.94

4.32

Molded Package Thickness

.115

.130

.145

2.92

3.30

3.68

Base to Seating Plane

.015

0.38

Shoulder to Shoulder Width

.300

.313

.325

7.62

7.94

8.26

Molded Package Width

.240

.250

.260

6.10

6.35

6.60

Overall Length

.360

.373

.385

9.14

9.46

9.78

Tip to Seating Plane

.125

.130

.135

3.18

3.30

3.43

Lead Thickness

.008

.012

.015

0.20

0.29

0.38

Upper Lead Width

.045

.058

.070

1.14

1.46

1.78

Lower Lead Width

.014

.018

.022

0.36

0.46

0.56

Overall Row Spacing

.310

.370

.430

7.87

9.40

10.92

Mold Draft Angle Top

Mold Draft Angle Bottom

* Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001
Drawing No. C04-018

.010" (0.254mm) per side.

§ Significant Characteristic

2004 Microchip Technology Inc.

DS21908A-page 33

MCP6S91/2/3

8-Lead Plastic Small Outline (SN) Narrow, 150 mil (SOIC)

Foot Angle

Mold Draft Angle Bottom

Mold Draft Angle Top

0.51

0.42

0.33

.020

.017

.013

Lead Width

0.25

0.23

0.20

.010

.009

.008

Lead Thickness

0.76

0.62

0.48

.030

.025

.019

Foot Length

0.51

0.38

0.25

.020

.015

.010

Chamfer Distance

5.00

4.90

4.80

.197

.193

.189

Overall Length

3.99

3.91

3.71

.157

.154

.146

Molded Package Width

6.20

6.02

5.79

.244

.237

.228

Overall Width

0.25

0.18

0.10

.010

.007

.004

Standoff

1.55

1.42

1.32

.061

.056

.052

Molded Package Thickness

1.75

1.55

1.35

.069

.061

.053

Overall Height

1.27

.050

Pitch

Number of Pins

MAX

NOM

MIN

MAX

NOM

MIN

Dimension Limits

MILLIMETERS

INCHES*

Units

* Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010" (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

§ Significant Characteristic

2004 Microchip Technology Inc.

DS21908A-page 34

MCP6S91/2/3

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037

.035

Footprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.004

.010

.006

.012

(F)

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff §

Overall Width

Number of Pins

Pitch

.016

.114

.022

.118

.002

.030

.193

.034

MIN

Units

.026

NOM

INCHES

1.00

0.95

0.90

.039

0.15

0.30

.008

.016

0.10

0.25

0.20

0.40

MILLIMETERS*

0.65

0.86

3.00

0.55

4.90

.044

.122

.028

.122

.038

.006

0.40

2.90

0.05

0.76

MIN

MAX

NOM

1.18

0.70

3.10

0.15

0.97

MAX

§ Significant Characteristic

.184

.200

4.67

.5.08

2004 Microchip Technology Inc.

DS21908A-page 35

MCP6S91/2/3

10-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REF

Footprint

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-021

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.006

.009

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016

.024

.118 BSC

.000

.030

.193 BSC

.033

MIN

Units

.020 TYP

NOM

INCHES

0.95 REF

0.23

.009

.012

0.08

0.15

0.23

0.30

MILLIMETERS*

0.50 TYP.

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX

NOM

1.10

0.80

0.15

0.95

MAX

5°

15°

5°

15°

0°

8°

5°

15°

JEDEC Equivalent: MO-187

8°

0°

(F)

2004 Microchip Technology Inc.

DS21908A-page 37

MCP6S91/2/3

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

Sales and Support

Device:

MCP6S91:

One-channel PGA

MCP6S91T: One-channel PGA

(Tape and Reel for SOIC and MSOP-8)

MCP6S92:

Two-channel PGA

MCP6S92T: Two-channel PGA

(Tape and Reel for SOIC and MSOP-8)

MCP6S93:

Two-channel PGA

MCP6S93T: Two-channel PGA

(Tape and Reel for MSOP-10)

Temperature Range:

= -40°C to +125°C

Package:

MS = Plastic Micro Small Outline (MSOP), 8-lead
P

= Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead
UN = Plastic Micro Small Outline (MSOP), 10-lead

Examples:

MCP6S91-E/P:

One-channel PGA,
PDIP package.

MCP6S91-E/SN:

One-channel PGA,
SOIC package.

MCP6S91-E/MS:

One-channel PGA,
MSOP package.

MCP6S92-E/MS:

Two-channel PGA,
MSOP-8 package.

MCP6S92T-E/MS: Tape and Reel,

Two-channel PGA,
MSOP-8 package.

MCP6S93-E/UN:

Two-channel PGA,
MSOP-10 package.

MCP6S93T-E/UN: Tape and Reel,

Two-channel PGA,
MSOP-10 package.

PART NO.

-X

/XX

Package

Temperature

Range

Device

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales office

The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

DS21908A-page 39

2004 Microchip Technology Inc.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip's products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

, micro

, MPLAB, PIC, PICmicro,

PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company's quality system processes and
procedures are for its PICmicro

8-bit MCUs, K

code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip's quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS21908A-page 40

2004 Microchip Technology Inc.

AMERICAS

Corporate Office
2355 West Chandler Blvd.
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
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Web Address:
www.microchip.com

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Tel: 852-2401-1200
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China - Shanghai
Tel: 86-21-5407-5533
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ASIA/PACIFIC

India - Bangalore
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India - New Delhi
Tel: 91-11-5160-8632
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Japan - Kanagawa
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EUROPE

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Italy - Milan
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Netherlands - Drunen
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Fax: 31-416-690340

England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820

ORLDWIDE

ALES

AND

ERVICE

09/27/04

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Document Outline

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Document Outline

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