2003 Microchip Technology Inc.
DS21749D-page 1
93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
Device Selection Table
Features
Low-power CMOS technology
ORG pin to select word size for `46C version
128 x 8-bit organization `A' ver. devices (no ORG)
64 x 16-bit organization `B' ver. devices (no ORG)
Self-timed ERASE/WRITE cycles (including
auto-erase)
Automatic ERAL before WRAL
Power-on/off data protection circuitry
Industry standard 3-wire serial I/O
Device Status signal (READY/BUSY)
Sequential READ function
1,000,000 E/W cycles
Data retention > 200 years
Temperature ranges supported
Pin Function Table
Description
The Microchip Technology Inc. 93XX46A/B/C devices
are 1K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
Package Types (not to scale)
Part Number
V
CC
Range
ORG Pin
Word Size
Temp Ranges
Packages
93AA46A
1.8-5.5
No
8-bit
I
P, SN, ST, MS, OT
93AA46B
1.8-5-5
No
16-bit
I
P, SN, ST, MS, OT
93LC46A
2.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT
93LC46B
2.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT
93C46A
4.5-5.5
No
8-bit
I, E
P, SN, ST, MS, OT
93C46B
4.5-5.5
No
16-bit
I, E
P, SN, ST, MS, OT
93AA46C
1.8-5.5
Yes
8 or 16-bit
I
P, SN, ST, MS
93LC46C
2.5-5.5
Yes
8 or 16-bit
I, E
P, SN, ST, MS
93C46C
4.5-5.5
Yes
8 or 16-bit
I, E
P, SN, ST, MS
- Industrial (I)
-40C to
+85C
- Automotive (E)
-40C to +125C
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
V
SS
Ground
NC
No internal connection
ORG
Memory Configuration
V
CC
Power Supply
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
PDIP/SOIC
(P, SN)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
ROTATED SOIC
(ex: 93LC46BX)
TSSOP/MSOP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
(ST, MS)
SOT-23
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
(OT)
* ORG pin is NC on A/B devices
1K Microwire Compatible Serial EEPROM
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS21749D-page 2
2003 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
()
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied ................................................................................................-40C to +125C
ESD protection on all pins
......................................................................................................................................................
4 kV
TABLE 1-1:
DC CHARACTERISTICS
NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
All parameters apply over the specified ranges
unless otherwise noted.
V
CC
= range by device (see Table on Page 1)
Industrial (I):
T
A
= -40C to +85C
Automotive (E): T
A
= -40C to +125C
Param. No. Symbol
Parameter
Min
Typ
Max
Units
Conditions
D1
V
IH
1
V
IH
2
High-level input voltage
2.0
0.7 V
CC
--
--
V
CC
+1
V
CC
+1
V
V
V
CC
2.7V
V
CC
<
2.7V
D2
V
IL
1
V
IL
2
Low-level input voltage
-0.3
-0.3
--
--
0.8
0.2 V
CC
V
V
V
CC
2.7V
V
CC
<
2.7V
D3
V
OL
1
V
OL
2
Low-level output voltage
--
--
--
--
0.4
0.2
V
V
I
OL
= 2.1 mA, V
CC
= 4.5V
I
OL
= 100
A, V
CC
= 2.5V
D4
V
OH
1
V
OH
2
High-level output voltage
2.4
V
CC
- 0.2
--
--
--
--
V
V
I
OH
= -400
A, V
CC
= 4.5V
I
OH
= -100
A, V
CC
= 2.5V
D5
I
LI
Input leakage current
--
--
1
A
V
IN
= V
SS
to V
CC
D6
I
LO
Output leakage current
--
--
1
A
V
OUT
= V
SS
to V
CC
D7
C
IN
,
C
OUT
Pin capacitance
(all inputs/outputs)
--
--
7
pF
V
IN
/V
OUT
= 0V (Note 1)
T
A
= 25C, F
CLK
= 1 MHz
D8
I
CC
write
Write current
--
--
--
500
2
--
mA
A
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 2.5V
D9
I
CC
read Read current
--
--
--
--
--
100
1
500
--
mA
A
A
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 3.0V
F
CLK
= 2 MHz, V
CC
= 2.5V
D10
I
CCS
Standby current
--
--
--
--
1
5
A
A
I-Temp
E-Temp
CLK = CS = 0V
ORG = DI = V
SS
or V
CC
(Note 2) (N
OTE
3)
D11
V
POR
V
CC
voltage detect
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
--
--
1.5V
3.8V
--
--
V
V
(Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on `A' or `B' versions.
3: READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".
2003 Microchip Technology Inc.
DS21749D-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
TABLE 1-2:
AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
V
CC
= range by device (see Table on Page 1)
Industrial (I):
T
A
= -40C to +85C
Automotive (E): T
A
= -40C to +125C
Param. No. Symbol
Parameter
Min
Max
Units
Conditions
A1
F
CLK
Clock frequency
--
3
2
1
MHz
MHz
MHz
4.5V
V
CC
<
5.5V, 93XX46C only
2.5V
V
CC
<
5.5V
1.8V
V
CC
<
2.5V
A2
T
CKH
Clock high time
200
250
450
--
ns
ns
ns
4.5V
V
CC
<
5.5V, 93XX46C only
2.5V
V
CC
<
5.5V
1.8V
V
CC
<
2.5V
A3
T
CKL
Clock low time
100
200
450
--
ns
ns
ns
4.5V
V
CC
<
5.5V, 93XX46C only
2.5V
V
CC
<
5.5V
1.8V
V
CC
<
2.5V
A4
T
CSS
Chip Select setup time
50
100
250
--
ns
ns
ns
4.5V
V
CC
<
5.5V
2.5V
V
CC
<
4.5V
1.8V
V
CC
<
2.5V
A5
T
CSH
Chip Select hold time
0
--
ns
1.8V
V
CC
<
5.5V
A6
T
CSL
Chip Select low time
250
--
ns
1.8V
V
CC
<
5.5V
A7
T
DIS
Data input setup time
50
100
250
--
ns
4.5V
V
CC
<
5.5V, 93XX46C only
2.5V
V
CC
<
5.5V
1.8V
V
CC
<
2.5V
A8
T
DIH
Data input hold time
50
100
250
--
ns
4.5V
V
CC
<
5.5V, 93XX46C only
2.5V
V
CC
<
5.5V
1.8V
V
CC
<
2.5V
A9
T
PD
Data output delay time
--
--
--
200
250
400
ns
4.5V
V
CC
<
5.5V, C
L
= 100 pF
2.5V
V
CC
<
4.5V, C
L
= 100 pF
1.8V
V
CC
<
2.5V, C
L
= 100 pF
A10
T
CZ
Data output disable time
--
--
100
200
ns
4.5V
V
CC
<
5.5V, (Note 1)
1.8V
V
CC
<
4.5V, (Note 1)
A11
T
SV
Status valid time
--
200
300
500
ns
4.5V
V
CC
<
5.5V, C
L
= 100 pF
2.5V
V
CC
<
4.5V, C
L
= 100 pF
1.8V
V
CC
<
2.5V, C
L
= 100 pF
A12
T
WC
Program cycle time
--
6
ms
Erase/Write mode (AA and LC
versions)
A13
T
WC
--
2
ms
Erase/Write mode (93C versions)
A14
T
EC
--
6
ms
ERAL mode, 4.5V
V
CC
5.5V
A15
T
WL
--
15
ms
WRAL mode, 4.5V
V
CC
5.5V
A16
--
Endurance
1M
--
cycles
25C, V
CC
= 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total EnduranceTM Model which may be obtained from www.microchip.com.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS21749D-page 4
2003 Microchip Technology Inc.
FIGURE 1-1:
SYNCHRONOUS DATA TIMING
TABLE 1-3:
INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
TABLE 1-4:
INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A5
A4
A3
A2
A1
A0
--
(RDY/BSY)
9
ERAL
1
00
1
0
X
X
X
X
--
(RDY/BSY)
9
EWDS
1
00
0
0
X
X
X
X
--
HIGH-Z
9
EWEN
1
00
1
1
X
X
X
X
--
HIGH-Z
9
READ
1
10
A5
A4
A3
A2
A1
A0
--
D15 - D0
25
WRITE
1
01
A5
A4
A3
A2
A1
A0
D15 - D0
(RDY/BSY)
25
WRAL
1
00
0
1
X
X
X
X
D15 - D0
(RDY/BSY)
25
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A6
A5
A4
A3
A2
A1
A0
--
(RDY/BSY)
10
ERAL
1
00
1
0
X
X
X
X
X
--
(RDY/BSY)
10
EWDS
1
00
0
0
X
X
X
X
X
--
HIGH-Z
10
EWEN
1
00
1
1
X
X
X
X
X
--
HIGH-Z
10
READ
1
10
A6
A5
A4
A3
A2
A1
A0
--
D7 - D0
18
WRITE
1
01
A6
A5
A4
A3
A2
A1
A0
D7 - D0
(RDY/BSY)
18
WRAL
1
00
0
1
X
X
X
X
X
D7 - D0
(RDY/BSY)
18
CS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
CLK
DI
DO
(READ)
DO
(PROGRAM)
T
CSS
T
DIS
T
CKH
T
CKL
T
DIH
T
PD
T
CSH
T
PD
T
CZ
STATUS VALID
T
SV
T
CZ
Note:
T
SV
is relative to CS.
2003 Microchip Technology Inc.
DS21749D-page 5
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0
FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to V
CC
, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a "bus conflict" to occur during the "dummy zero"
that precedes the READ operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
Data Protection
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an
EWEN
instruction must be
performed before the initial
ERASE
or
WRITE
instruction
can be executed.
Block Diagram
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
V
CC
V
SS
*ORG input is not available on A/B devices
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