1997 Microchip Technology Inc.
DS11168L-page 1
M
93LC46/56/66
FEATURES
Single supply with programming operation down
to 2.0V (Commercial only)
Low power CMOS technology
- 1 mA active current typical
- 5
A standby current (typical) at 3.0V
ORG pin selectable memory configuration
- 128 x 8 or 64 x 16-bit organization (93LC46)
- 256 x 8 or 128 x 16-bit organization(93LC56)
- 512 x 8 or 256 x 16-bit organization(93LC66)
Self-timed ERASE and WRITE cycles
(including auto-erase)
Automatic ERAL before WRAL
Power on/off data protection circuitry
Industry standard 3-wire serial I/O
Device status signal during ERASE/WRITE cycles
Sequential READ function
10,000,000 ERASE/WRITE cycles guaranteed on
93LC56 and 93LC66
1,000,000 E/W cycles guaranteed on 93LC46
Data retention > 200 years
8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
Temperature ranges supported
BLOCK DIAGRAM
DESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K, and 4K low-voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits, depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for
low-power, nonvolatile memory applications. The
93LC46/56/66 is available in standard 8-pin DIP and 8/
14-pin surface mount SOIC packages. The 93LC46X/
56X/66X are only offered in an "SN" package.
PACKAGE TYPES
- Commercial (C):
0
C to
+70
C
- Industrial (I):
-40
C to
+85
C
MEMORY
ARRAY
ADDRESS
DECODER
V
CC
V
SS
DATA REGISTER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DI
CS
CLK
ADDRESS
COUNTER
DIP
SOIC
93LC46
93LC56
93LC66
93LC46
93LC56
93LC66
93LC46X
93LC56X
93LC66X
93LC56
93LC66
SOIC
SOIC
CS
CLK
DI
DO
V
CC
NU
ORG
V
SS
NU
V
CC
CS
CLK
ORG
V
SS
DO
DI
CS
CLK
DI
DO
V
CC
NU
ORG
V
SS
NC
CS
CLK
NC
NC
Vcc
NU
NC
DI
DO
NC
ORG
V
SS
NC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
14
13
12
11
5
6
7
10
9
8
1K/2K/4K 2.0V Microwire
Serial EEPROM
93LC46/56/66
DS11168L-page 2
1997 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65C to +150C
Ambient temp. with power applied................. -65C to +125C
Soldering temperature of leads (10 seconds) ............. +300C
ESD protection on all pins................................................ 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
PIN function Table
TABLE 1-1
DC AND AC ELECTRICAL CHARACTERISTICS
Name
Function
CS
Chip Select
CLK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
V
SS
Ground
ORG
Memory Configuration
NU
Not Utilized
NC
No Connect
V
CC
Power Supply
Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0C to +70C
Industrial (I):
Vcc = +2.5V to +6.0V (I): Tamb = -40C to +85C
Parameter
Symbol
Min.
Max.
Units
Conditions
High level input voltage
V
IH1
2.0
Vcc +1
V
V
CC
2.7V
V
IH2
0.7 Vcc
Vcc +1
V
V
CC
< 2.7V
Low level input voltage
V
IL1
-0.3
0.8
V
V
CC
2.7V
V
IL2
-0.3
0.2 Vcc
V
V
CC
< 2.7V
Low level output voltage
V
OL1
--
0.4
V
I
OL
= 2.1 mA; Vcc = 4.5V
V
OL2
--
0.2
V
I
OL
=100
A; Vcc = Vcc Min.
High level output voltage
V
OH1
2.4
--
V
I
OH
= -400
A; Vcc = 4.5V
V
OH2
Vcc-0.2
--
V
I
OH
= -100
A; Vcc = Vcc Min.
Input leakage current
I
LI
-10
10
A
V
IN
= 0.1V to Vcc
Output leakage current
I
LO
-10
10
A
V
OUT
= 0.1V to Vcc
Pin capacitance
(all inputs/outputs)
C
IN
, C
OUT
--
7
pF
V
IN
/V
OUT
= 0 V (Notes 1 & 3)
Tamb = +25
C, F
CLK
= 1 MHz
Operating current
I
CC
read
--
1
500
mA
A
F
CLK
= 2 MHz; Vcc = 6.0V
F
CLK
= 1 MHz; Vcc = 3.0V
I
CC
write
--
3
mA
F
CLK
= 2 MHz; Vcc = 6.0V (Note 3)
Standby current
I
CCS
--
100
30
A
A
CLK = CS = 0V; Vcc = 6.0V
CLK = CS = 0V; Vcc = 3.0V
Clock frequency
F
CLK
--
2
1
MHz
MHz
Vcc
4.5V
Vcc < 4.5V
Clock high time
T
CKH
250
--
ns
Clock low time
T
CKL
250
--
ns
Chip select setup time
T
CSS
50
--
ns
Relative to CLK
Chip select hold time
T
CSH
0
--
ns
Relative to CLK
Chip select low time
T
CSL
250
--
ns
Data input setup time
T
DIS
100
--
ns
Relative to CLK
Data input hold time
T
DIH
100
--
ns
Relative to CLK
Data output delay time
T
PD
--
400
ns
C
L
= 100 pF
Data output disable time
T
CZ
--
100
ns
C
L
= 100 pF (Note 3)
Status valid time
T
SV
--
500
ns
C
L
= 100 pF
Program cycle time
T
WC
--
10
ms
ERASE/WRITE mode (Note 2)
T
EC
--
15
ms
ERAL mode
T
WL
--
30
ms
WRAL mode
Endurance
93LC46
93LC56/66
--
--
1M
10M
--
--
cycles
25
C, Vcc = 5.0V, Block Mode (Note 4)
Note 1:
This parameter is tested at Tamb = 25C and F
CLK
= 1 MHz.
2: Typical program cycle time is 4 ms per word.
3: This parameter is periodically sampled and not 100% tested.
4: This application is not tested but guaranteed by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on our BBS or website.
93LC46/56/66
1997 Microchip Technology Inc.
DS11168L-page 3
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
CKH
) and
clock low time (T
CKL
). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a "Don't Care" if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table
2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
2.3
Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4
Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (T
PD
after the posi-
tive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (T
CSL
) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
2.5
Organization (ORG)
When ORG is tied to V
SS
, the (x8) memory organiza-
tion is selected. When ORG is connected to Vcc or
floated, the (x16) memory organization is selected.
ORG can only be floated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or V
SS
.
Note:
CS must go low between consecutive
instructions.
93LC46/56/66
DS11168L-page 4
1997 Microchip Technology Inc.
TABLE 2-1
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
TABLE 2-2
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
TABLE 2-3
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
TABLE 2-4
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
TABLE 2-5
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
TABLE 2-6
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A6 A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
10
ERAL
1
00
1 0 X X X X X
--
(RDY/BSY)
10
EWDS
1
00
0 0 X X X X X
--
HIGH-Z
10
EWEN
1
00
1 1 X X X X X
--
HIGH-Z
10
READ
1
10
A6 A5 A4 A3 A2 A1 A0
--
D7 - D0
18
WRITE
1
01
A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/BSY)
18
WRAL
1
00
0 1 X X X X X
D7 - D0
(RDY/BSY)
18
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
9
ERAL
1
00
1 0 X X X X
--
(RDY/BSY)
9
EWDS
1
00
0 0 X X X X
--
HIGH-Z
9
EWEN
1
00
1 1 X X X X
--
HIGH-Z
9
READ
1
10
A5 A4 A3 A2 A1 A0
--
D15 - D0
25
WRITE
1
01
A5 A4 A3 A2 A1 A0
D15 - D0
(RDY/BSY)
25
WRAL
1
00
0 1 X X X X
D15 - D0
(RDY/BSY)
25
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
X A7 A6 A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
12
ERAL
1
00
1 0 X X X X X X X
--
(RDY/BSY)
12
EWDS
1
00
0 0 X X X X X X X
--
HIGH-Z
12
EWEN
1
00
1 1 X X X X X X X
--
HIGH-Z
12
READ
1
10
X A7 A6 A5 A4 A3 A2 A1 A0
--
D7 - D0
20
WRITE
1
01
X A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/BSY)
20
WRAL
1
00
0 1 X X X X X X X
D7 - D0
(RDY/BSY)
20
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
X A6 A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
11
ERAL
1
00
1 0 X X X X X X
--
(RDY/BSY)
11
EWDS
1
00
0 0 X X X X X X
--
HIGH-Z
11
EWEN
1
00
1 1 X X X X X X
--
HIGH-Z
11
READ
1
10
X A6 A5 A4 A3 A2 A1 A0
--
D15 - D0
27
WRITE
1
01
X A6 A5 A4 A3 A2 A1 A0
D15 - D0
(RDY/BSY)
27
WRAL
1
00
0 1 X X X X X X
D15 - D0
(RDY/BSY)
27
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
ERASE
1
11
A8 A7 A6 A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
12
ERAL
1
00
1 0 X X X X X X X
--
(RDY/BSY)
12
EWDS
1
00
0 0 X X X X X X X
--
HIGH-Z
12
EWEN
1
00
1 1 X X X X X X X
--
HIGH-Z
12
READ
1
10
A8 A7 A6 A5 A4 A3 A2 A1 A0
--
D7 - D0
20
WRITE
1
01
A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
(RDY/BSY)
20
WRAL
1
00
0 1 X X X X X X X
D7 - D0
(RDY/BSY)
20
Instruction
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
READ
1
10
A7 A6 A5 A4 A3 A2 A1 A0
--
D15 - D0
27
EWEN
1
00
1 1 X X X X X X
--
High-Z
11
ERASE
1
11
A7 A6 A5 A4 A3 A2 A1 A0
--
(RDY/BSY)
11
ERAL
1
00
1 0 X X X X X X
--
(RDY/BSY)
11
WRITE
1
01
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
(RDY/BSY)
27
WRAL
1
00
0 1 X X X X X X
D15 - D0
(RDY/BSY)
27
EWDS
1
00
0 0 X X X X X X
--
High-Z
11
93LC46/56/66
1997 Microchip Technology Inc.
DS11168L-page 5
3.0
FUNCTIONAL DESCRIPTION
When it is connected to ground, the (x8) organization is
selected. When the ORG pin is connected to Vcc, the
(x16) organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a HIGH-Z state, except when reading data from the
device or when checking the READY/BUSY status dur-
ing a programming operation. The READY/BUSY
status can be verified during an ERASE/WRITE opera-
tion by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the HIGH-Z state
on the falling edge of the CS.
3.1
START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcodes,
addresses, and data bits for any particular instruction is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
3.2
Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a "bus conflict"
to occur during the "dummy zero" that precedes the
READ operation. Under such a condition the voltage
level seen at DO is undefined and will depend upon the
relative impedances of Data Out, and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the DO pin.
3.3
Data Protection
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 1.4V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
CLK
STATUS VALID
V
IH
V
IL
CS
T
CSS
T
DIS
T
DIH
T
SV
T
CSH
T
CKH
T
CKL
T
PD
T
CZ
T
CZ
T
PD
V
IH
V
IL
DI
V
IH
V
IL
DO
(READ)
V
OH
V
OL
DO
(PROGRAM)
V
OH
V
OL
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