Document Outline

• High Performance RISC CPU:
• Peripheral Features:
• Advanced Analog Features:
• CAN bus Module Features:
• Special Microcontroller Features:
• FLASH Technology:
• Pin Diagrams
• Table of Contents
• Most Current Data Sheet
• Errata
• Customer Notification System
• 1.0 Device Overview
  • TABLE 1-1: PIC18FXX8 Device Features
  • FIGURE 1-1: PIC18F248/258 Block Diagram
  • FIGURE 1-2: PIC18F448/458 Block diagram
  • TABLE 1-2: PIC18FXX8 Pinout I/O Descriptions
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration)
    • TABLE 2-1: Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
  • 2.3 RC Oscillator
    • FIGURE 2-2: RC Oscillator Mode
  • 2.4 External Clock Input
    • FIGURE 2-3: External Clock Input Operation (EC OSC Configuration)
    • FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
  • 2.5 HS4 (PLL)
    • FIGURE 2-5: PLL Block Diagram
  • 2.6 Oscillator Switching Feature
    • 2.6.1 System clock switch bit
      • FIGURE 2-6: Device Clock Sources
      • Register 2-1: OSCCON Register
    • 2.6.2 Oscillator Transitions
      • FIGURE 2-7: Timing Diagram For Transition From OSC1 to Timer1 Oscillator
      • FIGURE 2-8: Timing Diagram For Transition Between Timer1 and OSC1 (HS, XT, LP)
      • FIGURE 2-9: Timing For Transition Between Timer1 and OSC1 (HS with PLL)
      • FIGURE 2-10: Timing For Transition Between Timer1 and OSC1 (RC, EC)
  • 2.7 Effects of Sleep Mode on the OnChip Oscillator
  • 2.8 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Reset
  • FIGURE 3-1: Simplified Block Diagram of On-chip Reset Circuit
  • 3.1 Power-on Reset (POR)
  • 3.2 MCLR
    • FIGURE 3-2: Recommended MCLR Circuit
  • 3.3 Power-up Timer (PWRT)
  • 3.4 Oscillator Start-up Timer (OST)
  • 3.5 PLL Lock Time-out
  • 3.6 Brown-out Reset (BOR)
  • 3.7 Time-out Sequence
    • TABLE 3-1: Time-out in Various Situations
    • Register 3-1: RCON Register Bits and Positions
    • TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd Via RC Network)
    • FIGURE 3-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
    • FIGURE 3-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
    • FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd Via RC Network)
    • FIGURE 3-7: Time-out Sequence on POR w/ PLL Enabled (MCLR tied to Vdd Via RC Network)
    • TABLE 3-3: Initialization Conditions for All Registers 
• 4.0 Memory Organization
  • 4.1 Program Memory Organization
    • FIGURE 4-1: Program Memory Map and Stack for PIC18F258/458
    • 4.1.1 Internal Program Memory Operation
      • FIGURE 4-2: Program Memory Map and Stack for PIC18F248/448
  • 4.2 Return Address Stack
    • 4.2.1 Top-Of-Stack Access
    • 4.2.2 Return Stack Pointer (STKPTR)
      • Register 4-1: STKPTR - Stack Pointer Register
      • FIGURE 4-3: Return Address Stack and Associated Registers
    • 4.2.3 PUSH and POP instructions
    • 4.2.4 Stack Full/Underflow Resets
  • 4.3 Fast Register Stack
    • EXAMPLE 4-1: Fast Register Stack Code Example
  • 4.4 PCL, PCLATH and PCLATU
  • 4.5 Clocking Scheme/Instruction Cycle
    • FIGURE 4-4: Clock/Instruction Cycle
  • 4.6 Instruction Flow/Pipelining
  • 4.7 Instructions in Program Memory
    • EXAMPLE 4-2: Instruction Pipeline Flow
    • EXAMPLE 4-3: Instructions in Program memory
    • 4.7.1 Two-Word Instructions
  • 4.8 Lookup Tables
    • 4.8.1 Computed GOTO
    • 4.8.2 Table reads/Table writes
      • EXAMPLE 4-4: Two-Word Instructions
  • 4.9 Data Memory Organization
    • 4.9.1 General purpose Register File
    • 4.9.2 Special Function Registers
      • FIGURE 4-5: DATA MEMORY MAP FOR PIC18F248/448
      • FIGURE 4-6: Data Memory Map for PIC18F258/458
      • TABLE 4-1: Special Function Register Map
      • TABLE 4-2: Register File Summary
  • 4.10 Access Bank
  • 4.11 Bank Select Register (BSR)
    • FIGURE 4-7: Direct Addressing
  • 4.12 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 4-5: How to Clear RAM (Bank 1) Using Indirect Addressing
    • 4.12.1 Indirect Addressing Operation
      • FIGURE 4-8: Indirect Addressing
  • 4.13 STATUS Register
    • Register 4-2: STATUS Register
  • 4.14 RCON Register
    • Register 4-3: RCON Register
• 5.0 Data EEPROM Memory
  • 5.1 EEADR Register
  • 5.2 EECON1 and EECON2 Registers
    • Register 5-1: EECON1 Register
  • 5.3 Reading the Data EEPROM Memory
    • EXAMPLE 5-1: DATA EEPROM READ
  • 5.4 Writing to the Data EEPROM Memory
    • EXAMPLE 5-2: Data EEPROM Write
  • 5.5 Write Verify
  • 5.6 Protection Against Spurious Write
  • 5.7 Operation During Code Protect
  • 5.8 Using the Data EEPROM
    • EXAMPLE 5-3: DATA EEPROM REFRESH ROUTINE
    • TABLE 5-1: Registers Associated with DATA EEPROM Memory
• 6.0 FLASH Program Memory
  • 6.1 Table Reads and Table Writes
    • FIGURE 6-1: Table Read Operation
    • FIGURE 6-2: Table Write Operation
  • 6.2 Control Registers
    • 6.2.1 EECON1 AND EECON2 REGISTERS
      • Register 6-1: EECON1 Register
    • 6.2.2 TABLAT - Table Latch Register
    • 6.2.3 TBLPTR - Table Pointer Register
    • 6.2.4 TABLE POINTER BOUNDARIES
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions
      • FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
  • 6.3 Reading the FLASH Program Memory
    • FIGURE 6-4: Reads from FLASH Program Memory
    • EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
  • 6.4 Erasing FLASH Program memory
    • 6.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE
      • EXAMPLE 6-2: ERasing a FLASH PROGRAM MEMORY row
  • 6.5 Writing to FLASH Program Memory
    • 6.5.1 FLASH Program memory write sequence
      • FIGURE 6-5: TABLE WRITES to flash PROGRAM MEMORY
      • EXAMPLE 6-3: writing to FLASH PROGRAM MEMORY
      • EXAMPLE 6-3: writing to FLASH PROGRAM MEMORY (CONTINUED)
    • 6.5.2 Write verify
    • 6.5.3 unexpected termination of write operation
    • 6.5.4 protection against spurious writes
  • 6.6 FLASH Program Operation During Code Protection
    • TABLE 6-2: Registers Associated with program flash Memory
• 7.0 8 X 8 Hardware Multiplier
  • 7.1 Introduction
  • 7.2 Operation
    • EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 7-2: 8 x 8 Signed Multiply Routine
    • TABLE 7-1: Performance Comparison
    • EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 7-4: 16 x 16 Signed Multiply Routine
• 8.0 Interrupts
  • FIGURE 8-1: Interrupt Logic
  • 8.1 INTCON Registers
    • Register 8-1: INTCON Register
    • Register 8-2: INTCON2 Register
    • Register 8-3: INTCON3 Register
  • 8.2 PIR Registers
    • Register 8-4: Peripheral Interrupt Request (Flag) Register 1 (PIR1)
    • Register 8-5: Peripheral Interrupt Request (Flag) Register 2 (PIR2)
    • Register 8-6: Peripheral Interrupt Request (Flag) Register 3 (PIR3)
  • 8.3 PIE Registers
    • Register 8-7: Peripheral Interrupt Enable Register 1 (PIE1)
    • Register 8-8: Peripheral Interrupt Enable Register 2 (PIE2)
    • Register 8-9: Peripheral Interrupt Enable Register 3 (PIE3)
  • 8.4 IPR Registers
    • Register 8-10: Peripheral Interrupt Priority Register 1 (IPR1)
    • Register 8-11: Peripheral Interrupt Priority Register 2 (IPR2)
    • Register 8-12: Peripheral Interrupt Priority Register 3 (IPR3)
  • 8.5 RCON Register
    • Register 8-13: RCON Register
  • 8.6 INT Interrupts
  • 8.7 TMR0 Interrupt
  • 8.8 PORTB Interrupt-on-Change
  • 8.9 Context Saving During Interrupts
    • EXAMPLE 8-1: Saving STATUS, WREG and BSR Registers in RAM
• 9.0 I/O Ports
  • 9.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 9-1: Initializing PORTA
    • FIGURE 9-1: RA3:RA0 and RA5 Pins Block Diagram
    • FIGURE 9-2: RA4/T0CKI Pin Block Diagram
    • FIGURE 9-3: RA6/OSC2/CLKOUT PIN Block Diagram
    • TABLE 9-1: PORTA Functions
    • TABLE 9-2: Summary of Registers Associated with PORTA
  • 9.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 9-2: Initializing PORTB
    • FIGURE 9-4: RB7:RB4 Pins Block Diagram
    • FIGURE 9-5: RB1:RB0 Pins Block Diagram
    • FIGURE 9-6: RB2/CANTX Block Diagram
    • FIGURE 9-7: Block Diagram of RB3/CANRX Pin
    • TABLE 9-3: PORTB Functions
    • TABLE 9-4: Summary of Registers Associated with PORTB
  • 9.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 9-3: Initializing PORTC
    • FIGURE 9-8: PORTC Block Diagram (Peripheral Output Override)
    • TABLE 9-5: PORTC Functions
    • TABLE 9-6: Summary of Registers Associated with PORTC
  • 9.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 9-4: Initializing PORTD
    • FIGURE 9-9: PORTD Block Diagram in I/O Port Mode
    • TABLE 9-7: PORTD Functions
    • TABLE 9-8: Summary of Registers Associated with PORTD
  • 9.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 9-5: Initializing PORTE
    • FIGURE 9-10: PortE Block Diagram
    • Register 9-1: TRISE Register
    • TABLE 9-9: PORTE Functions
    • TABLE 9-10: Summary of Registers Associated with PORTE
• 10.0 Parallel Slave Port
  • FIGURE 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)
  • FIGURE 10-2: Parallel Slave Port Write Waveforms
  • FIGURE 10-3: Parallel Slave Port Read Waveforms
  • TABLE 10-1: Registers Associated with Parallel Slave Port
• 11.0 Timer0 Module
  • Register 11-1: T0CON Register
  • FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode
  • FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode
  • 11.1 Timer0 Operation
  • 11.2 Prescaler
    • 11.2.1 Switching Prescaler Assignment
  • 11.3 Timer0 Interrupt
  • 11.4 16-bit Mode Timer Reads and Writes
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode
  • 12.2 Timer1 Oscillator
    • TABLE 12-1: Capacitor Selection for the alternate Oscillator
  • 12.3 Timer1 Interrupt
  • 12.4 Resetting Timer1 Using a CCP Trigger Output
  • 12.5 Timer1 16-bit Read/Write Mode
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON Register
  • 13.2 Timer2 Interrupt
  • 13.3 Output of TMR2
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer3 Module
  • Register 14-1: T3CON Register
  • 14.1 Timer3 Operation
    • FIGURE 14-1: Timer3 Block Diagram
    • FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit Read/Write Mode
  • 14.2 Timer1 Oscillator
  • 14.3 Timer3 Interrupt
  • 14.4 Resetting Timer3 Using a CCP Trigger Output
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
• 15.0 Capture/Compare/PWM (CCP) Modules
  • Register 15-1: CCP1CON Register
  • 15.1 CCP1 Module
    • TABLE 15-1: CCP1 Mode - Timer Resource
  • 15.2 Capture Mode
    • 15.2.1 CCP pin Configuration
    • 15.2.2 Timer1/Timer3 Mode Selection
      • TABLE 15-2: Interaction of CCP1 AND ECCP1 Modules
    • 15.2.3 Software Interrupt
    • 15.2.4 CCP1 Prescaler
    • 15.2.5 CAN Message Time-Stamp
      • EXAMPLE 15-1: Changing Between Capture Prescalers
      • FIGURE 15-1: Capture Mode Operation Block Diagram
  • 15.3 Compare Mode
    • 15.3.1 CCP1 Pin Configuration
    • 15.3.2 timer1/Timer3 Mode Selection
    • 15.3.3 Software Interrupt Mode
    • 15.3.4 Special Event Trigger
      • FIGURE 15-2: Compare Mode Operation Block Diagram
      • TABLE 15-3: Registers associated with Capture, compare, Timer1 and Timer3
  • 15.4 PWM Mode
    • FIGURE 15-3: Simplified PWM Block Diagram
    • FIGURE 15-4: PWM Output
    • 15.4.1 PWM period
      • EQUATION 15-1:
    • 15.4.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
    • 15.4.3 SetUp for PWM Operation
      • TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz
      • TABLE 15-5: Registers associated with PWM and Timer2
• 16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
  • Register 16-1: ECCP1Con REGISTER
  • 16.1 ECCP1 Module
    • TABLE 16-1: ECCP1 Mode - Timer Resource
    • TABLE 16-2: Interaction of CCP1 AND ECCP1 Modules
    • TABLE 16-3: pin aSSIGNMENTS FOR vARIOUS eccp mODES
  • 16.2 Capture Mode
    • 16.2.1 CAN Message TIME-STAMP
  • 16.3 Compare Mode
    • 16.3.1 Special Event Trigger
      • TABLE 16-4: Registers Associated with Enhanced Capture, compare, Timer1 and Timer3
  • 16.4 Standard PWM Mode
  • 16.5 Enhanced PWM Mode
    • 16.5.1 PWM OUTPUT CONFIGURATIONS
      • FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module
      • FIGURE 16-2: PWM Output Relationships
    • 16.5.2 Half-Bridge mode
      • FIGURE 16-3: Half-Bridge PWM OUTPUT
      • FIGURE 16-4: EXAMPLES OF Half-Bridge OUTPUT MODE APPLICATIONS
    • 16.5.3 Full-Bridge Mode
      • FIGURE 16-5: Full-Bridge PWM OUTPUT
      • FIGURE 16-6: EXAMPLE OF Full-Bridge APPLICATION
      • FIGURE 16-7: PWM Direction Change
      • FIGURE 16-8: PWM Direction Change at Near 100% Duty Cycle
    • 16.5.4 PROGRAMMABLE DEADBAND DELAY
    • 16.5.5 System Implementation
    • 16.5.6 Start-up Considerations
    • 16.5.7 Output Polarity Configuration
      • Register 16-2: ECCP1DEL REGISTER
    • 16.5.8 SETUP FOR PWM OPERATION
      • TABLE 16-5: Registers Associated with Enhanced PWM and Timer2
  • 16.6 Enhanced CCP Auto-Shutdown
    • Register 16-3: ECCPAS: Enhanced CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN CONTROL REGISTER
• 17.0 Master Synchronous Serial Port (MSSP) Module
  • 17.1 Master SSP (MSSP) Module Overview
  • 17.2 Control Registers
  • 17.3 SPI Mode
  • 17.4 I2C Mode
• 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
  • 18.1 USART Baud Rate Generator (BRG)
  • 18.2 USART Asynchronous Mode
  • 18.3 USART Synchronous Master Mode
  • 18.4 USART Synchronous Slave Mode
• 19.0 CAN Module
  • 19.1 Overview
  • 19.2 CAN Module Registers
  • 19.3 CAN Modes of Operation
  • 19.4 CAN Message Transmission
  • 19.5 Message Reception
  • 19.6 Message Acceptance Filters and Masks
  • 19.7 Baud Rate Setting
  • 19.8 Synchronization
  • 19.9 Programming Time Segments
  • 19.10 Oscillator Tolerance
  • 19.11 Bit Timing Configuration Registers
  • 19.12 Error Detection
  • 19.13 CAN Interrupts
• 20.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module
  • 20.1 A/D Acquisition Requirements
  • 20.2 Selecting the A/D Conversion Clock
  • 20.3 Configuring Analog Port Pins
  • 20.4 A/D Conversions
  • 20.5 Use of the ECCP Trigger
• 21.0 Comparator Module
  • 21.1 Comparator Configuration
  • 21.2 Comparator Operation
  • 21.3 Comparator Reference
  • 21.4 Comparator Response Time
  • 21.5 Comparator Outputs
  • 21.6 Comparator Interrupts
  • 21.7 Comparator Operation During SLEEP
  • 21.8 Effects of a RESET
  • 21.9 Analog Input Connection Considerations
• 22.0 Comparator Voltage Reference Module
  • 22.1 Configuring the Comparator Voltage Reference
  • 22.2 Voltage Reference Accuracy/Error
  • 22.3 Operation During SLEEP
  • 22.4 Effects of a RESET
  • 22.5 Connection Considerations
• 23.0 Low Voltage Detect
  • 23.1 Control Register
  • 23.2 Operation
  • 23.3 Operation During SLEEP
  • 23.4 Effects of a RESET
• 24.0 Special Features of the CPU
  • 24.1 Configuration Bits
  • 24.2 Watchdog Timer (WDT)
  • 24.3 Power-down Mode (SLEEP)
  • 24.4 Program Verification and Code Protection
  • 24.5 ID Locations
  • 24.6 In-Circuit Serial Programming
  • 24.7 In-Circuit Debugger
  • 24.8 Low Voltage ICSP Programming
• 25.0 Instruction Set Summary
  • 25.1 READMODIFY-WRITE OPERATIONS
  • 25.2 Instruction Set
• 26.0 Development Support
  • 26.1 MPLAB Integrated Development Environment Software
  • 26.2 MPASM Assembler
  • 26.3 MPLAB C17 and MPLAB C18 C Compilers
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 26.5 MPLAB SIM Software Simulator
  • 26.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
  • 26.7 ICEPIC In-Circuit Emulator
  • 26.8 MPLAB ICD In-Circuit Debugger
  • 26.9 PRO MATE II Universal Device Programmer
  • 26.10 PICSTART Plus Entry Level Development Programmer
  • 26.11 PICDEM 1 Low Cost PICmicro Demonstration Board
  • 26.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
  • 26.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
  • 26.14 PICDEM 17 Demonstration Board
  • 26.15 KeeLoq Evaluation and Programming Tools
• 27.0 Electrical Characteristics
  • 27.1 DC Characteristics
  • 27.1 DC Characteristics (Continued)
  • 27.1 DC Characteristics (Continued)
  • 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
  • 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial) (Continued)
  • 27.3 AC (Timing) Characteristics
• 28.0 DC and AC Characteristics Graphs and Tables
• 29.0 Packaging Information
  • 29.1 Package Marking Information
  • 29.1 Package Marking Information (Continued)
  • 29.2 Package Details
• Appendix A: Data Sheet Revision History
• Appendix B: Device Differences
• Appendix C: Device Migrations
• Appendix D: Migrating from other PICmicro Devices
• Appendix E: Development Tool Version Requirements
• INDEX
• On-Line Support
• Reader Response
• PIC18FXX8 Product Identification System
• Worldwide Sales and Service