Document Outline

• High-Performance RISC CPU:
• Peripheral Features:
• Advanced Analog Features:
• CAN bus Module Features:
• Special Microcontroller Features:
• Flash Technology:
• Pin Diagrams
• Table of Contents
• 1.0 Device Overview
  • TABLE 1-1: PIC18FXX8 Device Features
  • FIGURE 1-1: PIC18F248/258 Block Diagram
  • FIGURE 1-2: PIC18F448/458 Block Diagram
  • TABLE 1-2: PIC18FXX8 Pinout I/O Descriptions
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (HS, XT or LP Osc Configuration)
    • TABLE 2-1: Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
  • 2.3 RC Oscillator
    • FIGURE 2-2: RC Oscillator Mode
  • 2.4 External Clock Input
    • FIGURE 2-3: External Clock Input Operation (EC Osc Configuration)
    • FIGURE 2-4: External Clock Input Operation (ECIO Configuration)
  • 2.5 HS4 (PLL)
    • FIGURE 2-5: PLL Block Diagram
  • 2.6 Oscillator Switching Feature
    • 2.6.1 System Clock Switch Bit
      • FIGURE 2-6: Device Clock Sources
      • Register 2-1: OSCCON: Oscillator Control Register
    • 2.6.2 Oscillator Transitions
      • FIGURE 2-7: Timing Diagram for Transition From OSC1 to Timer1 Oscillator
      • FIGURE 2-8: Timing Diagram for Transition Between Timer1 and OSC1 (HS, XT, LP)
      • FIGURE 2-9: Timing for Transition Between Timer1 and OSC1 (HS with PLL)
      • FIGURE 2-10: Timing for Transition Between Timer1 and OSC1 (RC, EC)
  • 2.7 Effects of Sleep Mode on the OnChip Oscillator
  • 2.8 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Reset
  • FIGURE 3-1: Simplified Block Diagram of On-Chip Reset Circuit
  • 3.1 Power-on Reset (POR)
  • 3.2 MCLR
    • FIGURE 3-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  • 3.3 Power-up Timer (PWRT)
  • 3.4 Oscillator Start-up Timer (OST)
  • 3.5 PLL Lock Time-out
  • 3.6 Brown-out Reset (BOR)
  • 3.7 Time-out Sequence
    • TABLE 3-1: Time-out in Various Situations
    • Register 3-1: RCON Register Bits and Positions
    • TABLE 3-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • FIGURE 3-3: Time-out Sequence on Power-up (MCLR Tied to Vdd)
    • FIGURE 3-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
    • FIGURE 3-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
    • FIGURE 3-6: Slow Rise Time (MCLR Tied to Vdd)
    • FIGURE 3-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)
    • TABLE 3-3: Initialization Conditions for All Registers
• 4.0 Memory Organization
  • 4.1 Program Memory Organization
    • FIGURE 4-1: Program Memory Map and Stack for PIC18F248/448
    • 4.1.1 Internal Program Memory Operation
      • FIGURE 4-2: Program Memory Map and Stack for PIC18F258/458
  • 4.2 Return Address Stack
    • 4.2.1 Top-of-Stack Access
    • 4.2.2 Return Stack Pointer (STKPTR)
      • Register 4-1: STKPTR: Stack Pointer Register
      • FIGURE 4-3: Return Address Stack and Associated Registers
    • 4.2.3 PUSH and POP Instructions
    • 4.2.4 Stack Full/Underflow Resets
  • 4.3 Fast Register Stack
    • EXAMPLE 4-1: Fast Register Stack Code Example
  • 4.4 PCL, PCLATH and PCLATU
  • 4.5 Clocking Scheme/Instruction Cycle
    • FIGURE 4-4: Clock/Instruction Cycle
  • 4.6 Instruction Flow/Pipelining
  • 4.7 Instructions in Program Memory
    • EXAMPLE 4-2: Instruction Pipeline Flow
    • EXAMPLE 4-3: Instructions in Program Memory
    • 4.7.1 Two-Word Instructions
  • 4.8 Look-up Tables
    • 4.8.1 Computed GOTO
    • 4.8.2 Table Reads/Table Writes
      • EXAMPLE 4-4: Two-Word Instructions
  • 4.9 Data Memory Organization
    • 4.9.1 General Purpose Register File
    • 4.9.2 Special Function Registers
      • FIGURE 4-5: Data Memory Map for PIC18F248/448
      • FIGURE 4-6: Data Memory Map for PIC18F258/458
      • TABLE 4-1: Special Function Register Map
      • TABLE 4-2: Register File Summary
  • 4.10 Access Bank
  • 4.11 Bank Select Register (BSR)
    • FIGURE 4-7: Direct Addressing
  • 4.12 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 4-5: How to Clear RAM (Bank 1) Using Indirect Addressing
    • 4.12.1 Indirect Addressing Operation
      • FIGURE 4-8: Indirect Addressing
  • 4.13 Status Register
    • Register 4-2: Status Register
  • 4.14 RCON Register
    • Register 4-3: RCON: Reset Control Register
• 5.0 Data EEPROM Memory
  • 5.1 EEADR Register
  • 5.2 EECON1 and EECON2 Registers
    • Register 5-1: EECON1: EEPROM Control Register 1
  • 5.3 Reading the Data EEPROM Memory
    • EXAMPLE 5-1: Data EEPROM Read
  • 5.4 Writing to the Data EEPROM Memory
    • EXAMPLE 5-2: Data EEPROM Write
  • 5.5 Write Verify
  • 5.6 Protection Against Spurious Write
  • 5.7 Operation During Code-Protect
  • 5.8 Using the Data EEPROM
    • EXAMPLE 5-3: Data EEPROM Refresh Routine
    • TABLE 5-1: Registers Associated with Data EEPROM Memory
• 6.0 Flash Program Memory
  • 6.1 Table Reads and Table Writes
    • FIGURE 6-1: Table Read Operation
    • FIGURE 6-2: Table Write Operation
  • 6.2 Control Registers
    • 6.2.1 EECON1 and EECON2 Registers
      • Register 6-1: EECON1: EEPROM Control Register 1
    • 6.2.2 TABLAT � Table Latch Register
    • 6.2.3 TBLPTR � Table Pointer Register
    • 6.2.4 Table Pointer Boundaries
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions
      • FIGURE 6-3: Table Pointer Boundaries Based on Operation
  • 6.3 Reading the Flash Program Memory
    • FIGURE 6-4: Reads From Flash Program Memory
    • EXAMPLE 6-1: Reading a Flash Program Memory Word
  • 6.4 Erasing Flash Program Memory
    • 6.4.1 Flash Program Memory Erase Sequence
      • EXAMPLE 6-2: Erasing a Flash Program Memory Row
  • 6.5 Writing to Flash Program Memory
    • 6.5.1 Flash Program Memory Write Sequence
      • FIGURE 6-5: Table Writes to Flash Program Memory
      • EXAMPLE 6-3: Writing to Flash Program Memory
      • EXAMPLE 6-3: Writing to Flash Program Memory (CONTINUED)
    • 6.5.2 Write Verify
    • 6.5.3 Unexpected Termination of Write Operation
    • 6.5.4 Protection Against Spurious Writes
  • 6.6 Flash Program Operation During Code Protection
    • TABLE 6-2: Registers Associated with Program Flash Memory
• 7.0 8 x 8 Hardware Multiplier
  • 7.1 Introduction
  • 7.2 Operation
    • EXAMPLE 7-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 7-2: 8 x 8 Signed Multiply Routine
    • TABLE 7-1: Performance Comparison
    • EQUATION 7-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 7-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 7-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 7-4: 16 x 16 Signed Multiply Routine
• 8.0 Interrupts
  • FIGURE 8-1: Interrupt Logic
  • 8.1 INTCON Registers
    • Register 8-1: INTCON: Interrupt Control Register
    • Register 8-2: INTCON2: Interrupt Control Register 2
    • Register 8-3: INTCON3: Interrupt Control Register 3
  • 8.2 PIR Registers
    • Register 8-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 8-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
    • Register 8-6: PIR3: Peripheral Interrupt Request (Flag) Register 3
  • 8.3 PIE Registers
    • Register 8-7: PIE1: Peripheral Interrupt Enable Register 1
    • Register 8-8: PIE2: Peripheral Interrupt Enable Register 2
    • Register 8-9: PIE3: Peripheral Interrupt Enable Register 3
  • 8.4 IPR Registers
    • Register 8-10: IPR1: Peripheral Interrupt Priority Register 1
    • Register 8-11: IPR2: Peripheral Interrupt Priority Register 2
    • Register 8-12: IPR3: Peripheral Interrupt Priority Register 3
  • 8.5 RCON Register
    • Register 8-13: RCON: Reset Control Register
  • 8.6 INT Interrupts
  • 8.7 TMR0 Interrupt
  • 8.8 PORTB Interrupt-on-Change
  • 8.9 Context Saving During Interrupts
    • EXAMPLE 8-1: Saving Status, WREG and BSR Registers in RAM
• 9.0 I/O Ports
  • 9.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 9-1: Initializing PORTA
    • FIGURE 9-1: RA3:RA0 and RA5 Pins Block Diagram
    • FIGURE 9-2: RA4/T0CKI Pin Block Diagram
    • FIGURE 9-3: OSC2/CLKO/RA6 Pin Block Diagram
    • TABLE 9-1: PORTA Functions
    • TABLE 9-2: Summary of Registers Associated with PORTA
  • 9.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 9-2: Initializing PORTB
    • FIGURE 9-4: RB7:RB4 Pins Block Diagram
    • FIGURE 9-5: RB1:RB0 Pins Block Diagram
    • FIGURE 9-6: RB2/CANTX/INT2 Pin Block Diagram
    • FIGURE 9-7: RB3/CANRX Pin Block Diagram
    • TABLE 9-3: PORTB Functions
    • TABLE 9-4: Summary of Registers Associated with PORTB
  • 9.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 9-3: Initializing PORTC
    • FIGURE 9-8: PORTC Block Diagram (Peripheral Output Override)
    • TABLE 9-5: PORTC Functions
    • TABLE 9-6: Summary of Registers Associated with PORTC
  • 9.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 9-4: Initializing PORTD
    • FIGURE 9-9: PORTD Block Diagram in I/O Port Mode
    • TABLE 9-7: PORTD Functions
    • TABLE 9-8: Summary of Registers Associated with PORTD
  • 9.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 9-5: Initializing PORTE
    • FIGURE 9-10: PortE Block Diagram
    • Register 9-1: TRISE Register
    • TABLE 9-9: PORTE Functions
    • TABLE 9-10: Summary of Registers Associated with PORTE
• 10.0 Parallel Slave Port
  • FIGURE 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port)
  • FIGURE 10-2: Parallel Slave Port Write Waveforms
  • FIGURE 10-3: Parallel Slave Port Read Waveforms
  • TABLE 10-1: Registers Associated with Parallel Slave Port
• 11.0 Timer0 Module
  • Register 11-1: T0CON: Timer0 Control Register
  • FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode
  • FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode
  • 11.1 Timer0 Operation
  • 11.2 Prescaler
    • 11.2.1 Switching Prescaler Assignment
  • 11.3 Timer0 Interrupt
  • 11.4 16-Bit Mode Timer Reads and Writes
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON: Timer1 Control Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode
  • 12.2 Timer1 Oscillator
    • TABLE 12-1: Capacitor Selection for the Alternate Oscillator
  • 12.3 Timer1 Interrupt
  • 12.4 Resetting Timer1 Using a CCP Trigger Output
  • 12.5 Timer1 16-Bit Read/Write Mode
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON: Timer2 Control Register
  • 13.2 Timer2 Interrupt
  • 13.3 Output of TMR2
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer3 Module
  • Register 14-1: T3CON:Timer3 Control Register
  • 14.1 Timer3 Operation
    • FIGURE 14-1: Timer3 Block Diagram
    • FIGURE 14-2: Timer3 Block Diagram Configured in 16-bit Read/Write Mode
  • 14.2 Timer1 Oscillator
  • 14.3 Timer3 Interrupt
  • 14.4 Resetting Timer3 Using a CCP Trigger Output
    • TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
• 15.0 Capture/Compare/PWM (CCP) Modules
  • Register 15-1: CCP1CON: CCP1 Control Register
  • 15.1 CCP1 Module
    • TABLE 15-1: CCP1 Mode � Timer Resource
  • 15.2 Capture Mode
    • 15.2.1 CCP Pin Configuration
    • 15.2.2 Timer1/Timer3 Mode Selection
      • TABLE 15-2: Interaction of CCP1 and ECCP1 Modules
    • 15.2.3 Software Interrupt
    • 15.2.4 CCP1 Prescaler
    • 15.2.5 CAN Message Time-Stamp
      • EXAMPLE 15-1: Changing Between Capture Prescalers
      • FIGURE 15-1: Capture Mode Operation Block Diagram
  • 15.3 Compare Mode
    • 15.3.1 CCP1 Pin Configuration
    • 15.3.2 Timer1/Timer3 Mode Selection
    • 15.3.3 Software Interrupt Mode
    • 15.3.4 Special Event Trigger
      • FIGURE 15-2: Compare Mode Operation Block Diagram
      • TABLE 15-3: Registers Associated with Capture, Compare, Timer1 and Timer3
  • 15.4 PWM Mode
    • FIGURE 15-3: Simplified PWM Block Diagram
    • FIGURE 15-4: PWM Output
    • 15.4.1 PWM Period
      • EQUATION 15-1:
    • 15.4.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
    • 15.4.3 Setup for PWM Operation
      • TABLE 15-4: Example PWM Frequencies and Resolutions at 40 MHz
      • TABLE 15-5: Registers Associated with PWM and Timer2
• 16.0 Enhanced Capture/ Compare/PWM (ECCP) Module
  • Register 16-1: ECCP1Con: ECCP1 Control Register
  • 16.1 ECCP1 Module
    • TABLE 16-1: ECCP1 Mode � Timer Resource
    • TABLE 16-2: Interaction of CCP1 and ECCP1 Modules
    • TABLE 16-3: Pin Assignments for Various ECCP Modes
  • 16.2 Capture Mode
    • 16.2.1 CAN Message TIME-STAMP
  • 16.3 Compare Mode
    • 16.3.1 Special Event Trigger
      • TABLE 16-4: Registers Associated with Enhanced Capture, Compare, Timer1 and Timer3
  • 16.4 Standard PWM Mode
  • 16.5 Enhanced PWM Mode
    • 16.5.1 PWM Output Configurations
      • FIGURE 16-1: Simplified Block Diagram of the Enhanced PWM Module
      • FIGURE 16-2: PWM Output Relationships
    • 16.5.2 Half-Bridge Mode
      • FIGURE 16-3: Half-Bridge PWM Output
      • FIGURE 16-4: Examples of Half-Bridge Output Mode Applications
    • 16.5.3 Full-Bridge Mode
      • FIGURE 16-5: Full-Bridge PWM Output
      • FIGURE 16-6: Example of Full-Bridge Application
      • FIGURE 16-7: PWM Direction Change
      • FIGURE 16-8: PWM Direction Change at Near 100% Duty Cycle
    • 16.5.4 Programmable Dead-Band Delay
    • 16.5.5 System Implementation
    • 16.5.6 Start-up Considerations
    • 16.5.7 Output Polarity Configuration
      • Register 16-2: ECCP1DEL: PWM Delay Register
    • 16.5.8 Setup for PWM Operation
      • TABLE 16-5: Registers Associated with Enhanced PWM and Timer2
  • 16.6 Enhanced CCP Auto-Shutdown
    • Register 16-3: ECCPAS: Enhanced Capture/Compare/PWM Auto-Shutdown Control Register
• 17.0 Master Synchronous Serial Port (MSSP) Module
  • 17.1 Master SSP (MSSP) Module Overview
  • 17.2 Control Registers
  • 17.3 SPI Mode
    • FIGURE 17-1: MSSP Block Diagram (SPI�Mode)
    • 17.3.1 Registers
      • Register 17-1: SSPSTAT: MSSP Status Register (SPI Mode)
      • Register 17-2: SSPCON1: MSSP Control Register 1 (SPI Mode)
    • 17.3.2 Operation
      • EXAMPLE 17-1: Loading the SSPBUF (SSPSR) Register
    • 17.3.3 Enabling SPI I/O
    • 17.3.4 Typical Connection
      • FIGURE 17-2: SPI� Master/Slave Connection
    • 17.3.5 Master Mode
      • FIGURE 17-3: SPI� Mode Waveform (Master Mode)
    • 17.3.6 Slave Mode
    • 17.3.7 Slave Select Synchronization
      • FIGURE 17-4: Slave Synchronization Waveform
      • FIGURE 17-5: SPI� Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 17-6: SPI� Mode Waveform (Slave Mode with CKE = 1)
    • 17.3.8 Sleep Operation
    • 17.3.9 Effects of a Reset
    • 17.3.10 Bus Mode Compatibility
      • TABLE 17-1: SPI� Bus Modes
      • TABLE 17-2: Registers Associated with SPI� Operation
  • 17.4 I2C Mode
    • FIGURE 17-7: MSSP Block Diagram (I2C� Mode)
    • 17.4.1 Registers
      • Register 17-3: SSPSTAT: MSSP Status Register (I2C Mode)
      • Register 17-4: SSPCON1: MSSP Control Register 1 (I2C Mode)
      • Register 17-5: SSPCON2: MSSP Control Register 2 (I2C Mode)
    • 17.4.2 Operation
    • 17.4.3 Slave Mode
      • FIGURE 17-8: I2C� Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)
      • FIGURE 17-9: I2C� Slave Mode Timing (Transmission, 7-bit Address)
      • FIGURE 17-10: I2C� Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)
      • FIGURE 17-11: I2C� Slave Mode Timing (Transmission, 10-bit Address)
    • 17.4.4 Clock Stretching
      • FIGURE 17-12: Clock Synchronization Timing
      • FIGURE 17-13: I2C� Slave Mode Timing with SEN = 1 (Reception, 7-bit Address)
      • FIGURE 17-14: I2C� Slave Mode Timing with SEN = 1 (Reception, 10-bit Address)
    • 17.4.5 General Call Address Support
      • FIGURE 17-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)
    • 17.4.6 Master Mode
      • FIGURE 17-16: MSSP Block Diagram (I2C� Master Mode)
    • 17.4.7 Baud Rate Generator
      • FIGURE 17-17: Baud Rate Generator Block Diagram
      • TABLE 17-3: I2C� Clock Rate w/BRG
      • FIGURE 17-18: Baud Rate Generator Timing with Clock Arbitration
    • 17.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 17-19: First Start Bit Timing
    • 17.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 17-20: Repeated Start Condition Waveform
    • 17.4.10 I2C Master Mode Transmission
    • 17.4.11 I2C Master Mode Reception
      • FIGURE 17-21: I2C� Master Mode Waveform (Transmission, 7 or 10-bit Address)
      • FIGURE 17-22: I2C� Master Mode Waveform (Reception, 7-bit Address)
    • 17.4.12 Acknowledge Sequence Timing
    • 17.4.13 Stop Condition Timing
      • FIGURE 17-23: Acknowledge Sequence Waveform
      • FIGURE 17-24: Stop Condition Receive or Transmit Mode
    • 17.4.14 Sleep Operation
    • 17.4.15 Effect of a Reset
    • 17.4.16 Multi-Master Mode
    • 17.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 17-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 17-26: Bus Collision During Start Condition (SDA Only)
      • FIGURE 17-27: Bus Collision During Start Condition (SCL = 0)
      • FIGURE 17-28: BRG Reset Due to SDA Arbitration During Start Condition
      • FIGURE 17-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 17-30: Bus Collision During a Repeated Start Condition (Case 2)
      • FIGURE 17-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 17-32: Bus Collision During a Stop Condition (Case 2)
• 18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
  • Register 18-1: TXSTA: Transmit Status and Control Register
  • Register 18-2: RCSTA: Receive Status and Control Register
  • 18.1 USART Baud Rate Generator (BRG)
    • 18.1.1 Sampling
      • EXAMPLE 18-1: Calculating Baud Rate Error
      • TABLE 18-1: Baud Rate Formula
      • TABLE 18-2: Registers Associated with Baud Rate Generator
      • TABLE 18-3: Baud Rates for Synchronous Mode
      • TABLE 18-4: Baud Rates for Asynchronous Mode (BRGH = 0)
      • TABLE 18-5: Baud Rates for Asynchronous Mode (BRGH = 1)
  • 18.2 USART Asynchronous Mode
    • 18.2.1 USART Asynchronous Transmitter
      • FIGURE 18-1: USART Transmit Block Diagram
      • FIGURE 18-2: Asynchronous Transmission
      • FIGURE 18-3: Asynchronous Transmission (Back to Back)
      • TABLE 18-6: Registers Associated with Asynchronous Transmission
    • 18.2.2 USART Asynchronous Receiver
    • 18.2.3 Setting Up 9-bit Mode with Address Detect
      • FIGURE 18-4: USART Receive Block Diagram
      • FIGURE 18-5: Asynchronous Reception
      • TABLE 18-7: Registers Associated with Asynchronous Reception
  • 18.3 USART Synchronous Master Mode
    • 18.3.1 USART Synchronous Master Transmission
      • TABLE 18-8: Registers Associated with Synchronous Master Transmission
      • FIGURE 18-6: Synchronous Transmission
      • FIGURE 18-7: Synchronous Transmission (Through TXEN)
    • 18.3.2 USART Synchronous Master Reception
      • TABLE 18-9: Registers Associated with Synchronous Master Reception
      • FIGURE 18-8: Synchronous Reception (Master Mode, SREN)
  • 18.4 USART Synchronous Slave Mode
    • 18.4.1 USART Synchronous Slave Transmit
    • 18.4.2 USART Synchronous Slave Reception
      • TABLE 18-10: Registers Associated with Synchronous Slave Transmission
      • TABLE 18-11: Registers Associated with Synchronous Slave Reception
• 19.0 CAN Module
  • 19.1 Overview
    • 19.1.1 Overview of the Module
    • 19.1.2 Transmit/Receive Buffers
      • FIGURE 19-1: CAN Buffers and Protocol Engine Block Diagram
  • 19.2 CAN Module Registers
    • 19.2.1 CAN Control and Status Registers
      • Register 19-1: CANCON: CAN Control Register
      • Register 19-2: CANSTAT: CAN Status Register
      • EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers
      • EXAMPLE 19-1: WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers (Cont...
      • Register 19-3: COMSTAT: Communication Status Register
    • 19.2.2 CAN Transmit Buffer Registers
      • Register 19-4: TXBnCON: Transmit Buffer n Control Registers
      • Register 19-5: TXBnSIDH: Transmit Buffer n Standard Identifier, High Byte Registers
      • Register 19-6: TXBnSIDL: Transmit Buffer n Standard Identifier, Low Byte Registers
      • Register 19-7: TXBnEIDH: Transmit Buffer n Extended Identifier, High Byte Registers
      • Register 19-8: TXBnEIDL: Transmit Buffer n Extended Identifier, Low Byte Registers
      • Register 19-9: TXBnDm: Transmit Buffer n Data Field Byte m Registers
      • Register 19-10: TXBnDLC: Transmit Buffer N Data Length Code Registers
      • Register 19-11: TXERRCNT: Transmit Error Count Register
    • 19.2.3 CAN Receive Buffer Registers
      • Register 19-12: RXB0CON: Receive Buffer 0 Control Register
      • Register 19-13: RXB1CON: Receive Buffer 1 Control Register
      • Register 19-14: RXBnSIDH: Receive Buffer N Standard Identifier, High Byte Registers
      • Register 19-15: RXBnSIDL: Receive Buffer N Standard Identifier, Low Byte Registers
      • Register 19-16: RXBnEIDH: Receive Buffer N Extended Identifier, High Byte Registers
      • Register 19-17: RXBnEIDL: Receive Buffer N Extended Identifier, Low Byte Registers
      • Register 19-18: RXBnDLC: Receive Buffer N Data Length Code Registers
      • Register 19-19: RXBnDm: Receive Buffer N Data Field Byte M Registers
      • Register 19-20: RXERRCNT: Receive Error Count Register
      • Register 19-21: RXFnSIDH: Receive Acceptance Filter N Standard Identifier Filter, High Byte Regis...
      • Register 19-22: RXFnSIDL: Receive Acceptance Filter N Standard Identifier Filter, Low Byte Registers
      • Register 19-23: RXFnEIDH: Receive Acceptance Filter N Extended Identifier, High Byte Registers
      • Register 19-24: RXFnEIDL: Receive Acceptance Filter N Extended Identifier, Low Byte Registers
      • Register 19-25: RXMnSIDH: Receive Acceptance Mask N Standard Identifier Mask, High Byte Registers
      • Register 19-26: RXMnSIDL: Receive Acceptance Mask N Standard Identifier Mask, Low Byte Registers
      • Register 19-27: RXMnEIDH: Receive Acceptance Mask N Extended Identifier Mask, High Byte Registers
      • Register 19-28: RXMnEIDL: Receive Acceptance Mask N Extended Identifier Mask, Low Byte Registers
    • 19.2.4 CAN Baud Rate Registers
      • Register 19-29: BRGCON1: Baud Rate Control Register 1
      • Register 19-30: BRGCON2: Baud Rate Control Register 2
      • Register 19-31: BRGCON3: Baud Rate Control Register 3
    • 19.2.5 CAN Module I/O Control Register
      • Register 19-32: CIOCON: CAN I/O Control Register
    • 19.2.6 CAN Interrupt Registers
      • Register 19-33: PIR3: Peripheral Interrupt Request (Flag) Register 3
      • Register 19-34: PIE3: Peripheral Interrupt Enable Register 3
      • Register 19-35: IPR3: Peripheral Interrupt Priority Register 3
      • TABLE 19-1: CAN Controller Register Map
  • 19.3 CAN Modes of Operation
    • 19.3.1 Configuration Mode
    • 19.3.2 Disable Mode
    • 19.3.3 Normal Mode
    • 19.3.4 Listen Only Mode
    • 19.3.5 Loopback Mode
    • 19.3.6 Error Recognition Mode
  • 19.4 CAN Message Transmission
    • 19.4.1 Transmit Buffers
    • 19.4.2 Transmit Priority
      • FIGURE 19-2: Transmit Buffer Block Diagram
    • 19.4.3 Initiating Transmission
    • 19.4.4 Aborting Transmission
      • FIGURE 19-3: Internal Transmit Message Flowchart
  • 19.5 Message Reception
    • 19.5.1 Receive Message Buffering
    • 19.5.2 Receive Buffers
    • 19.5.3 Receive Priority
    • 19.5.4 Time-Stamping
      • FIGURE 19-4: Receive Buffer Block Diagram
      • FIGURE 19-5: Internal Message Reception Flowchart
  • 19.6 Message Acceptance Filters and Masks
    • TABLE 19-2: Filter/Mask Truth Table
    • FIGURE 19-6: Message Acceptance Mask and Filter Operation
  • 19.7 Baud Rate Setting
    • FIGURE 19-7: Bit Time Partitioning
    • 19.7.1 Time Quanta
      • EXAMPLE 19-2: Calculating Tq, Nominal Bit Rate and Nominal Bit Time
    • 19.7.2 Synchronization Segment
    • 19.7.3 Propagation Segment
    • 19.7.4 Phase Buffer Segments
    • 19.7.5 Sample Point
    • 19.7.6 Information Processing Time
  • 19.8 Synchronization
    • 19.8.1 Hard Synchronization
    • 19.8.2 Resynchronization
    • 19.8.3 synchronization rules
      • FIGURE 19-8: Lengthening a Bit Period (Adding SJW to Phase Segment 1)
      • FIGURE 19-9: Shortening a Bit Period (Subtracting SJW From Phase Segment 2)
  • 19.9 Programming Time Segments
  • 19.10 Oscillator Tolerance
  • 19.11 Bit Timing Configuration Registers
    • 19.11.1 BRGCON1
    • 19.11.2 BRGCON2
    • 19.11.3 BRGCON3
  • 19.12 Error Detection
    • 19.12.1 CRC Error
    • 19.12.2 Acknowledge Error
    • 19.12.3 Form Error
    • 19.12.4 Bit Error
    • 19.12.5 Stuff Bit Error
    • 19.12.6 Error States
    • 19.12.7 Error Modes and Error Counters
      • FIGURE 19-10: Error Modes State Diagram
  • 19.13 CAN Interrupts
    • 19.13.1 Interrupt Code Bits
    • 19.13.2 Transmit Interrupt
    • 19.13.3 Receive Interrupt
      • TABLE 19-3: Values for ICODE<2:0>
    • 19.13.4 Message Error Interrupt
    • 19.13.5 Bus Activity Wake-up Interrupt
    • 19.13.6 Error Interrupt
    • 19.13.7 Interrupt Acknowledge
• 20.0 Compatible 10-Bit Analog- to-Digital Converter (A/D) Module
  • Register 20-1: ADCON0: A/D Control Register 0
  • Register 20-2: ADCON1: A/D Control Register 1
  • FIGURE 20-1: A/D Block Diagram
  • 20.1 A/D Acquisition Requirements
    • FIGURE 20-2: Analog Input Model
    • EQUATION 20-1: Acquisition Time
    • EQUATION 20-2: A/D Minimum Charging Time
    • EXAMPLE 20-1: Calculating The Minimum Required Acquisition Time
  • 20.2 Selecting the A/D Conversion Clock
  • 20.3 Configuring Analog Port Pins
    • TABLE 20-1: Tad vs. Device Operating Frequencies
    • TABLE 20-2: Tad vs. Device Operating Frequencies (for Extended, LF Devices)
  • 20.4 A/D Conversions
    • 20.4.1 A/D Result Registers
      • FIGURE 20-3: A/D Result Justification
  • 20.5 Use of the ECCP Trigger
    • FIGURE 20-4: A/D Conversion Tad Cycles
    • TABLE 20-3: Summary of A/D Registers
• 21.0 Comparator Module
  • Register 21-1: CMCON: Comparator Control Register
  • 21.1 Comparator Configuration
    • FIGURE 21-1: Comparator I/O Operating Modes
  • 21.2 Comparator Operation
  • 21.3 Comparator Reference
    • FIGURE 21-2: Single Comparator
    • 21.3.1 External Reference Signal
    • 21.3.2 Internal Reference Signal
  • 21.4 Comparator Response Time
  • 21.5 Comparator Outputs
    • FIGURE 21-3: Comparator Output Block Diagram
  • 21.6 Comparator Interrupts
  • 21.7 Comparator Operation During Sleep
  • 21.8 Effects of a Reset
  • 21.9 Analog Input Connection Considerations
    • FIGURE 21-4: Analog Input Model
    • TABLE 21-1: Registers Associated with Comparator Module
• 22.0 Comparator Voltage Reference Module
  • 22.1 Configuring the Comparator Voltage Reference
    • EQUATION 22-1:
    • EQUATION 22-2:
    • Register 22-1: CVRCON: Comparator Voltage Reference Control Register
    • FIGURE 22-1: Voltage Reference Block Diagram
  • 22.2 Voltage Reference Accuracy/Error
  • 22.3 Operation During Sleep
  • 22.4 Effects of a Reset
  • 22.5 Connection Considerations
    • FIGURE 22-2: Voltage Reference Output Buffer Example
    • TABLE 22-1: Registers Associated with Comparator Voltage Reference
• 23.0 Low-Voltage Detect
  • FIGURE 23-1: Typical Low-Voltage Detect Application
  • FIGURE 23-2: Low-Voltage Detect (LVD) Block Diagram
  • FIGURE 23-3: Low-Voltage Detect (LVD) with External Input Block Diagram
  • 23.1 Control Register
    • Register 23-1: LVDCON: Low-Voltage Detect Control Register
  • 23.2 Operation
    • FIGURE 23-4: Low-Voltage Detect Waveforms
    • 23.2.1 Reference Voltage Set Point
    • 23.2.2 Current Consumption
  • 23.3 Operation During Sleep
  • 23.4 Effects of a Reset
• 24.0 Special Features of the CPU
  • 24.1 Configuration Bits
    • TABLE 24-1: Configuration Bits and Device IDs
    • Register 24-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
    • Register 24-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
    • Register 24-3: config2h: Configuration Register 2 High (Byte Address 300003h)
    • Register 24-4: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
    • Register 24-5: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
    • Register 24-6: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
    • Register 24-7: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
    • Register 24-8: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
    • Register 24-9: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
    • Register 24-10: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
    • Register 24-11: DEVID1: Device ID Register 1 for PIC18FXX8 Devices (Byte Address 3FFFFEh)
    • Register 24-12: DEVID2: Device ID Register 2 for PIC18FXX8 Devices (Byte Address 3FFFFFh)
  • 24.2 Watchdog Timer (WDT)
    • 24.2.1 Control Register
      • Register 24-13: WDTCON: Watchdog Timer Control Register
    • 24.2.2 WDT Postscaler
      • FIGURE 24-1: Watchdog Timer Block Diagram
      • TABLE 24-2: Summary of Watchdog Timer Registers
  • 24.3 Power-Down Mode (Sleep)
    • 24.3.1 Wake-up From Sleep
    • 24.3.2 Wake-up Using Interrupts
      • FIGURE 24-2: Wake-up From Sleep Through Interrupt(1,2)
  • 24.4 Program Verification and Code Protection
    • FIGURE 24-3: Code-Protected Program Memory for PIC18FXX8
    • TABLE 24-3: Summary of Code Protection Registers
    • 24.4.1 Program Memory Code Protection
      • FIGURE 24-4: Table Write (WRTn) Disallowed
      • FIGURE 24-5: External Block Table Read (EBTRn) Disallowed
      • FIGURE 24-6: External Block Table Read (EBTRn) Allowed
    • 24.4.2 Data EEPROM Code Protection
    • 24.4.3 Configuration Register Protection
  • 24.5 ID Locations
  • 24.6 In-Circuit Serial Programming
  • 24.7 In-Circuit Debugger
  • 24.8 Low-Voltage ICSP Programming
• 25.0 Instruction Set Summary
  • 25.1 ReadModify-Write Operations
    • TABLE 25-1: Opcode Field Descriptions
    • FIGURE 25-1: General Format for Instructions
    • TABLE 25-2: PIC18FXXX Instruction Set
  • 25.2 Instruction Set
• 26.0 Development Support
  • 26.1 MPLAB Integrated Development Environment Software
  • 26.2 MPASM Assembler
  • 26.3 MPLAB C17 and MPLAB C18 C Compilers
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 26.5 MPLAB C30 C Compiler
  • 26.6 MPLAB ASM30 Assembler, Linker and Librarian
  • 26.7 MPLAB SIM Software Simulator
  • 26.8 MPLAB SIM30 Software Simulator
  • 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator
  • 26.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator
  • 26.11 MPLAB ICD 2 In-Circuit Debugger
  • 26.12 PRO MATE II Universal Device Programmer
  • 26.13 MPLAB PM3 Device Programmer
  • 26.14 PICSTART Plus Development Programmer
  • 26.15 PICDEM 1 PICmicro Demonstration Board
  • 26.16 PICDEM.net Internet/Ethernet Demonstration Board
  • 26.17 PICDEM 2 Plus Demonstration Board
  • 26.18 PICDEM 3 PIC16C92X Demonstration Board
  • 26.19 PICDEM 4 8/14/18-Pin Demonstration Board
  • 26.20 PICDEM 17 Demonstration Board
  • 26.21 PICDEM 18R PIC18C601/801 Demonstration Board
  • 26.22 PICDEM LIN PIC16C43X Demonstration Board
  • 26.23 PICkitTM 1 Flash Starter Kit
  • 26.24 PICDEM USB PIC16C7X5 Demonstration Board
  • 26.25 Evaluation and Programming Tools
• 27.0 Electrical Characteristics
  • Absolute Maximum Ratings(�)
    • FIGURE 27-1: PIC18FXX8 Voltage-Frequency Graph (Industrial)
    • FIGURE 27-2: PIC18FXX8 Voltage-Frequency Graph (Extended)
    • FIGURE 27-3: PIC18LFXX8 Voltage-Frequency Graph (Industrial)
  • 27.1 DC Characteristics
  • 27.2 DC Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
    • FIGURE 27-4: Low-Voltage Detect Characteristics
    • TABLE 27-1: Low-Voltage Detect Characteristics
    • TABLE 27-2: DC Characteristics: EEPROM and Enhanced Flash
    • TABLE 27-3: Comparator Specifications
    • TABLE 27-4: Voltage Reference Specifications
  • 27.3 AC (Timing) Characteristics
    • 27.3.1 Timing Parameter Symbology
    • 27.3.2 Timing Conditions
      • TABLE 27-5: Temperature and Voltage Specifications � AC
      • FIGURE 27-5: Load Conditions for Device Timing Specifications
    • 27.3.3 Timing Diagrams and Specifications
      • FIGURE 27-6: External Clock Timing
      • TABLE 27-6: External Clock Timing Requirements
      • TABLE 27-7: PLL Clock Timing Specifications (Vdd = 4.2 to 5.5V)
      • FIGURE 27-7: CLKO and I/O Timing
      • TABLE 27-8: CLKO and I/O Timing Requirements
      • FIGURE 27-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 27-9: Brown-out Reset and Low-Voltage Detect Timing
      • TABLE 27-9: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, Brown-out Reset and...
      • FIGURE 27-10: Timer0 and Timer1 External Clock Timings
      • TABLE 27-10: Timer0 and Timer1 External Clock Requirements
      • FIGURE 27-11: Capture/Compare/PWM Timings (CCP1 and ECCP1)
      • TABLE 27-11: Capture/Compare/PWM Requirements (CCP1 and ECCP1)
      • FIGURE 27-12: Parallel Slave Port Timing (PIC18F248 and PIC18F458)
      • TABLE 27-12: Parallel Slave Port Requirements (PIC18F248 and PIC18F458)
      • FIGURE 27-13: Example SPI� Master Mode Timing (CKE=0)
      • TABLE 27-13: Example SPI� Mode Requirements (Master Mode, CKE=0)
      • FIGURE 27-14: Example SPI� Master Mode Timing (CKE=1)
      • TABLE 27-14: Example SPI� Mode Requirements (Master Mode, CKE=1)
      • FIGURE 27-15: Example SPI� Slave Mode Timing (CKE=0)
      • TABLE 27-15: Example SPI� Mode Requirements, Slave Mode Timing (CKE=0)
      • FIGURE 27-16: Example SPI� Slave Mode Timing (CKE=1)
      • TABLE 27-16: Example SPI� Slave Mode Requirements (CKE=1)
      • FIGURE 27-17: I2C� Bus Start/Stop Bits Timing
      • TABLE 27-17: I2C� Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 27-18: I2C� Bus Data Timing
      • TABLE 27-18: I2C� Bus Data Requirements (Slave Mode)
      • FIGURE 27-19: Master SSP I2C� Bus Start/Stop Bits Timing Waveforms
      • TABLE 27-19: Master SSP I2C� Bus Start/Stop Bits Requirements
      • FIGURE 27-20: Master SSP I2C� Bus Data Timing
      • TABLE 27-20: Master SSP I2C� Bus Data Requirements
      • FIGURE 27-21: USART Synchronous Transmission (Master/Slave) Timing
      • TABLE 27-21: USART Synchronous Transmission Requirements
      • FIGURE 27-22: USART Synchronous Receive (Master/Slave) Timing
      • TABLE 27-22: USART Synchronous Receive Requirements
      • TABLE 27-23: A/D Converter Characteristics: PIC18FXX8 (Industrial, Extended) PIC18LFXX8 (Industrial)
      • FIGURE 27-23: A/D Conversion Timing
      • TABLE 27-24: A/D Conversion Requirements
• 28.0 DC and AC Characteristics Graphs and Tables
  • FIGURE 28-1: Typical Idd vs. Fosc Over Vdd (Hs Mode)
  • FIGURE 28-2: Maximum Idd vs. Fosc Over Vdd (Hs Mode)
  • FIGURE 28-3: Typical Idd vs. Fosc Over Vdd (HS/PLL Mode)
  • FIGURE 28-4: Maximum Idd vs. Fosc Over Vdd (HS/PLL Mode)
  • FIGURE 28-5: Typical Idd vs. Fosc Over Vdd (XT Mode)
  • FIGURE 28-6: Maximum Idd vs. Fosc Over Vdd (XT Mode)
  • FIGURE 28-7: Typical Idd vs. Fosc Over Vdd (LP Mode)
  • FIGURE 28-8: Maximum Idd vs. Fosc Over Vdd (LP Mode)
  • FIGURE 28-9: Typical Idd vs. Fosc Over Vdd (EC Mode)
  • FIGURE 28-10: Maximum Idd vs. Fosc Over Vdd (EC Mode)
  • FIGURE 28-11: Typical and Maximum Idd vs. Vdd (Timer1 as Main Oscillator 32.768kHz, C1 and C2 = ...
  • FIGURE 28-12: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25�C)
  • FIGURE 28-13: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100pF, +25�C)
  • FIGURE 28-14: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25�C)
  • FIGURE 28-15: Ipd vs. Vdd, -40�C to +125�C (Sleep Mode, All Peripherals Disabled)
  • FIGURE 28-16: DIbor vs. Vdd Over Temperature (BOR Enabled, Vbor = 2.00-2.16V)
  • FIGURE 28-17: Typical and Maximum DItmr1 vs. Vdd Over Temperature (-10�C to +70�C, Timer1 with Os...
  • FIGURE 28-18: Typical and Maximum DIwdt vs. Vdd Over Temperature (WDT Enabled)
  • FIGURE 28-19: Typical, Minimum and Maximum WDT Period vs. Vdd (-40�C to +125�C)
  • FIGURE 28-20: DIlvd vs. Vdd Over Temperature (LVD Enabled, Vlvd = 4.5 - 4.78V)
  • FIGURE 28-21: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40�C to +125�C)
  • FIGURE 28-22: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40�C to +125�C)
  • FIGURE 28-23: Typical and Maximum Vol vs. Iol (Vdd = 5V, -40�C to +125�C)
  • FIGURE 28-24: Typical and Maximum Vol vs. Iol (Vdd = 3V, -40�C to +125�C)
  • FIGURE 28-25: Minimum and Maximum Vin vs. Vdd (ST Input, -40�C to +125�C)
  • FIGURE 28-26: Minimum and Maximum Vin vs. Vdd (TTL Input, -40�C to +125�C)
  • FIGURE 28-27: Minimum and Maximum Vin vs. Vdd (I2C� Input, -40�C to +125�C)
  • FIGURE 28-28: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40�C to +125�C)
  • FIGURE 28-29: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40�C to +125�C)
• 29.0 Packaging Information
  • 29.1 Package Marking Information
  • 29.1 Package Marking Information (Continued)
  • 29.2 Package Details
    • 28-Lead Skinny Plastic Dual In-line (SP) � 300 mil Body (PDIP)
    • 28-Lead Plastic Small Outline (SO) �Wide, 300 mil Body (SOIC)
    • 40-Lead Plastic Dual In-line (P) � 600 mil Body (PDIP)
    • 44-Lead Plastic Leaded Chip Carrier (L) � Square (PLCC)
    • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
• Appendix A: Data Sheet Revision History
  • Revision A (June 2001)
  • Revision B (May 2002)
  • Revision C (January 2003)
  • Revision D (September 2004)
• Appendix B: Device Differences
  • TABLE B-1: Device Differences
• Appendix C: Device Migrations
• Appendix D: Migrating From Other PICmicro� Devices
  • D.1 PIC16CXXX to PIC18FXX8
  • D.2 PIC17CXXX to PIC18FXX8
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
• Systems Information and Upgrade Hot Line
• Reader Response
• PIC18FXX8 Product Identification System
• Worldwide Sales and Service