2005 Microchip Technology Inc.
DS21333B-page 1
TC1302A/B
Features
Dual Output LDO:
- V
OUT1
= 1.5V to 3.3V @ 300 mA
- V
OUT2
= 1.5V to 3.3V @ 150 mA
Output Voltage (See Table 8-1)
Low Dropout Voltage:
- V
OUT1
= 104 mV @ 300 mA Typical
- V
OUT2
= 150 mV @ 150 mA Typical
Low Supply Current: 116 A Typical
TC1302A/B with both output voltages available
Reference Bypass Input for Low-Noise Operation
Both Output Voltages Stable with a Minimum of
1 F Ceramic Output Capacitor
Separate V
OUT1
and V
OUT2
SHDN pins
(TC1302B)
Power-Saving Shutdown Mode of Operation
Wake-up from SHDN: 5.3 s. Typical
Small 8-pin DFN or MSOP Package Options
Operating Junction Temperature Range:
- -40C to +125C
Overtemperature and Overcurrent Protection
Applications
Cellular/GSM/PHS Phones
Battery-Operated Systems
Hand-Held Medical Instruments
Portable Computers/PDAs
Linear Post-Regulators for SMPS
Pagers
Related Literature
AN765, "Using Microchip's Micropower LDOs",
DS00765, Microchip Technology Inc., 2002
AN766, "Pin-Compatible CMOS Upgrades to
BiPolar LDOs", DS00766,
Microchip Technology Inc., 2002
AN792, "A Method to Determine How Much
Power a SOT23 Can Dissipate in an Application",
DS00792, Microchip Technology Inc., 2001
Description
The TC1302A/B combines two Low Dropout (LDO)
regulators into a single 8-pin MSOP or DFN package.
Both regulator outputs feature low dropout voltage,
104 mV @ 300 mA for V
OUT1
, 150 mV @ 150 mA for
V
OUT2
, low quiescent current consumption, 58 A each
and a typical regulation accuracy of 0.5%. Several
fixed-output voltage combinations are available. A
reference bypass pin is available to further reduce
output noise and improve the power supply rejection
ratio of both LDOs.
The TC1302A/B is stable over all line and load
conditions, with a minimum of 1 F of ceramic output
capacitance, and utilizes a unique compensation
scheme to provide fast dynamic response to sudden
line voltage and load current changes.
Additional features include an overcurrent limit and
overtemperature protection that combine to provide a
robust design for all load fault conditions.
Package Types
8-Pin DFN/MSOP
NC
SHDN2
Bypass
GND
NC
1
2
3
4
5
6
7
8
V
OUT2
V
IN
1
2
3
4
5
6
7
8
V
OUT1
TC1302A
NC
SHDN2
Bypass
GND
NC
V
OUT2
V
IN
V
OUT1
DFN8
MSOP8
NC
SHDN2
Bypass
GND
SHDN1
1
2
3
4
5
6
7
8
V
OUT2
V
IN
1
2
3
4
5
6
7
8
V
OUT1
TC1302B
NC
SHDN2
Bypass
GND
SHDN1
V
OUT2
V
IN
V
OUT1
DFN8
MSOP8
Low Quiescent Current Dual Output LDO
TC1302A/B
DS21333B-page 2
2005 Microchip Technology Inc.
Functional Block Diagrams
Typical Application Circuits
LDO #2
150 mA
LDO #1
300 mA
LDO #2
150 mA
V
IN
V
OUT1
V
OUT2
Bandgap
Reference
SHDN2
GND
Bypass
TC1302A
TC1302B
V
IN
SHDN2
GND
Bypass
SHDN1
LDO #1
300 mA
Bandgap
Reference
V
OUT1
V
OUT2
1.2V
1.2V
8
4
1
2
3
NC
GND
NC
BATTERY
C
OUT1
1 F Ceramic
X5R
C
IN
1 F
TC1302A
C
OUT2
1 F Ceramic
X5R
C
BYPASS
(Note)
10 nF Ceramic
Bypass
V
IN
7
2.7V
to
4.2V
V
OUT2
6
SHDN2
ON/OFF Control V
OUT2
2.8V @ 300 mA
2.6V @ 150 mA
5
V
OUT1
8
4
1
2
3
NC
GND
SHDN1
BATTERY
C
OUT1
1 F Ceramic
X5R
C
IN
1 F
TC1302B
C
OUT2
1 F Ceramic
X5R
Bypass
V
IN
7
2.7V
to
4.2V
V
OUT2
6
SHDN2
ON/OFF Control V
OUT2
2.8V @ 300 mA
2.6V @ 150 mA
5
ON/OFF Control V
OUT1
Note: C
BYPASS
is optional
V
OUT1
2005 Microchip Technology Inc.
DS21333B-page 3
TC1302A/B
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
V
DD
...................................................................................6.5V
Maximum Voltage on Any Pin ...... (V
SS
0.3) to (V
IN
+ 0.3)V
Power Dissipation ..........................Internally Limited (Note 7)
Storage temperature .....................................-65C to +150C
Maximum Junction Temperature, T
J
........................... +150C
Continuous Operating Temperature Range ..-40C to +125C
ESD protection on all pins, HBM, MM
.....................
4 kV, 400V
Notice: Stresses above those listed under "Maximum Rat-
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F,
C
OUT1
= C
OUT2
= 1 F, C
BYPASS
= 10 nF, SHDN > V
IH
, T
A
= +25C.
Boldface type specifications apply for junction temperatures of -40C to +125C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Operating Voltage
V
IN
2.7
--
6.0
V
Note 1
Maximum Output Current
I
OUT1Max
300
--
--
mA
V
IN
= 2.7V to 6.0V (Note 1)
Maximum Output Current
I
OUT2Max
150
--
--
mA
V
IN
= 2.7V to 6.0V (Note 1)
Output Voltage Tolerance
(V
OUT1
and V
OUT2
)
V
OUT
V
R
2.5
V
R
0.5 V
R
+ 2.5
%
Note 2
Temperature Coefficient
(V
OUT1
and V
OUT2
)
TCV
OUT
--
25
--
ppm/C
Note 3
Line Regulation
(V
OUT1
and V
OUT2
)
V
OUT
/
V
IN
--
0.02
0.2
%/V
(V
R
+ 1V)
V
IN
6V
Load Regulation, V
OUT
2.5V
(V
OUT1
and V
OUT2
)
V
OUT
/
V
OUT
-1
0.1
+1
%
I
OUTX
= 0.1 mA to I
OUTMax
,
(Note 4)
Load Regulation, V
OUT
< 2.5V
(V
OUT1
and V
OUT2
)
V
OUT
/
V
OUT
-1.5
0.1
+1.5
%
I
OUTX
= 0.1 mA to I
OUTMax
,
(Note 4)
Thermal Regulation
V
OUT
/
P
D
--
0.04
--
%/W
Note 5
Dropout Voltage (Note 6)
V
OUT1
> 2.7V
V
IN
V
OUT
--
104
180
mV
I
OUT1
= 300 mA
V
OUT2
> 2.6V
V
IN
V
OUT
--
150
250
mV
I
OUT2
= 150 mA
Supply Current
TC1302A
I
IN(A)
--
103
180
A
SHDN2 = V
IN
, I
OUT1
= I
OUT2
= 0 mA
TC1302B
I
IN(B)
--
114
180
A
SHDN1 = SHDN2 = V
IN
,
I
OUT1
= I
OUT2
= 0 mA
Note
1:
The minimum V
IN
has to meet two conditions: V
IN
2.7V and V
IN
V
R
+ V
DROPOUT
.
2:
V
R
is defined as the higher of the two regulator nominal output voltages (V
OUT1
or V
OUT2
).
3:
TCV
OUT
= ((V
OUTmax
- V
OUTmin
) * 10
6
)/(V
OUT
*
T).
4:
Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
5:
Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to I
LMAX
at V
IN
= 6V for t = 10 msec.
6:
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
value measured at a 1V differential.
7:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air (i.e., T
A
, T
J
,
JA
). Exceeding the maximum allowable power
dissipation causes the device to initiate thermal shutdown.
TC1302A/B
DS21333B-page 4
2005 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
Shutdown Supply Current
TC1302A
I
IN_SHDNA
--
58
90
A
SHDN2 = GND
Shutdown Supply Current
TC1302B
I
IN_SHDNB
--
0.1
1
A
SHDN1 = SHDN2 = GND
Power Supply Rejection Ratio
PSRR
--
58
--
dB
f
100 Hz, I
OUT1
= I
OUT2
= 50 mA,
C
IN
= 0 F
Output Noise
eN
--
830
--
nV/(Hz)
f
1 kHz, I
OUT1
= I
OUT2
= 50 mA,
C
IN
= 0 F
Output Short Circuit Current (Average)
V
OUT1
I
OUTsc1
--
200
--
mA
R
LOAD1
1
V
OUT2
I
OUTsc2
--
140
--
mA
R
LOAD2
1
SHDN Input High Threshold
V
IH
45
--
--
%V
IN
V
IN
= 2.7V to 6.0V
SHDN Input Low Threshold
V
IL
--
--
15
%V
IN
V
IN
= 2.7V to 6.0V
Wake Up Time (From SHDN
mode), (V
OUT2
)
t
WK
--
5.3
20
s
V
IN
= 5V, I
OUT1
= I
OUT2
= 30 mA,
See Figure 5-1
Settling Time (From SHDN mode),
(V
OUT2
)
t
S
--
50
--
s
V
IN
= 5V, I
OUT1
= I
OUT2
= 50 mA,
See Figure 5-2
Thermal Shutdown Die
Temperature
T
SD
--
150
--
C
V
IN
= 5V, I
OUT1
= I
OUT2
= 100 A
Thermal Shutdown Hysteresis
T
HYS
--
10
--
C
V
IN
= 5V
Electrical Specifications: Unless otherwise indicated, all limits are specified for: V
IN
= +2.7V to +6.0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Operating Junction Temperature Range
T
A
-40
--
+125
C
Steady State
Storage Temperature Range
T
A
-65
--
+150
C
Maximum Junction Temperature
T
J
--
--
+150
C
Transient
Thermal Package Resistances
Thermal Resistance, MSOP8
JA
--
208
--
C/W
Typical 4-Layer Board
Thermal Resistance, DFN8
JA
--
41
--
C/W
Typical 4-Layer Board with Vias
DC CHARACTERISTICS (Continued)
Electrical Specifications: Unless otherwise noted, V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F,
C
OUT1
= C
OUT2
= 1 F, C
BYPASS
= 10 nF, SHDN > V
IH
, T
A
= +25C.
Boldface type specifications apply for junction temperatures of -40C to +125C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note
1:
The minimum V
IN
has to meet two conditions: V
IN
2.7V and V
IN
V
R
+ V
DROPOUT
.
2:
V
R
is defined as the higher of the two regulator nominal output voltages (V
OUT1
or V
OUT2
).
3:
TCV
OUT
= ((V
OUTmax
- V
OUTmin
) * 10
6
)/(V
OUT
*
T).
4:
Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested
over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating
effects are covered by the thermal regulation specification.
5:
Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied,
excluding load or line regulation effects. Specifications are for a current pulse equal to I
LMAX
at V
IN
= 6V for t = 10 msec.
6:
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its
value measured at a 1V differential.
7:
The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction
temperature and the thermal resistance from junction to air (i.e., T
A
, T
J
,
JA
). Exceeding the maximum allowable power
dissipation causes the device to initiate thermal shutdown.
2005 Microchip Technology Inc.
DS21333B-page 5
TC1302A/B
2.0
TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated,
V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F, C
OUT1 =
C
OUT2
= 1 F (X5R or X7R),
C
BYPASS
= 0 pF, SHDN1 = SHDN2 > V
IH
, T
A
= +25C.
FIGURE 2-1:
Quiescent Current vs. Input
Voltage.
FIGURE 2-2:
SHDN Voltage Threshold
vs. Input Voltage.
FIGURE 2-3:
Quiescent Current vs.
Junction Temperature.
FIGURE 2-4:
Output Voltage vs. Input
Voltage.
FIGURE 2-5:
Output Voltage vs. Input
Voltage.
FIGURE 2-6:
Dropout Voltage vs. Output
Current (V
OUT1
).
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
50
100
150
200
250
300
350
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0
Input Voltage (V)
Quiescent C
u
r
r
e
nt (
A
)
V
OUT2
SHDN
V
OUT2
Active
T
J
= +25C
I
OUT1
= I
OUT2
= 0 A
V
OUT1
Active
TC1302B
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
Input Voltage (V)
SH
D
N
Thr
e
s
hol
d
(
V
)
ON
OFF
40
50
60
70
80
90
100
110
120
130
140
-40 -25 -10
5
20 35 50 65
80 95 110 125
Junction Temperature (C)
Quiescent C
u
r
r
e
nt (
A
)
V
IN
= 4.2V
I
OUT1
= I
OUT2
= 0 A
V
OUT1
Active
V
OUT2
SHDN
V
OUT2
Active
TC1302B
2.60
2.70
2.80
2.90
3.00
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
Input Voltage (V)
Output V
o
ltage (V
)
T
J
= +25C
I
OUT1
= 100 mA
I
OUT2
= 50 mA
V
OUT1
V
OUT2
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
6
Input Voltage (V)
Output V
o
ltage (V
)
T
J
= +25C
I
OUT1
= 300 mA
I
OUT2
= 100 mA
V
OUT1
V
OUT2
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
0
50
100
150
200
250
300
I
OUT1
(mA)
D
r
opout V
o
l
t
age V
OUT
1
(m
V
)
V
R1
= 2.8V
V
R2
= 2.6V
I
OUT2
= 100 A
T
J
= - 40C
T
J
= +25C
T
J
= +125C
TC1302A/B
DS21333B-page 6
2005 Microchip Technology Inc.
Note: Unless otherwise indicated,
V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F, C
OUT1 =
C
OUT2
= 1 F (X5R or X7R),
C
BYPASS
= 0 pF, SHDN1 = SHDN2 > V
IH
, T
A
= +25C.
FIGURE 2-7:
Dropout Voltage vs.
Junction Temperature (V
OUT1
).
FIGURE 2-8:
Dropout Voltage vs. Output
Current (V
OUT2
).
FIGURE 2-9:
Dropout Voltage vs.
Junction Temperature (V
OUT2
).
FIGURE 2-10:
V
OUT1
and V
OUT2
Load
Regulation vs. Junction Temperature.
FIGURE 2-11:
V
OUT1
and V
OUT2
Line
Regulation vs. Junction Temperature.
FIGURE 2-12:
V
OUT1
vs. Junction
Temperature.
0
20
40
60
80
100
120
140
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (C)
D
r
opout V
o
l
t
age V
OUT
1
(m
V
)
V
R1
= 2.8V
V
R2
= 2.6V
I
OUT2
= 100 A
I
OUT1
= 300 mA
I
OUT1
= 100 mA
I
OUT1
= 50 mA
0
20
40
60
80
100
120
140
160
180
0
30
60
90
120
150
I
OUT2
(mA)
D
r
opout V
o
l
t
age,
V
OUT
2
(m
v)
V
R1
= 2.8V
V
R2
= 2.6V
I
OUT1
= 100 A
T
J
= +125C
T
J
= +25C
T
J
= - 40C
0
20
40
60
80
100
120
140
160
180
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (C)
D
r
opout V
o
l
t
age V
OUT
2
(m
V
)
V
R1
= 2.8V
V
R2
= 2.6V
I
OUT1
= 100 A
I
OUT2
= 150 mA
I
OUT2
= 50 mA
I
OUT2
= 10 mA
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
-40 -25 -10
5
20
35
50
65
80
95 110 125
Junction Temperature (125C)
Load Regulation (%
)
I
OUT2
= 0.1 mA to 150 mA
I
OUT1
= 0.1 mA to 300 mA
V
R1
= 2.8V
V
R2
= 2.6V
V
IN
= 4.2
V
OUT2
V
OUT1
0.000
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0.040
0.045
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (C)
Li
ne R
e
gul
ati
on (%
/
V
)
V
IN
= 3.8V to 6.0V
V
R1
= 2.8V, I
OUT1
= 100 A
V
R2
= 2.6V, I
OUT2
= 100 A
V
OUT1
V
OUT2
2.808
2.812
2.816
2.820
2.824
2.828
2.832
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (C)
Ou
tp
u
t
Vo
l
t
ag
e V
OU
T1
(V)
V
IN
= 4.2V
V
R1
= 2.8V
V
R2
= 2.6V, I
OUT2
= 100 A
I
OUT1
= 300 mA
I
OUT1
= 100 A
I
OUT1
= 100 mA
2005 Microchip Technology Inc.
DS21333B-page 7
TC1302A/B
Note: Unless otherwise indicated,
V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F, C
OUT1 =
C
OUT2
= 1 F (X5R or X7R),
C
BYPASS
= 0 pF, SHDN1 = SHDN2 > V
IH
, T
A
= +25C.
FIGURE 2-13:
V
OUT1
vs. Junction
Temperature.
FIGURE 2-14:
V
OUT2
vs. Junction
Temperature.
FIGURE 2-15:
V
OUT2
vs. Junction
Temperature.
FIGURE 2-16:
Power Supply Rejection
Ratio vs. Frequency (without bypass capacitor).
FIGURE 2-17:
Power Supply Rejection
Ratio vs. Frequency (with bypass capacitor).
FIGURE 2-18:
V
OUT1
and V
OUT2
Noise vs.
Frequency (without bypass capacitor).
2.808
2.816
2.824
2.832
2.840
2.848
2.856
-40 -25 -10
5
20
35
50
65
80 95 110 125
Junction Temperature (C)
O
u
t
put
V
o
lt
age V
OU
T
1
(V)
V
R1
= 2.8V, I
OUT1
= 300 mA
V
R2
= 2.6V, I
OUT2
= 100 A
V
IN
= 6.0V
V
IN
= 4.2V
V
IN
= 3.0V
2.615
2.620
2.625
2.630
2.635
2.640
2.645
-40 -25 -10
5
20
35
50
65
80 95 110 125
Junction Temperature (C)
O
u
t
put
V
o
lt
age V
OU
T
2
(V)
V
IN
= 4.2V
V
R1
= 2.8V, I
OUT1
= 100 A
V
R2
= 2.6V
I
OUT2
= 150 mA
I
OUT2
= 100 A
I
OUT2
= 50 mA
2.624
2.628
2.632
2.636
2.640
2.644
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (C)
Output V
o
ltage V
OUT
2
(V
)
V
R1
= 2.8V, I
OUT1
= 100 A
V
R2
= 2.6V, I
OUT2
= 150 mA
V
IN
= 6.0V
V
IN
= 3.0V
V
IN
= 4.2V
0.01
0.1
1
10
0.01
0.1
1
10
100
1000
Frequency (KHz)
NOISE (V/
Hz)
V
IN
= 4.2V
V
R1
= 2.8V
V
R2
=2.6V
I
OUT1
= 150 mA
I
OUT2
= 100 mA
C
BYPASS
= 0 nF
V
OUT1
V
OUT2
TC1302A/B
DS21333B-page 8
2005 Microchip Technology Inc.
Note: Unless otherwise indicated,
V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F, C
OUT1 =
C
OUT2
= 1 F (X5R or X7R),
C
BYPASS
= 0 pF, SHDN1 = SHDN2 > V
IH
, T
A
= +25C.
FIGURE 2-19:
V
OUT1
and V
OUT2
Noise vs.
Frequency (with bypass capacitor).
FIGURE 2-20:
V
OUT1
and V
OUT2
Power-up
from Shutdown TC1302B.
FIGURE 2-21:
V
OUT2
Power-up from
Shutdown Input TC1302A.
FIGURE 2-22:
V
OUT1
and V
OUT2
Power-up
from Input Voltage TC1302B.
FIGURE 2-23:
Dynamic Line Response.
FIGURE 2-24:
300 mA Dynamic Load Step
V
OUT1
.
0.001
0.01
0.1
1
10
0.01
0.1
1
10
100
1000
Frequency (KHz)
NOISE (V/
Hz)
V
IN
= 4.2V
V
R1
= 2.8V
V
R2
=2.6V
I
OUT1
= 150 mA
I
OUT2
= 100 mA
C
BYPASS
= 10 nF
V
OUT1
V
OUT2
2005 Microchip Technology Inc.
DS21333B-page 9
TC1302A/B
Note: Unless otherwise indicated,
V
IN
= V
R
+1V, I
OUT1
=
I
OUT2
= 100 A, C
IN
= 4.7 F, C
OUT1 =
C
OUT2
= 1 F (X5R or X7R),
C
BYPASS
= 0 pF, SHDN1 = SHDN2 > V
IH
, T
A
= +25C.
FIGURE 2-25:
150 mA Dynamic Load Step
V
OUT2
.
TC1302A/B
DS21333B-page 10
2005 Microchip Technology Inc.
3.0
TC1302A PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
TC1302A PIN FUNCTION TABLE
3.1
Regulated Output Voltage #1
(V
OUT1
)
Connect V
OUT1
to the positive side of the V
OUT1
capacitor and load. Capable of 300 mA maximum
output current. V
OUT1
output is available when V
IN
is
available; there is no pin to turn it OFF. See TC1302B
if ON/OFF control of V
OUT1
is desired.
3.2
Circuit Ground Pin (GND)
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 A maximum).
3.3
Reference Bypass Input
By connecting an external 10 nF capacitor (typical) to
the Bypass Input, both outputs (V
OUT1
and V
OUT2
) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage start-up time will increase with the addition of
an external bypass capacitor. By leaving this pin
unconnected, the start-up time will be minimized.
3.4
Output Voltage #2 Shutdown
(SHDN2)
ON/OFF control is performed by connecting SHDN2 to
its proper level. When the input of this pin is connected
to a voltage less than 15% of V
IN
, V
OUT2
will be OFF. If
this pin is connected to a voltage that is greater than
45% of V
IN
, V
OUT2
will be turned ON.
3.5
Regulated Output Voltage #2
(V
OUT2
)
Connect V
OUT2
to the positive side of the V
OUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. V
OUT2
can be turned ON and
OFF using SHDN2.
3.6
Unregulated Input Voltage Pin
(V
IN
)
Connect the unregulated input voltage source to V
IN
. If
the input voltage source is located more than several
inches away or is a battery, a typical input capacitance
of 1 F to 4.7 F is recommended.
Pin No.
Name
Function
1
NC
No connect.
2
V
OUT1
Regulated output voltage #1, capable of 300 mA.
3
GND
Circuit ground pin.
4
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
5
SHDN2
Output #2 shutdown control input.
6
V
OUT2
Regulated output voltage #2, capable of 150 mA.
7
V
IN
Unregulated input voltage pin.
8
NC
No connect.
2005 Microchip Technology Inc.
DS21333B-page 11
TC1302A/B
4.0
TC1302B PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
TC1302B PIN FUNCTION TABLE
4.1
Regulated Output Voltage #1
(V
OUT1
)
Connect V
OUT1
to the positive side of the V
OUT1
capacitor and load. Capable of 300 mA maximum
output current. For the TC1302B, V
OUT1
can be turned
ON and OFF using the SHDN1 input pin.
4.2
Circuit Ground Pin (GND)
Connect GND to the negative side of the input and
output capacitor. Only the LDO internal circuitry bias
current flows out of this pin (200 A maximum).
4.3
Reference Bypass Input
By connecting an external 10 nF capacitor (typical) to
the bypass input, both outputs (V
OUT1
and V
OUT2
) will
have less noise and improved Power Supply Ripple
Rejection (PSRR) performance. The LDO output
voltage startup time will increase with the addition of an
external bypass capacitor. By leaving this pin
unconnected, the startup time will be minimized.
4.4
Output Voltage #2 Shutdown
(SHDN2)
ON/OFF control is performed by connecting SHDN2 to
its proper level. When this pin is connected to a voltage
less than 15% of V
IN
, V
OUT2
will be OFF. If this pin is
connected to a voltage that is greater than 45% of V
IN
,
V
OUT2
will be turned ON.
4.5
Regulated Output Voltage #2
(V
OUT2
)
Connect V
OUT2
to the positive side of the V
OUT2
capacitor and load. This pin is capable of a maximum
output current of 150 mA. V
OUT2
can be turned ON and
OFF using SHDN2.
4.6
Unregulated Input Voltage Pin
(V
IN
)
Connect the unregulated input voltage source to V
IN
. If
the input voltage source is located more than several
inches away, or is a battery, a typical minimum input
capacitance of 1 F and 4.7 F is recommended.
4.7
Output Voltage #1 Shutdown
(SHDN1)
ON/OFF control is performed by connecting SNDN1 to
its proper level. When this pin is connected to a voltage
less than 15% of V
IN
, V
OUT1
will be OFF. If this pin is
connected to a voltage that is greater than 45% of V
IN
,
V
OUT1
will be turned ON.
Pin No.
Name
Function
1
NC
No connect.
2
V
OUT1
Regulated output voltage #1, capable of 300 mA.
3
GND
Circuit ground pin.
4
Bypass
Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce
output noise and improve PSRR performance.
5
SHDN2
Output #2 shutdown control input.
6
V
OUT2
Regulated output voltage #2, capable of 150 mA.
7
V
IN
Unregulated Input voltage pin.
8
SHDN1
Output #1 shutdown control input.
TC1302A/B
DS21333B-page 12
2005 Microchip Technology Inc.
5.0
DETAILED DESCRIPTION
5.1
Device Overview
The TC1302A/B is a combination device consisting of
one 300 mA LDO regulator with a fixed output voltage
V
OUT1
(1.5V 3.3V) and one 150 mA LDO regulator
with a fixed output voltage V
OUT2
(1.5V 3.3V).
For the TC1302A, the 300 mA output (V
OUT1
) is always
present, independent of the level of SHDN2. The
150 mA output (V
OUT2
) can be turned ON/OFF by
controlling the level of SHDN2.
For the TC1302B, V
OUT1
and V
OUT2
each have
independent shutdown input pins (SHDN1 and
SHDN2) to control their respective outputs.
5.2
LDO Output #1
LDO output #1 is rated for 300 mA of output current.
The typical dropout voltage for V
OUT1
= 104 mV @
300 mA. A 1 F (minimum) output capacitor is needed
for stability and should be located as close to the V
OUT1
pin and ground as possible.
5.3
LDO Output #2
LDO output #2 is rated for 150 mA of output current.
The typical dropout voltage for V
OUT2
= 150 mV. A 1 F
(minimum) capacitor is needed for stability and should
be located as close to the V
OUT2
pin and ground as
possible.
5.4
Input Capacitor
Low input source impedance is necessary for the two
LDO outputs to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 F to 4.7 F is recommended for most
applications. When using large capacitors on the LDO
outputs, larger capacitance is recommended on the
LDO input. The capacitor should be placed as close to
the input of the LDO as is practical. Larger input
capacitors will help reduce the input impedance and
further reduce any high-frequency noise on the input
and output of the LDO.
5.5
Output Capacitor
A minimum output capacitance of 1 F for each of the
TC1302A/B LDO outputs is necessary for stability.
Ceramic capacitors are recommended because of their
size, cost and environmental robustness qualities.
Tantalum or aluminum electrolytic capacitors can be
used on the LDO outputs as well. The Equivalent
Series Resistance (ESR) requirements on the
electrolytic output capacitor's are between 0 and 2
ohms. The output capacitor should be located as close
to the LDO output as is practical. Ceramic materials,
X7R and X5R, have low temperature coefficients and
are well within the acceptable ESR range required. A
typical 1 uF X5R 0805 capacitor has an ESR of 50 milli-
ohms. Larger LDO output capacitors can be used with
the TC1302A/B to improve dynamic performance and
power supply ripple rejection performance. A maximum
of 10 F is recommended. Aluminum electrolytic
capacitors are not recommended for low temperature
applications of < -25 C.
5.6
Bypass Input
The Bypass pin is connected to the internal LDO
reference. By adding capacitance to this pin, the LDO
ripple rejection, input voltage transient response and
output noise performance are all increased. A typical
bypass capacitor between 470 pF to 10 nF is
recommended. Larger bypass capacitors can be used,
but result in a longer time period for the LDO outputs to
reach their rated output voltage when started from
SHDN or V
IN
.
5.7
GND
For the optimal noise and PSRR performance, the
GND pin of the TC1302A/B should be tied to a quiet
circuit ground. For applications that have switching or
noisy inputs, tie the GND pin to the return of the output
capacitor. Ground planes help lower inductance and
voltage spikes caused by fast transient load currents
and are recommended for applications that are
subjected to fast load transients.
5.8
SHDN1/SHDN2 Operation
The TC1302A SHDN2 pin is used to turn V
OUT2
ON
and OFF. A logic-high level on SHDN2 will enable the
V
OUT2
output, while a logic-low on the SHDN2 pin will
disable the V
OUT2
output. For the TC1302A, V
OUT1
is
not affected by SHDN2 and will be enabled as long as
the input voltage is present.
The TC1302B SHDN1 and SHDN2 pins are used to
turn V
OUT1
and V
OUT2
ON and OFF. They operate
independent of each other.
2005 Microchip Technology Inc.
DS21333B-page 13
TC1302A/B
5.9
TC1302A SHDN2 Timing
V
OUT1
will rise independent of the level of SHDN2 for
the TC1302A. Figure 5-1 is used to define the wake-up
time from shutdown (t
WK
) and the settling time (t
S
). The
wake-up time is dependant upon the frequency of
operation. The faster the SHDN pin is pulsed, the
shorter the wake-up time will be.
FIGURE 5-1:
TC1302A Timing.
5.10
TC1302B SHDN1/SHDN2 Timing
For the TC1302B, the SHDN1 input pin is used to
control V
OUT1
. The SHDN2 input pin is used to control
V
OUT2
, independent of the logic input on SHDN1.
FIGURE 5-2:
TC1302B Timing.
5.11
Device Protection
5.11.1
OVERCURRENT LIMIT
In the event of a faulted output load, the maximum
current the LDO output will permit to flow is limited
internally for each of the TC1302A/B outputs. The peak
current limit for V
OUT1
is typically 1.1A, while the peak
current limit for V
OUT2
is typically 0.5A. During short-
circuit operation, the average current is limited to
200 mA for V
OUT1
and 140 mA for V
OUT2
.
5.11.2
OVERTEMPERATURE
PROTECTION
If the internal power dissipation within the TC1302A/B
is excessive due to a faulted load or higher-than-
specified line voltage, an internal temperature-sensing
element will prevent the junction temperature from
exceeding approximately 150
C. If the junction
temperature does reach 150
C, both outputs will be
disabled until the junction temperature cools to
approximately 140
C and the device resumes normal
operation. If the internal power dissipation continues to
be excessive, the device will again shut off.
V
IN
SHDN2
V
OUT1
V
OUT2
t
wk
t
s
SHDN2
SHDN1
V
IN
V
OUT1
t
wk
t
s
V
OUT2
TC1302A/B
DS21333B-page 14
2005 Microchip Technology Inc.
6.0
APPLICATION CIRCUITS/
ISSUES
6.1
Typical Application
The TC1302A/B is used for applications that require
the integration of two LDOs.
FIGURE 6-1:
Typical Application Circuit
TC1302A/B.
6.1.1
APPLICATION INPUT CONDITIONS
6.2
Power Calculations
6.2.1
POWER DISSIPATION
The internal power dissipation within the TC1302A/B is
a function of input voltage, output voltage, output
current and quiescent current. The following equation
can be used to calculate the internal power dissipation
for each LDO.
EQUATION 6-1:
In addition to the LDO pass element power dissipation,
there is power dissipation within the TC1302A/B as a
result of quiescent or ground current. The power
dissipation, as a result of the ground current, can be
calculated using the following equation.
EQUATION 6-2:
The total power dissipated within the TC1302A/B is the
sum of the power dissipated in both of the LDOs and
the P(I
GND
) term. Because of the CMOS construction,
the typical I
GND
for the TC1302A/B is 116 A.
Operating at a maximum of 4.2V results in a power
dissipation of 0.5 milliWatts. For most applications, this
is small compared to the LDO pass device power dissi-
pation and can be neglected.
The maximum continuous operating junction
temperature specified for the TC1302A/B is +125
C
.
To
estimate the internal junction temperature of the
TC1302A/B, the total internal power dissipation is
multiplied by the thermal resistance from junction to
ambient (R
JA
) of the device. The thermal resistance
from junction-to-ambient for the 3x3DFN8 pin package
is estimated at 41
C/W.
EQUATION 6-3:
Package Type = 3x3DFN8
Input Voltage Range = 2.7V to 4.2V
V
IN
maximum = 4.2V
V
IN
typical = 3.6V
V
OUT1
= 300 mA maximum
V
OUT2
= 150 mA maximum
8
4
1
2
3
NC
GND
NC
BATTERY
C
OUT1
1 F Ceramic
X5R
C
IN
1 F
TC1302A
C
OUT2
1 F Ceramic
X5R
C
bypass
10 nF Ceramic
Bypass
V
IN
7
2.7V
to
4.2V
V
OUT2
6
SHDN2
ON/OFF Control V
OUT2
2.8V @ 300 mA
1.8V
5
V
OUT1
8
4
1
2
3
NC
BATTERY
C
OUT1
1 F Ceramic
X5R
C
IN
1 F
TC1302B
C
OUT2
1 F Ceramic
X5R
Bypass
V
IN
7
2.7V
to
4.2V
V
OUT2
6
SHDN2
ON/OFF Control V
OUT2
2.8V @ 300 mA
1.8V
5
ON/OFF Control V
OUT1
V
OUT1
@ 150 mA
GND
@ 150 mA
SHDN1
P
LDO
V
IN MAX
)
(
)
V
OUT MIN
(
)
(
) I
OUT MAX
)
(
)
=
P
LDO
= LDO Pass device internal power
dissipation
V
IN(MAX)
= Maximum input voltage
V
OUT(MIN)
= LDO minimum output voltage
P
I GND
(
)
V
IN MAX
(
)
I
V IN
=
P
I(GND)
= Total current in ground pin.
V
IN(MAX)
= Maximum input voltage.
I
VIN
= Current flowing in the V
IN
pin with
no output current on either LDO output.
T
J MAX
(
)
P
TOTAL
R
JA
T
AMAX
+
=
T
J(MAX)
= Maximum continuous junction
temperature.
P
TOTAL
= Total device power dissipation.
R
JA
= Thermal resistance from junction
to ambient.
T
AMAX
= Maximum Ambient Temperature.
2005 Microchip Technology Inc.
DS21333B-page 15
TC1302A/B
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. The following equation
can be used to determine the package maximum
internal power dissipation.
EQUATION 6-4:
EQUATION 6-5:
EQUATION 6-6:
6.3
Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
are calculated in the following example. The power
dissipation, as a result of ground current, is small
enough to be neglected.
6.3.1
POWER DISSIPATION EXAMPLE
Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction to ambient for the application. The
thermal resistance from junction to ambient (R
JA
) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7 "High
Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages". The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors, such as copper area and
thickness. Refer to AN792, "A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application", (DS00792), for more information
regarding this subject.
Junction Temperature Estimate
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below.
Maximum Package Power Dissipation at 50C
Ambient Temperature
Package
Package Type = 3x3DFN8
Input Voltage
V
IN
= 2.7V to 4.2V
LDO Output Voltages and Currents
V
OUT1
= 2.8V
I
OUT1
= 300 mA
V
OUT2
= 1.8V
I
OUT2
= 150 mA
P
D MAX
(
)
T
J MAX
(
)
T
A MAX
(
)
(
)
R
JA
---------------------------------------------------
=
P
D(MAX)
= maximum device power dissipation.
T
J(MAX)
= maximum continuous junction
temperature.
T
A(MAX)
= maximum ambient temperature.
R
JA
= Thermal resistance from junction to
ambient.
T
J RISE
(
)
P
D MAX
(
)
R
J A
=
T
J(RISE)
= Rise in device junction temperature over
the ambient temperature.
P
D(MAX)
= Maximum device power dissipation.
R
JA
= Thermal resistance from junction-to-
ambient.
T
J
T
J RISE
(
)
T
A
+
=
T
J
= Junction temperature.
T
J(RISE)
= Rise in device junction temperature over
the ambient temperature.
T
A
= Ambient Temperature.
Maximum Ambient Temperature
T
A(MAX)
= 50C
Internal Power Dissipation
Internal power dissipation is the sum of the power
dissipation for each LDO pass device.
P
LDO1(MAX)
= (V
IN(MAX)
- V
OUT1(MIN)
) x
I
OUT1(MAX)
P
LDO1
= (4.2V - (0.975 x 2.8V)) x 300 mA
P
LDO1
= 441.0 milliWatts
P
LDO2
= (4.2V - (0.975 X 1.8V)) x 150 mA
P
LDO2
= 366.8 milliWatts
P
TOTAL
= P
LDO1
+ P
LDO2
P
TOTAL
= 807.8 milliWatts
T
J(RISE)
= P
TOTAL
x Rq
JA
T
JRISE
= 807.8 milliWatts x 41.0
C/W
T
JRISE
= 33.1
C
T
J
= T
JRISE
+ T
A(MAX)
T
J
= 83.1C
3x3DFN8 (41C/Watt R
JA
)
P
D(MAX)
= (125C - 50C)/41 C/W
P
D(MAX)
= 1.83 Watts
MSOP8 (208C/Watt R
JA
)
P
D(MAX)
= (125C - 50C)/208 C/W
P
D(MAX)
= 0.360 Watts
TC1302A/B
DS21333B-page 16
2005 Microchip Technology Inc.
7.0
TYPICAL LAYOUT
FIGURE 7-1:
MSOP8 Silk-screen Layer.
When designing the physical layout for the TC1302A/B,
the highest priority should be placed on positioning the
input and output capacitors as close to the device pins
as is practical. Figure 7-1 above represents a typical
placement of the components when using the SMT0805
capacitors.
FIGURE 7-2:
DFN3x3 Silk-screen
Example.
Figure 7-2 above represents a typical placement of the
components when using the SMT0603 capacitors.
8.0
ADDITIONAL OUTPUT
VOLTAGES
8.1
Output Voltage Options
Table 8-1 describes the range of output voltage options
available for the TC1302A/B. V
OUT1
and V
OUT2
can be
factory preset from 1.5V to 3.3V in 100 mV increments.
TABLE 8-1:
CUSTOM OUTPUT
VOLTAGES
For a listing of TC1302A/B standard parts, refer to the
Product Identification System on page 23.
V
OUT1
V
OUT2
1.5V to 3.3V
1.5V to 3.3V
2005 Microchip Technology Inc.
DS21333B-page 17
TC1302A/B
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
X1 represents V
OUT1
configuration:
X2 represents V
OUT2
configuration:
For a listing of TC1302A/B standard parts, refer to the
Product Identification System on page 23.
8-Lead MSOP
XXXXXX
YWWNNN
Example:
BFH
0542
256
Example:
32AFH
542256
8-Lead DFN
XXXX
YYWW
NNN
-- 32A = TC1302A
-- F = 2.8V V
OUT1
-- H = 2.6V V
OUT2
Code
V
OUT1
Code
V
OUT1
Code
V
OUT1
A
3.3V
J
2.4V
S
1.5V
B
3.2V
K
2.3V
T
1.65V
C
3.1V
L
2.2V
U
2.85V
D
3.0V
M
2.1V
V
2.65V
E
2.9V
N
2.0V
W
1.85V
F
2.8V
O
1.9V
X
--
G
2.7V
P
1.8V
Y
--
H
2.6V
Q
1.7V
Z
--
I
2.5V
R
1.6V
Code
V
OUT2
Code
V
OUT1
Code
V
OUT2
A
3.3V
J
2.4V
S
1.5V
B
3.2V
K
2.3V
T
1.65V
C
3.1V
L
2.2V
U
2.85V
D
3.0V
M
2.1V
V
2.65V
E
2.9V
N
2.0V
W
1.85V
F
2.8V
O
1.9V
X
--
G
2.7V
P
1.8V
Y
--
H
2.6V
Q
1.7V
Z
--
I
2.5V
R
1.6V
Legend: XX...X
Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
Week code (week of January 1 is week `01')
NNN
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
TC1302A/B
DS21333B-page 18
2005 Microchip Technology Inc.
8-Lead Plastic Micro Small Outline Package (UA) (MSOP)
D
A
A1
L
c
(F)
A2
E1
E
p
B
n
1
2
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REF
F
Footprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
c
B
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016
.024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0
0.23
0.40
8
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX
NOM
1.10
0.80
0.15
0.95
MAX
8
-
-
-
15
5
-
15
5
-
JEDEC Equivalent: MO-187
0
-
8
5
5
-
-
15
15
-
-
-
-
2005 Microchip Technology Inc.
DS21333B-page 19
TC1302A/B
8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN)
E2
D
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
Exposed Pad Width
Exposed Pad Length
Lead Length
*Controlling Parameter
Lead Width
Drawing No. C04-062
Notes:
Exposed pad dimensions vary with paddle size.
exceed .010" (0.254mm) per side.
Overall Width
D2
E2
L
b
D
.019
.012
.007
.047
.055
.010
.118 BSC
A1
Number of Pins
Standoff
Lead Thickness
Overall Length
Overall Height
Pitch
A
A3
p
n
Units
A
A1
E
A3
Dimension Limits
8
.000
.001
.008 REF.
.118 BSC
.031
.026 BSC
MIN
INCHES
NOM
TOP VIEW
EXPOSED
METAL
PAD
0.48
0.26
3.00 BSC
0.30
.022
.069
.015
.096
0.23
1.20
1.39
0.55
0.37
1.75
2.45
0.02
0.80
3.00 BSC
0.20 REF.
0.65 BSC
MILLIMETERS*
.002
.039
0.00
MIN
MAX
NOM
8
0.05
1.00
MAX
BOTTOM VIEW
2
1
ID INDEX
PIN 1
E
L
D2
p
b
n
3.
4.
Package may have one or more exposed tie bars at ends.
1.
AREA
Pin 1 visual index feature may vary, but must be located within the hatched area.
2.
(NOTE 2)
TIE BAR
(NOTE 1)
EXPOSED
0.90
.035
(Note 4)
(Note 4)
5. JEDEC equivalent: Pending
TC1302A/B
DS21333B-page 20
2005 Microchip Technology Inc.
NOTES:
2005 Microchip Technology Inc.
DS21333B-page 21
TC1302A/B
APPENDIX A:
REVISION HISTORY
Revision B (January 2005)
The following is the list of modifications:
1.
Correct the incorrect part number options shown
on the Product Identification System page and
change the "standard" output voltage and reset
voltage combinations.
2.
Added Appendix A: Revision History.
Revision A (September 2003)
Original data sheet release.
TC1302A/B
DS21333B-page 22
2005 Microchip Technology Inc.
NOTES:
2005 Microchip Technology Inc.
DS21333B-page 23
TC1302A/B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
Device:
TC1302A: Dual Output LDO with Single Shutdown input.
TC1302B: Dual Output LDO with Dual Shutdown Inputs.
Standard
Configurations: *
V
OUT1
/V
OUT2
Configuration
Code
TC1302A
3.0/1.65
DT
TC1302B
3.0/1.65
2.6/1.8
2.5/1.8
DT
HP
IP
* Contact Factory for Alternate Output Voltage
Configurations.
Temperature Range:
V
= -40C to +125C
Package:
MF
= Dual Flat, No Lead (3x3 mm body), 8-lead
UA
= Plastic Micro Small Outline (MSOP), 8-lead
Tube or
Tape and Reel:
Blank
= Tube
TR
= Tape and Reel
Examples:
a)
TC1302ADTVMF:
3.0, 1.65,
8LD DFN pkg.
a)
TC1302BDTVMF:
3.0, 1.65,
8LD DFN pkg.
b)
TC1302BHPVMFTR:
2.6, 1.8,
8LD DFN pkg,
Tape and Reel.
c)
TC1302BIPVUA:
2.5, 1.8,
8LD MSOP pkg.
PART NO.
X-
X
V
OUT1
Type
A/B
TC1302
X
V
OUT2
X
Temp
Range
XX
Package
XX
Tube
or
Tape &
Reel
Standard
Configurations
TC1302A/B
DS21333B-page 24
2005 Microchip Technology Inc.
NOTES:
2005 Microchip Technology Inc.
DS21333B-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip's products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EE
L
OQ
, micro
ID
, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel and Total
Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2005, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable."
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company's quality system processes and
procedures are for its PICmicro
8-bit MCUs, K
EE
L
OQ
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip's quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21333B-page 26
2005 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westford, MA
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
San Jose
Mountain View, CA
Tel: 650-215-1444
Fax: 650-961-0286
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Qingdao
Tel: 86-532-502-7355
Fax: 86-532-502-7205
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
India - New Delhi
Tel: 91-11-5160-8631
Fax: 91-11-5160-8632
Japan - Kanagawa
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Taiwan - Hsinchu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
EUROPE
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Massy
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Ismaning
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
England - Berkshire
Tel: 44-118-921-5869
Fax: 44-118-921-5820
W
ORLDWIDE
S
ALES
AND
S
ERVICE
10/20/04
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