2002 Microchip Technology Inc.
DS21425B-page 1
M
TC4467/TC4468/TC4469
Features
High Peak Output Current: 1.2 A
Wide Operating Range:
- 4.5 V to 18 V
Symmetrical Rise/Fall Times: 25 nsec
Short, Equal Delay Times: 75 nsec
Latch-proof. Will Withstand 500 mA Inductive
Kickback
3 Input Logic Choices:
- AND / NAND / AND + Inv
ESD Protection on All Pins: 2 kV
Applications
General Purpose CMOS Logic Buffer
Driving All Four MOSFETs in an H-Bridge
Direct Small Motor Driver
Relay or Peripheral Drivers
CCD Driver
Pin-Switching Network Driver
Package Types
General Description
The TC4467/TC4468/TC4469 devices are a family of
four-output CMOS buffers/MOSFET drivers with 1.2 A
peak drive capability. Unlike other MOSFET drivers,
these devices have two inputs for each output. The
inputs are configured as logic gates: NAND (TC4467),
AND (TC4468) and AND/INV (TC4469).
The TC4467/TC4468/TC4469 drivers can continuously
source up to 250 mA into ground referenced loads.
These devices are ideal for direct driving low current
motors or driving MOSFETs in a H-bridge configuration
for higher current motor drive (see Section 5.0 for
details). Having the logic gates onboard the driver can
help to reduce component count in many designs.
The TC4467/TC4468/TC4469 devices are very robust
and highly latch-up resistant. They can tolerate up to
5 V of noise spiking on the ground line and can handle
up to 0.5 A of reverse current on the driver outputs.
The TC4467/4468/4469 devices are available in
commercial, industrial and military temperature ranges.
1
2
3
4
5
6
7
8
16
13
12
11
10
9
1A
1B
2A
2B
3A
3B
GND
GND
V
DD
1Y
2Y
3Y
4Y
4B
4A
V
DD
15
14
TC4467
TC4468
TC4469
16-Pin SOIC (Wide)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
3A
3B
GND
V
DD
1Y
2Y
3Y
4Y
4B
4A
TC4467
TC4468
TC4469
14-Pin PDIP/CERDIP
Logic-Input CMOS Quad Drivers
2002 Microchip Technology Inc.
DS21425B-page 3
TC4467/TC4468/TC4469
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
Supply Voltage ...............................................................+20 V
Input Voltage ............................. (GND 5 V) to (V
DD
+ 0.3 V)
Package Power Dissipation: (T
A
70C)
PDIP...................................................................800 mW
CERDIP .............................................................840 mW
SOIC ..................................................................760 mW
Package Thermal Resistance:
CERDIP R
J-A
...................................................100C/W
CERDIP R
J-C
.....................................................23C/W
PDIP R
J-A
..........................................................80C/W
PDIP R
J-C
..........................................................35C/W
SOIC R
J-A
..........................................................95C/W
SOIC R
J-C
..........................................................28C/W
Operating Temperature Range:
C Version ................................................... 0C to +70C
E Version.................................................-40C to +85C
M Version ..............................................-55C to +125C
Maximum Chip Temperature....................................... +150C
Storage Temperature Range.........................-65C to +150C
Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, T
A
= +25C, with 4.5 V
V
DD
18 V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input
Logic 1, High Input Voltage
V
IH
2.4
--
V
DD
V
Note 3
Logic 0, Low Input Voltage
V
IL
--
--
0.8
V
Note 3
Input Current
I
IN
-1.0
--
+1.0
A
0 V
V
IN
V
DD
Output
High Output Voltage
V
OH
V
DD
0.025
--
--
V
I
LOAD
= 100 A (Note 1)
Low Output Voltage
V
OL
--
--
0.15
V
I
LOAD
= 10 mA (Note 1)
Output Resistance
R
O
--
10
15
I
OUT
= 10 mA, V
DD
= 18 V
Peak Output Current
I
PK
--
1.2
--
A
Continuous Output Current
I
DC
--
--
300
mA
Single Output
--
--
500
Total Package
Latch-Up Protection Withstand
Reverse Current
I
--
500
--
mA
4.5 V
V
DD
16 V
Switching Time (Note 1)
Rise Time
t
R
--
15
25
nsec
Figure 4-1
Fall Time
t
F
--
15
25
nsec
Figure 4-1
Delay Time
t
D1
--
40
75
nsec
Figure 4-1
Delay Time
t
D2
--
40
75
nsec
Figure 4-1
Power Supply
Power Supply Current
I
S
--
1.5
4
mA
Power Supply Voltage
V
DD
4.5
--
18
V
Note 2
Note
1:
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
2:
When driving all four outputs simultaneously in the same direction, V
DD
will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
3:
The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 sec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
TC4467/TC4468/TC4469
DS21425B-page 4
2002 Microchip Technology Inc.
ELECTRICAL SPECIFICATIONS (OPERATING TEMPERATURES)
TRUTH TABLE
Electrical Characteristics: Unless otherwise noted, over operating temperature range with 4.5 V
V
DD
18 V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input
Logic 1, High Input Voltage
V
IH
2.4
--
--
V
Note 3
Logic 0, Low Input Voltage
V
IL
--
--
0.8
V
Note 3
Input Current
I
IN
-10
--
10
A
0 V
V
IN
V
DD
Output
High Output Voltage
V
OH
V
DD
0.025
--
--
V
I
LOAD
= 100 A (Note 1)
Low Output Voltage
V
OL
--
--
0.30
V
I
LOAD
= 10 mA (Note 1)
Output Resistance
R
O
--
20
30
I
OUT
= 10 mA, V
DD
= 18 V
Peak Output Current
I
PK
--
1.2
--
A
Continuous Output Current
I
DC
--
--
300
mA
Single Output
--
--
500
Total Package
Latch-Up Protection Withstand
Reverse Current
I
--
500
--
mA
4.5 V
V
DD
16 V
Switching Time (Note 1)
Rise Time
t
R
--
15
50
nsec
Figure 4-1
Fall Time
t
F
--
15
50
nsec
Figure 4-1
Delay Time
t
D1
--
40
100
nsec
Figure 4-1
Delay Time
t
D2
--
40
100
nsec
Figure 4-1
Power Supply
Power Supply Current
I
S
--
--
8
mA
Power Supply Voltage
V
DD
4.5
--
18
V
Note 2
Note
1:
Totem pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device. Switching
times are ensured by design.
2:
When driving all four outputs simultaneously in the same direction, V
DD
will be limited to 16 V. This reduces the chance that internal dv/dt
will cause high-power dissipation in the device.
3:
The input threshold has approximately 50 mV of hysteresis centered at approximately 1.5 V. Input rise times should be kept below 5 sec
to avoid high internal peak currents during input transitions. Static input levels should also be maintained above the maximum, or below
the minimum, input levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
Part No.
TC4467 NAND
TC4468 AND
TC4469 AND/INV
Inputs A
H
H
L
L
H
H
L
L
H
H
L
L
Inputs B
H
L
H
L
H
L
H
L
H
L
H
L
Outputs TC446X
L
H
H
H
H
L
L
L
L
H
L
L
Legend: H = High L = Low
2002 Microchip Technology Inc.
DS21425B-page 5
TC4467/TC4468/TC4469
2.0
TYPICAL PERFORMANCE CURVES
Note:
T
A
= +25C, with 4.5 V
V
DD
18 V.
FIGURE 2-1:
Rise Time vs. Supply
Voltage.
FIGURE 2-2:
Rise Time vs. Capacitive
Load.
FIGURE 2-3:
Rise/Fall Times vs.
Temperature.
FIGURE 2-4:
Fall Time vs. Supply
Voltage.
FIGURE 2-5:
Fall Time vs. Capacitive
Load.
FIGURE 2-6:
Propagation Delay Time vs.
Supply Voltage.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
140
120
100
80
60
40
20
0
3
5
7
9
11
13
15
17
19
2200 pF
0 p
p
1600 pF
1000 pF
470 pF
100 pF
t
R
I
SE
(
nsec
)
V
SUPPLY
(V)
140
120
100
80
60
40
20
0
100
1000
10,000
10 V
15 V
V
V
V
5 V
t
R
I
SE
(
nsec
)
C
LOAD
(pF)
0
-50
TIME
(
nsec
)
5
10
15
20
25
-25
0
25
50
75
100
125
t
FALL
t
RISE
V
SUPPLY
= 17.5 V
C
LOAD
= 470 pF
TEMPERATURE (
C)
140
120
100
80
60
40
20
0
3
5
7
9
11
13
15
17
19
p
100 pF
470 pF
1000 pF
1500 pF
2200 pF
t
FALL
(
nsec
)
V
SUPPLY
(V)
140
120
100
80
60
40
20
0
100
0
0
1000
10,000
V
V
V
5 V
10 V
15 V
t
FALL
(
nsec
)
C
LOAD
(pF)
0
4
D
ELAY TIME
(
nsec
)
20
40
60
80
8
12
14
16
18
6
10
V
SUPPLY
(V)
t
t
D1
t
D2
C
C
LOAD
470 pF
= 4
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