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2002 Microchip Technology Inc.

DS21463B-page 1

Features

· Low Input Offset Voltage: 0.7µV Typ

· Low Input Offset Voltage Drift: 0.05

V/°C Max

· Low Input Bias Current: 10pA Max

· High Impedance Differential CMOS Inputs: 10

· High Open Loop Voltage Gain: 120dB Min.

· Low Input Noise Voltage: 2.0

Vp-p

· High Slew Rate: 2.5V/

sec.

· Low Power Operation: 20mW

· Output Clamp Speeds Recovery Time

· Compensated Internally for Stable Unity Gain

Operation

· Direct Replacement for ICL7650

· Available in 8-Pin Plastic DIP and 14-Pin Plastic

DIP Packages

Applications

· Instrumentation

· Medical Instrumentation

· Embedded Control

· Temperature Sensor Amplifier

· Strain Gage Amplifier

Device Selection Table

Package Type

Part

Number

Package

Temperature

Range

Max V

TC7650CPA

8-Pin PDIP

0°C to +70°C

TC7650CPD 14-Pin PDIP

0°C to +70°C

8-Pin DIP

INT/EXT

EXT CLK IN

INT CLK OUT

OUTPUT

OUTPUT CLAMP

RETN

TC7650CPD

OUTPUT

TC7650CPA

INPUT

OUTPUT CLAMP

INPUT

14-Pin DIP

NC = NO INTERNAL CONNECTION

TC7650

Chopper Stabilized Operational Amplifier

TC7650

DS21463B-page 2

2002 Microchip Technology Inc.

General Description

The TC7650 CMOS chopper stabilized operational
amplifier practically removes offset voltage error terms
from system error calculations. The 5

V maximum V

specification, for example, represents a 15 times
improvement over the industry standard OP07E. The
50nV/°C offset drift specification is over 25 times lower
than the OP07E. The increased performance elimi-
nates V

trim procedures, periodic potentiometer

adjustment and the reliability problems caused by dam-
aged trimmers.

The TC7650 performance advantages are achieved
without the additional manufacturing complexity and
cost incurred with laser or "zener zap" V

trim tech-

niques.

The TC7650 nulling scheme corrects both DC V

errors and V

drift errors with temperature. A nulling

amplifier alternately corrects its own V

errors and the

main amplifier V

error. Offset nulling voltages are

stored on two user supplied external capacitors. The
capacitors connect to the internal amplifier V

null

points. The main amplifier input signal is never
switched. Switching spikes are not present at the
TC7650 output.

The 14-pin dual-in-line package (DIP) has an external
oscillator input to drive the nulling circuitry for optimum
noise performance. Both the 8 and 14-pin DIPs have
an output voltage clamp circuit to minimize overload
recovery time.

Functional Block Diagram

TC7650

Null

NULL

Inputs

Output

Clamp

Output

For 8-Pin DIP, connect to Vss

Null
Amplifier

Main
Amplifier

Output Clamp

Circuit

Intermod

Compensation

Oscillator

INT/EXT
EXT CLK IN
CLK OUT

14-Pin DIP Only

RETN

2002 Microchip Technology Inc.

DS21463B-page 3

TC7650

1.0

ELECTRICAL
CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

Total Supply Voltage (V

to V

) .......................+18V

Input Voltage .................... (V

+0.3V) to (V

0.3V)

Storage Temperature Range .............. -65°C to +150°C

Voltage on Oscillator Control Pins...............V

to V

Duration of Output Short Circuit ..................... Indefinite

Current Into Any Pin............................................ 10mA

While Operating (Note 3)............................ 100µA

Package Power Dissipation (T

70°C)

8-Pin Plastic DIP ....................................... 730mW

14-Pin Plastic DIP ..................................... 800mW

Operating Temperature Range

C Device .......................................... 0°C to +70°C

*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the
device at these or any other conditions above those indi-
cated in the operation sections of the specifications is not
implied. Exposure to Absolute Maximum Rating conditions
for extended periods my affect device reliability.

TC7652 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: V

= +5V, V

= -5V, C

= C

= 0.1

F, T

= +25°C, unless otherwise indicated.

Symbol

Parameter

Min.

Typ

Max

Units

Test Conditions

Input

Input Offset Voltage

--
--

±0.7
±1.0

±5
--

= +25°C

Over Operating Temp Range

Input Offset Voltage Average
Temperature Coefficient

0.01

0.05

V/°C

Operating Temperature Range

Offset Voltage vs. Time

100

nV/

month

BIAS

Input Bias Current

--
--
--

1.5

100

150
400

pA
pA
pA

= +25°C

0°C

+70°C

-25°C

+85°C

Input Offset Current

0.5

NP-P

Input Noise Voltage

P-P

= 100

, 0 to 10Hz

Input Noise Current

0.01

pA/

f = 10Hz

Input Resistance

CMVR

Common Mode Voltage Range

-5

-5.2 to +2

+1.6

CMRR

Common Mode Rejection Ratio

120

130

CMVR = -5V to +1.5V

Output

Large Signal Voltage Gain

120

130

= 10k

OUT

Output Voltage Swing (Note 2)

±4.7

±4.85
±4.95

--
--

= 10k

= 100k

Clamp ON Current

200

= 100k

(Note 1)

Clamp OFF Current

-4V < V

OUT

< +4V (Note 1)

Dynamic

Unity Gain Bandwidth

2.0

MHz

Unity Gain (+1)

Slew Rate

2.5

sec

= 50pF, R

= 10k

Rise Time

0.2

sec

Overshoot

Internal Chopping Frequency

120

200

375

Pins 1214 Open (DIP)

Supply

, V

Operating Supply Range

4.5

Supply Current

3.5

No Load

PSRR

Power Supply Rejection Ratio

120

130

= ±3V to ±8V

Note

See "Output Clamp" discussion.

Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics.

Limiting input current to 100

A is recommended to avoid latch-up problems.

TC7650

DS21463B-page 4

2002 Microchip Technology Inc.

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

3.0

DETAILED DESCRIPTION

3.1

Theory of Operation

Figure 3-1 shows the major elements of the TC7650.
There are two amplifiers (the main amplifier and the
nulling amplifier), and both have offset null capability.
The main amplifier is connected full-time from the input
to the output. The nulling amplifier, under the control of
the chopping frequency oscillator and clock circuit,
alternately nulls itself and the main amplifier. Two exter-
nal capacitors provide the required storage of the null-
ing potentials and the necessary nulling loop time
constants. The nulling arrangement operates over the
full common mode and power supply ranges, and is
also independent of the output level, thus giving excep-
tionally high CMRR, PSRR and A

VOL

Careful balancing of the input switches minimizes
chopper frequency charge injection at the input termi-
nals, and the feed forward type injection into the com-
pensation capacitor that can cause output spikes in this
type of circuit.

The circuit's offset voltage compensation is easily
shown. With the nulling inputs shorted, a voltage
almost identical to the nulling amplifier offset voltage is
stored on C

. The effective offset voltage at the null

amplifier input is:

EQUATION 3-1:

After the nulling amplifier is zeroed, the main amplifier
is zeroed; the A switches open and B switches close.

The output voltage equation is:

EQUATION 3-2:

EQUATION 3-3:

As desired, the device offset voltages are reduced by
the high open loop gain of the nulling amplifier.

3.2

Output Stage/Loading

The output circuit is a high impedance stage (approxi-
mately 18k

). With loads less than this, the chopper

amplifier behaves in some ways like a trans-conduc-
tance amplifier whose open-loop gain is proportional to
load resistance. For example, the open loop gain will
be 17dB lower with a 1k

load than with a 10k

load.

If the amplifier is used strictly for DC, the lower gain is
of little consequence, since the DC gain is typically
greater than 120dB, even with a 1k

load. In wideband

applications, the best frequency response will be
achieved with a load resistor of 10k

or higher. This

results in a smooth 6dB/octave response from 0.1Hz to
2MHz, with phase shifts of less than 10° in the transi-

Pin Number

Symbol

Description

8-pin DIP

14-pin DIP

1,8

2,1

, C

Nulling capacitor pins

-INPUT

Inverting Input

+INPUT

Non-inverting Input

Negative Power Supply

OUTPUT

CLAMP

Output Voltage Clamp

OUTPUT

Output

Positive Power Supply

3,6

No internal connection

RETN

Capacitor current return pin

INT CLK OUT

Internal Clock Output

EXT CLK IN

External Clock Input

INT/EXT

Select Internal or External Clock

OSE

------------------V

OSN

OUT

= A

[

OSM

+ (V

- V

) + A

- V

) + A

OSE

]

OUT

(

)

OSM

OSN

-------------------------------------------

2002 Microchip Technology Inc.

DS21463B-page 5

TC7650

tion region, where the main amplifier takes over from
the null amplifier. The clock frequency sets the transi-
tion region.

3.3

Intermodulation

Previous chopper stabilized amplifiers have suffered
from intermodulation effects between the chopper fre-
quency and input signals. These arise because the
finite AC gain of the amplifier results in a small AC sig-
nal at the input. This is seen by the zeroing circuit as an
error signal, which is chopped and fed back, thus inject-

ing sum and difference frequencies, and causing dis-
turbances to the gain and phase versus frequency
characteristics near the chopping frequency. These
effects are substantially reduced in the TC7650 by
feeding the nulling circuit with a dynamic current corre-
sponding to the compensation capacitor current in such
a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can gen-
erally be ignored.

FIGURE 3-1:

TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION
VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS

FIGURE 3-2:

NULLING CAPACITOR
CONNECTION

3.4

Nulling Capacitor Connection

The offset voltage correction capacitors are connected
to C

and C

. The common capacitor connection is

made to V

(Pin 4) on the 8-pin packages and to

capacitor return (C

RETN

, Pin 8) on the 14-pin packages.

The common connection should be made through a
separate PC trace or wire to avoid voltage drops. The
capacitors outside foil, if possible, should be connected
to C

RETN

or V

3.5

Clock Operation

The internal oscillator is set for a 200Hz nominal chop-
ping frequency on both the 8- and 14-pin DIPs. With the
14-pin DIP TC7650, the 200 Hz internal chopping fre-
quency is available at the internal clock output (Pin 12).
A 400Hz nominal signal will be present at the external
clock input pin (Pin 13) with INT/EXT high or open. This
is the internal clock signal before a divide-by-two oper-
ation.

The 14-pin DIP device can be driven by an external
clock. The INT/EXT input (Pin 14) has an internal pull-
up and may be left open for internal clock operation. If
an external clock is used, INT/EXT must be tied to V

(Pin 7) to disable the internal clock. The external clock
signal is applied to the external clock input (Pin 13).

The external clock amplitude should swing between
V

and ground for power supplies up to ±6V and

between V

and V

-6V for higher supply voltages.

At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the
desired 50% switching duty cycle. The offset storage
correction capacitors are charged only when the exter-
nal clock input is high. A 50% to 80% external clock

Null

Main
Amplifier

Null
Amplifier

Gain = A

TC7650

Null

V-

V+

Gain = A

, Offset = V

OSN

OUT

Analog Input

TC7650

14-PIN PACKAGE

8-PIN PACKAGE

TC7650

DS21463B-page 6

2002 Microchip Technology Inc.

positive duty cycle is desired for frequencies above
500Hz to ensure transients settle before the internal
switches open.

The external clock input can also be used as a strobe
input. If a strobe signal is connected at the external
clock input so that it is LOW during the time an overload
signal is applied, neither capacitor will be charged. The
leakage currents at the capacitors pins are very low. At
25°C a typical TC7650 will drift less than 10

V/sec.

3.6

Output Clamp

Chopper-stabilized systems can show long recovery
times from overloads. If the output is driven to either
supply rail, output saturation occurs. The inputs are no
longer held at a "virtual ground." The V

null circuit

treats the differential signal as an offset and tries to cor-
rect it by charging the external capacitors. The nulling
circuit also saturates. Once the input signal returns to
normal, the response time is lengthened by the long
recovery time of the nulling amplifier and external
capacitors.

Through an external clamp connection, the TC7650
eliminates the overload recovery problem by reducing
the feedback network gain before the output voltage
reaches either supply rail.

FIGURE 3-3:

INTERNAL CLAMP CIRCUIT

FIGURE 3-4:

NON-INVERTING AMPLIFIER
WITH OPTIONAL CLAMP

FIGURE 3-5:

INVERTING AMPLIFIER WITH
OPTIONAL CLAMP

The output clamp circuit is shown in Figure 3-3, with
typical inverting and non-inverting circuit connections
shown in Figures 3-4 and 3-5. Output voltage versus
clamp circuit current characteristics are shown in the
typical operating curves. For the clamp to be fully effec-
tive, the impedance across the clamp output should be
greater than 100k

3.7

Latch-Up Avoidance

Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has charac-
teristics similar to an SCR. Under certain circum-
stances this junction may be triggered into a low-
impedance state, resulting in excessive supply current.
To avoid this condition, no voltage greater than 0.3V
beyond the supply rails should be applied to any pin. In
general, the amplifier supplies must be established
either at the same time or before any input signals are
applied. If this is not possible, the drive circuits must
limit input current flow to under 0.1mA to avoid latch-
up.

3.8

Thermoelectric Potentials

Precision DC measurements are ultimately limited by
thermoelectric potentials developed in thermocouple
junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, ther-
moelectric voltages, typically around 0.1

V/°C, but up

to tens of

V/°C for some materials, will be generated.

In order to realize the benefits extremely-low offset volt-
ages provide, it is essential to take special precautions
to avoid temperature gradients. All components should
be enclosed to eliminate air movement, especially
those caused by power dissipating elements in the sys-
tem.

Low

thermoelectric

co-efficient

connections

should be used where possible and power supply volt-
ages and power dissipation should be kept to a mini-
mum. High impedance loads are preferable, and
separation from surrounding heat dissipating elements
is advised.

Internal
Positive Clamp Bias

V+ - V

V+ - 0.7

P-Channel

Output
Clamp Pin

N-Channel

TC7650

Output

Input

For Full Clamp Effect

+ (R1/R2) 100 k

0.1µF

Connect To V

On 8-Pin DIP.

Clamp

TC7650

Clamp

Output

0.1 F

Input

For Full Clamp
Effect

Connect To V

On 8-Pin DIP.

) 100 k

2002 Microchip Technology Inc.

DS21463B-page 7

TC7650

3.9

Pin Compatibility

On the 8-pin mini-DIP TC7650, the external null stor-
age capacitors are connected to pins 1 and 8. On most
other operational amplifiers these are left open or are
used for offset potentiometer or compensation capaci-
tor connections.

For OP05 and OP07 operational amplifiers, the
replacement of the offset null potentiometer between
pins 1 and 8 by two capacitors from the pins to V

will

convert the OP05/07 pin configurations for TC7650
operation. For LM108 devices, the compensation
capacitor is replaced by the external nulling capacitors.
The LM101/748/709 pinouts are modified similarly by
removing any circuit connections to Pin 5. On the
TC7650, Pin 5 is the output clamp connection.

Other operational amplifiers may use this pin as an off-
set or compensation point.

The minor modifications needed to retrofit a TC7650
into existing sockets operating at reduced power sup-
ply voltages make prototyping and circuit verification
straightforward.

3.10

Input Guarding

High impedance, low leakage CMOS inputs allow the
TC7650 to make measurements of high-impedance
sources. Stray leakage paths can increase input cur-
rents and decrease input resistance unless inputs are
guarded. A guard is a conductive PC trace surrounding
the input terminals. The ring connects to a low imped-
ance point at the same potential as the inputs. Stray
leakages are absorbed by the low impedance ring. The
equal potential between ring and inputs prevents input
leakage currents. Typical guard connections are shown
in Figure 3-6.

The 14-pin DIP configuration has been specifically
designed to ease input guarding. The pins adjacent to
the inputs are unused.

In applications requiring low leakage currents, boards
should be cleaned thoroughly and blown dry after sol-
dering. Protective coatings will prevent future board
contamination.

3.11

Component Selection

The two required capacitors, C

and C

, have optimum

values, depending on the clock or chopping frequency.
For the preset internal clock, the correct value is 0.1

To maintain the same relationship between the chop-
ping frequency and the nulling time constant, the
capacitor values should be scaled in proportion to the
external clock, if used. High quality film type capacitors
(such as Mylar) are preferred; ceramic or other lower
grade capacitors may be suitable in some applications.
For fast settling on initial turn-on, low dielectric absorp-
tion capacitors (such as polypropylene) should be
used. With ceramic capacitors, several seconds may
be required to settle to 1

FIGURE 3-6:

INPUT GUARD CONNECTION

Input

Output

Inverting Amplifier

Input

Output

Follower

Input

Output

Noninverting Amplifier

Should Be Low
Impedence For
Optimum Guarding

NOTE: R

+ R

TC7650

DS21463B-page 8

2002 Microchip Technology Inc.

4.0

TYPICAL CHARACTERISTICS

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

OUTPUT VOLTAGE (V)

Positive Clamp Current

vs. Output Voltage

CLAMP CURRENT

1 mA

0.1 mA

0.01 mA

1 A

0.1 A

0.01 A

1 nA

1 pA

0.01 nA

0.1 nA

-4.0 -4.1 -4.2 -4.3 -4.4 -4.5 -4.6 -4.7 -4.8 -4.9 -5.0

OUTPUT VOLTAGE (V)

Negative Clamp Current

vs. Output Voltage

CLAMP CURRENT

3.0

2.6

2.2

1.8

1.0

1.4

10 11 12

13 14 15

SUPPLY VOLTAGE (V)

Supply Current vs.

Supply Voltage

SUPPL

Y CURRENT (mA)

Gain/Phase vs. Frequency

10k

100k

10M

GAIN (dB)

225

180

135

-45

-90

-135

-180

FREQUENCY (H )

PHASE

(
de

1 mA

0.1 mA

0.01 mA

1 A

0.1 A

0.01 A

1 nA

1 pA

0.01 nA

0.1 nA

CLOSED-LOOP
GAIN = 20

PHASE

GAIN

= +25°C

= ±5V

= +25°C

= ±5V

= +25°C

2002 Microchip Technology Inc.

DS21463B-page 9

TC7650

5.0

PACKAGING INFORMATION

5.1

Package Marking Information

Package marking information not available at this time.

5.2

Package Dimensions

MIN.

PIN 1

.260 (6.60)
.240 (6.10)

.045 (1.14)
.030 (0.76)

.070 (1.78)
.040 (1.02)

.400 (10.16)

.348 (8.84)

.200 (5.08)
.140 (3.56)

.150 (3.81)
.115 (2.92)

.110 (2.79)
.090 (2.29)

.022 (0.56)
.015 (0.38)

.040 (1.02)
.020 (0.51)

.015 (0.38)
.008 (0.20)

.310 (7.87)
.290 (7.37)

.400 (10.16)

.310 (7.87)

8-Pin Plastic DIP

Dimensions: inches (mm)

.260 (6.60)
.240 (6.10)

.770 (19.56)
.745 (18.92)

.310 (7.87)
.290 (7.37)

.040 (1.02)
.020 (0.51)

.070 (1.78)
.045 (1.14)

.022 (0.56)
.015 (0.38)

.110 (2.79)
.090 (2.29)

.200 (5.08)
.140 (3.56)

.150 (3.81)
.115 (2.92)

PIN 1

14-Pin PDIP (Narrow)

.015 (0.38)
.008 (0.20)

MIN.

.400 (10.16)

.310 (7.87)

Dimensions: inches (mm)

2002 Microchip Technology Inc.

DS21463B - page 13

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip's products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,
K

, microID,

MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
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dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
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Serialized Quick Turn Programming (SQTP) is a service mark
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All other trademarks mentioned herein are property of their
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Printed on recycled paper.

Microchip received QS-9000 quality system
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The Company's quality system processes and
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PICmicro

8-bit MCUs, K

code hopping

devices, Serial EEPROMs, microperipherals,
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systems is ISO 9001 certified.

DS21463B-page 14

2002 Microchip Technology Inc.

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Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521

China - Shanghai

Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

China - Shenzhen

Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086

Hong Kong

Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431

India

Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O'Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910

France

Microchip Technology SARL
Parc d'Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820

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