2002 Microchip Technology Inc.
DS21482B-page 1
TC913A/TC913B
Features
First Monolithic Dual Auto-Zeroed
Operational Amplifier
Chopper Amplifier Performance Without External
Capacitors
- V
OS
: 15
V Max
- V
OS
: Drift; 0.15
V/C Max
- Saves Cost of External Capacitors
SOIC Packages Available
High DC Gain; 120dB
Low Supply Current; 650
A
Low Input Voltage Noise
- 0.65
V
P-P
(0.1Hz to 10Hz)
Wide Common Mode Voltage Range
- V
SS
to V
DD
- 2V
High Common Mode Rejection; 116dB
Dual or Single Supply Operation:
- 3.3V to 8.3V
- +6.5V to +16V
Excellent AC Operating Characteristics
- Slew Rate; 2.5V/
sec
- Unity-Gain Bandwidth; 1.5MHz
Pin Compatible with LM358, OP-14, MC1458,
ICL7621, TL082, TLC322
Applications
Instrumentation
Medical Instrumentation
Embedded Control
Temperature Sensor Amplifier
Strain Gage Amplifier
Device Selection Table
Package Type
General Description
The TC913 is the world's first complete monolithic, dual
auto-zeroed operational amplifier. The TC913 sets a
new standard for low power, precision dual-operational
amplifiers. Chopper-stabilized or auto-zeroed amplifi-
ers offer low offset voltage errors by periodically sam-
pling offset error, and storing correction voltages on
capacitors. Previous single amplifier designs required
two user-supplied, external 0.1
F error storage correc-
tion capacitors -- much too large for on-chip integra-
tion. The unique TC913 architecture requires smaller
capacitors,
making
on-chip
integration
possible.
Microvolt offset levels are achieved and external
capacitors are not required.
The TC913 system benefits are apparent when con-
trasted with a TC7650 chopper amplifier circuit imple-
mentation. A single TC913 replaces two TC7650's and
four capacitors. Five components and assembly steps
are eliminated.
The TC913 pinout matches many popular dual-opera-
tional amplifiers: OP-04, TLC322, LM358, and ICL7621
are typical examples. In many applications, operating
from dual 5V power supplies or single supplies, the
TC913 offers superior electrical performance, and can
be a functional drop-in replacement; printed circuit
board rework is not necessary. The TC913's low offset
voltage
error
eliminates
offset
voltage
trim
potentiometers often needed with bipolar and low
accuracy CMOS operational amplifiers.
The TC913 takes full advantage of Microchip's
proprietary CMOS technology. Unity gain bandwidth is
1.5MHz and slew rate is 2.5V/
sec.
Part Number
Package
Temp.
Range
Offset
Voltage
TC913ACOA
8-Pin SOIC
0C to
+70C
15
V
TC913ACPA
8-Pin PDIP
0C to
+70C
15
V
TC913BCOA
8-Pin SOIC
0C to
+70C
30
V
TC913BCPA
8-Pin PDIP
0C to
+70C
30
V
1
2
3
4
6
5
-IN B
7
8
OUT A
-IN A
+IN A
V
SS
V
SS
V
DD
V
DD
+IN B
PDIP
SOIC
TC913ACPA
TC913BCPA
TC913ACOA
TC913BCOA
OUT B
+
-
-
+
A
B
1
2
3
4
6
5
-IN B
7
8
OUT A
-IN A
+IN A
+IN B
OUT B
+
-
-
+
A
B
Dual Auto-Zeroed Operational Amplifiers
TC913A/TC913B
DS21482B-page 2
2002 Microchip Technology Inc.
Functional Block Diagram
-
+
+
-
TC913
A
4
8
B
*
A
B
*NOTE: Internal capacitors. No external capacitors required.
Main Amplifier
Low Impedance
Output Buffer
Internal
Oscillator
(f
OSC
200Hz)
+
-Input A
-Input B
1 of 2 Amplifier Shown
Output A
2
6
+Input A
+Input B
3
5
Output B
7
1
*
V
DD
V
SS
V
OS
Correction Amplifier
2002 Microchip Technology Inc.
DS21482B-page 3
TC913A/TC913B
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Total Supply Voltage (V
DD
to V
SS
) .......................+18V
Input Voltage ...................... (V
DD
+0.3V) to (V
SS
-
0.3V)
Current Into Any Pin............................................ 10mA
While Operating .......................................... 100
A
Package Power Dissipation (T
A
70C)
Plastic DIP ................................................ 730mW
Plastic SOIC ............................................. 470mW
Operating Temperature Range
C Device .......................................... 0C to +70C
Storage Temperature Range .............. -65C to +150C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied. Expo-
sure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
TC913A AND TC913B ELECTRICAL SPECIFICATIONS
Electrical Characteristics: V
S
= 5V, T
A
= +25C, unless otherwise indicated.
TC913A
TC913B
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
V
OS
Input Offset
Voltage
--
5
15
--
15
30
V
T
A
= +25C
TCV
OS
Average Temp.
Coefficient of
Input Offset
Voltage
--
--
0.05
0.05
0.15
0.15
--
--
0.1
0.1
0.25
0.25
V/C
V/C
0C
T
A
+70C
-25C
T
A
+85C
(Note 1)
I
B
Average Input
Bias Current
--
--
--
--
--
--
90
3
4
--
--
--
--
--
--
120
4
6
pA
nA
nA
T
A
= +25C
0C
T
A
+70C
-25C
T
A
+85
I
OS
Average Input
Offset Current
--
--
5
--
20
1
--
--
10
--
40
1
pA
nA
T
A
= +25C
T
A
= +85C
e
N
Input Voltage
Noise
--
--
0.6
11
--
--
--
--
0.6
11
--
--
V
P-P
V
P-P
0.1 to 1 Hz, R
S
100
0.1 to 10 Hz, R
S
100
CMRR
Common Mode
Rejection Ratio
110
116
--
100
110
--
dB
V
SS
V
CM
V
DD
- 2.2
CMVR
Common Mode
Voltage Range
V
SS
--
V
DD -
2
V
SS
--
V
DD -
2
V
A
OL
Open-Loop
Voltage Gain
115
120
--
110
120
--
dB
R
L
= 10 k
, V
OUT
= 4V
V
OUT
Output Voltage
Swing
V
SS
+ 0.3
--
V
DD
- 0.9
V
SS
+ 0.3
--
V
DD
-0.9
V
R
L
= 10 k
BW
Closed Loop
Bandwidth
--
1.5
--
--
1.5
--
MHz
Closed Loop Gain = +1
SR
Slew Rate
--
2.5
--
--
2.5
--
V/
sec R
L
= 10 k
, C
L
= 50 pF
PSRR
Power Supply
Rejection Ratio
110
--
--
100
--
--
dB
3.3V to 5.5V
V
S
Operating
Supply Voltage
Range
3.3
6.5
--
--
8.3
16
3.3
6.5
--
--
8.3
16
V
V
Split Supply
Single Supply
I
S
Quiescent
Supply Current
--
0.65
0.85
--
--
1.1
mA
V
S
= 5V
Note
1:
Characterized; not 100% tested.
TC913A/TC913B
DS21482B-page 4
2002 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin No.
(8-Pin PDIP)
(8-Pin SOIC)
Symbol
Description
1
OUT A
Output
2
-IN A
Inverting Input
3
+IN A
Non-inverting Input
4
V
SS
Negative Power Supply
5
+IN B
Non-inverting Input
6
-IN B
Inverting Input
7
OUT B
Output
8
V
DD
Positive Power Supply
2002 Microchip Technology Inc.
DS21482B-page 5
TC913A/TC913B
3.0
DETAILED DESCRIPTION
3.1
Theory of Operation
Each of the TC913's two Op Amps actually consists of
two amplifiers. A main amplifier is always connected
from the input to the output. A separate nulling amplifier
alternately nulls its own offset and then the offset of the
amplifier. Since each amplifier is continuously being
nulled, offset voltage drift with time, temperature and
power supply variations is greatly reduced.
All nulling circuitry is internal and the nulling operation
is transparent to the user. Offset nulling voltages are
stored on two internal capacitors. An internal oscillator
and control logic, shared by the TC913's two amplifiers,
control the nulling process.
3.2
Pin Compatibility
The TC913 pinout is compatible with OP-14, LM358,
MC1458, LT1013, TLC322, and similar dual Op Amps.
In many circuits operating from single or 5V supplies,
the TC913 is a drop-in replacement offering DC
performance rivaling that of the best single Op Amps.
The TC913's amplifiers include a low-impedance class
AB output buffer. Some previous CMOS chopper
amplifiers used a high impedance output stage which
made open-loop gain dependent on load resistance.
The TC913's open-loop gain is not dependent on load
resistance.
3.3
Overload Recovery
The TC913 recovers quickly from output saturation.
Typical recovery time from positive output saturation is
20 msec. Negative output saturation recovery time is
typically 5 msec.
3.4
Avoiding Latchup
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding
the supplies by 0.3V should not be applied to the
device pins. Larger voltages can turn the p-n-p-n
device on, causing excessive device power supply
current and power dissipation. The TC913's power
supplies should be established at the same time or
before input signals are applied. If this is not possible,
input current should be limited to 0.1mA to avoid
triggering the p-n-p-n structure.
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