1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM67.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 64

NONBUFFERED DRAM DIMMs

OBSOLETE

FEATURES

· JEDEC pinout in a 168-pin, dual in-line memory

module (DIMM)

· 8MB (1 Meg x 64), 16MB (2 Meg x 64) and

32MB (4 Meg x 64)

· Nonbuffered
· High-performance CMOS silicon-gate process
· Single +3.3V

0.3V power supply

· All inputs, outputs and clocks are TTL-compatible
· Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

· FAST-PAGE-MODE (FPM) or Extended Data-Out

(EDO) PAGE MODE access cycles

· 1,024-cycle refresh (10 row, 10 column addresses)

[MT4LD(T)164A(X)]
2,048-cycle refresh (11 row, 10 column addresses)
[MT8LD264A(X)]
2,048-cycle refresh (11 row, 11 column addresses)
[MT16LD464A(X)]

· Serial presence-detect (SPD)

OPTIONS

MARKING

· Components

SOJ

TSOP (1 Meg x 64 only)

· Package

168-pin DIMM (gold)

· Timing

50ns access

-5*

60ns access

-6

· Access Cycles

FAST PAGE MODE

None

EDO PAGE MODE

*EDO version only

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

127

DQ0

OE2#

DQ32

128

RFU

DQ1

RAS2#

DQ33

129

DQ2

CAS2#

DQ34

130

CAS6#

DQ3

CAS3#

DQ35

131

CAS7#

WE2#

132

RFU

DQ4

DQ36

133

DQ5

DQ37

134

DQ6

DQ38

135

DQ7

DQ39

136

DQ8

DQ40

137

138

DQ9

DQ16

DQ41

139

DQ48

DQ10

DQ17

DQ42

140

DQ49

DQ11

DQ18

DQ43

141

DQ50

DQ12

DQ19

100

DQ44

142

DQ51

DQ13

101

DQ45

143

DQ20

102

144

DQ52

DQ14

103

DQ46

145

DQ15

RFU

104

DQ47

146

RFU

105

147

106

148

DQ21

107

149

DQ53

DQ22

108

150

DQ54

DQ23

109

151

DQ55

110

152

WE0#

DQ24

111

RFU

153

DQ56

CAS0#

DQ25

112

CAS4#

154

DQ57

CAS1#

DQ26

113

CAS5#

155

DQ58

RAS0#

DQ27

114

156

DQ59

OE0#

115

RFU

157

DQ28

116

158

DQ60

DQ29

117

159

DQ61

DQ30

118

160

DQ62

DQ31

119

161

DQ63

120

162

121

163

NC**/A10

122

NC (A11)

164

NC (A12)

123

NC (A13)

165

SA0

SDA

124

166

SA1

SCL

125

RFU

167

SA2

RFU

126

RFU

168

**1 Meg x 64 version only

PIN ASSIGNMENT (Front View)

168-Pin DIMM

DRAM
MODULE

MT4LDT164A(X), MT8LD264A(X),
MT16LD464A(X)

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html

NOTE: Pin symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM67.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 64

NONBUFFERED DRAM DIMMs

OBSOLETE

by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.

EDO PAGE MODE

EDO PAGE MODE, designated by the "X" version, is an

accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(

CP) to occur without the output data going invalid. This

elimination of CAS# output control provides for pipeline
READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.

During an application, if the DQ outputs are wire OR'd,

OE# must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after

OFF, which is refer-

enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 4 (MT4LC4M4E8) DRAM
data sheet for additional information on EDO functional-
ity.)

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-detect

(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM's SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.

KEY TIMING PARAMETERS

EDO Operating Mode

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

13/15ns*

8ns

-6

104ns

60ns

25ns

30ns

10ns

*8MB DIMM

FPM Operating Mode

SPEED

RAC

CAC

-6

110ns

60ns

35ns

30ns

15ns

40ns

PART NUMBERS

EDO Operating Mode

PART NUMBER

CONFIGURATION

SPEED

PACKAGE

MT4LDT164AG-5 X

1 Meg x 64

50ns

TSOP

MT4LDT164AG-6 X

1 Meg x 64

60ns

TSOP

MT8LD264AG-5 X

2 Meg x 64

50ns

SOJ

MT8LD264AG-6 X

2 Meg x 64

60ns

SOJ

MT16LD464AG-5 X

4 Meg x 64

50ns

SOJ

MT16LD464AG-6 X

4 Meg x 64

60ns

SOJ

FPM Operating Mode

PART NUMBER

CONFIGURATION

SPEED

PACKAGE

MT4LDT164AG-6

1 Meg x 64

60ns

TSOP

MT8LD264AG-6

2 Meg x 64

60ns

SOJ

MT16LD464AG-6

4 Meg x 64

60ns

SOJ

GENERAL DESCRIPTION

The MT4LDT164A(X), MT8LD264A(X) and

MT16LD464A(X) are randomly accessed 8MB, 16MB and
32MB memories organized in a x64 configuration. During
READ or WRITE cycles, each bit is uniquely addressed
through the 20/21/22 address bits, which are entered 10/
11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-A10) at
CAS# time.

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed

1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM67.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 64

NONBUFFERED DRAM DIMMs

OBSOLETE

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).

The SPD device will always respond with an acknowl-

edge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition, which

is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.

SPD STOP CONDITION

All communications are terminated by a stop condition,

which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

Figure 3

ACKNOWLEDGE RESPONSE FROM RECEIVER

Figure 1

DATA VALIDITY

Figure 2

DEFINITION OF START AND STOP

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM67.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 64

NONBUFFERED DRAM DIMMs

OBSOLETE

FUNCTIONAL BLOCK DIAGRAM

MT4LDT164A(X) (8MB)

DQ0-DQ15

DQ16-DQ31

DQ32-DQ47

DQ48-DQ63

A0-A9

OE2#

WE2#

CAS4#

RAS2#

CAS5#

CAS7#

CAS6#

U1-U4 = MT4LC1M16C3 FAST PAGE MODE

U1-U4 = MT4LC1M16E5 EDO PAGE MODE

OE0#

WE0#

CAS0#

RAS0#

CAS1#

CAS3#

CAS2#

DQ0-DQ15

A0A9

WE#

OE#

RAS#

LCAS#

UCAS#

A0A9

SA0

SPD

SCL

SDA

A0A9

SA1

SA2

WE#

OE#

RAS#

LCAS#

UCAS#

WE#

OE#

RAS#

LCAS#

UCAS#

WE#

OE#

RAS#

LCAS#

UCAS#

U1-U4

DQ0-DQ15

1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM67.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 64

NONBUFFERED DRAM DIMMs

OBSOLETE

FUNCTIONAL BLOCK DIAGRAM

MT8LD264A(X) (16MB)

A0-A10

OE2#

WE2#

CAS4#

RAS2#

CAS5#

CAS7#

CAS6#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

U1-U8 = MT4LC2M8B1 FAST PAGE MODE

U1-U8 = MT4LC2M8E7 EDO PAGE MODE

OE0#

WE0#

CAS0#

RAS0#

CAS1#

CAS3#

CAS2#

SA0

SPD

SCL

SDA

SA1

SA2

U1-U8

DQ0-DQ7

DQ8-DQ15

DQ16-DQ23

DQ24-DQ31

DQ32-DQ39

DQ40-DQ47

DQ48-DQ55

DQ56-DQ63

FUNCTIONAL BLOCK DIAGRAM

MT16LD464A(X) (32MB)

WE#

OE#

RAS#

CAS#

A0A10

WE#

OE#

RAS#

CAS#

WE#

OE#

RAS#

CAS#

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS#

WE#

OE#

RAS#

CAS#

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

A0A10

WE#

OE#

RAS#

CAS# A0A10

WE#

OE#

RAS#

CAS# A0A10

U1-U16 = MT4LC4M4B1 FAST PAGE MODE

U1-U16 = MT4LC4M4E8 EDO PAGE MODE

U10

U11

U12

U13

U14

U15

U16

OE0#

CAS1#

CAS2#

CAS3#

WE0#

CAS0#

OE2#

CAS5#

CAS6#

CAS7#

WE2#

CAS4#

A0-A10

RAS0#

RAS2#

SA0

SPD

SCL

SDA

SA1

SA2

U1-U16

DQ0-DQ3

DQ4-DQ7

DQ8-DQ11

DQ12-DQ15

DQ16-DQ19

DQ20-DQ23

DQ24-DQ27

DQ28-DQ31

DQ32-DQ35

DQ36-DQ39

DQ40-DQ43

DQ44-DQ47

DQ48-DQ51

DQ52-DQ55

DQ56-DQ59

DQ60-DQ63

DQ0-DQ3

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT16LD464AX

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT16LD464AX