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Электронный компонент: MT16VDDF12864H

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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
1
2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
SMALL-OUTLINE
DDR SDRAM DIMM
MT16VDDF6464H 512MB
MT16VDDF12864H 1GB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/moduleds
Features
200-pin, small-outline, dual in-line memory
module (SODIMM)
Fast data transfer rates: PC1600, PC2100, and PC2700
Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR
SDRAM components
512MB (64 Meg x 64), 1GB (128 Meg x 64)
V
DD
= V
DD
Q = +2.5V
V
DDSPD
= +2.3V to +3.6V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/
received with data--i.e., source-synchronous data
capture
Differential clock inputs CK and CK#
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
7.8125s maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Gold edge contacts
Figure 1: 200-Pin SODIMM (MO-224)
NOTE:
1. Contact factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) latency.
OPTIONS
MARKING
Package
200-pin SODIMM (standard)
G
200-pin SODIMM (lead-free)
1
Y
Frequency/CAS Latency
2
167 MHz (333 MT/s) CL = 2.5
-335
133 MHz (266 MT/s) CL = 2
-262
133 MHz (266 MT/s) CL = 2
-26A
133 MHz (266 MT/s) CL = 2.5
-265
100 MHz (200 MT/s) CL = 2
-202
512MB Module
1GB Module
Table 1:
Address Table
512MB
1GB
Refresh Count
8K
8K
Device Row Addressing
8K (A0A12)
8K (A0A12)
Device Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
Device Configuration
32 Meg x 8
64 Meg x 8
Device Column Addressing
1K (A0A9)
2K (A0A9, A11)
Module Rank Addressing
2 (S0#, S1#)
2 (S0#, S1#)
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
2
2003 Micron Technology, Inc.
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current Revision codes. Example: MT16VDDF6464HG-265A1.
Table 2:
Part Numbers and Timing Parameters
PART NUMBER
MODULE
DENSITY
CONFIGURATION
TRANSFER
RATE
MEMORY CLOCK/
DATA BIT RATE
LATENCY
(CL -
t
RCD -
t
RP)
MT16VDDF6464HG-335__
512MB
64 Meg x 64
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT16VDDF6464HY-335__
512MB
64 Meg x 64
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT16VDDF6464HG-262__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT16VDDF6464HY-262__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT16VDDF6464HG-26A__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT16VDDF6464HY-26A__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT16VDDF6464HG-265__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT16VDDF6464HY-265__
512MB
64 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT16VDDF6464HG-202__
512MB
64 Meg x 64
1.6 GB/s
10ns/200 MT/s
2-2-2
MT16VDDF6464HY-202__
512MB
64 Meg x 64
1.6 GB/s
10ns/200 MT/s
2-2-2
MT16VDDF12864HG-335__
1GB
128 Meg x 64
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT16VDDF12864HY-335__
1GB
128 Meg x 64
2.7 GB/s
6ns/333 MT/s
2.5-3-3
MT16VDDF12864HG-262__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT16VDDF12864HY-262__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-2-2
MT16VDDF12864HG-26A__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT16VDDF12864HY-26A__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2-3-3
MT16VDDF12864HG-265__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT16VDDF12864HY-265__
1GB
128 Meg x 64
2.1 GB/s
7.5ns/266 MT/s
2.5-3-3
MT16VDDF12864HG-202__
1GB
128 Meg x 64
1.6 GB/s
10ns/200 MT/s
2-2-2
MT16VDDF12864HY-202__
1GB
128 Meg x 64
1.6 GB/s
10ns/200 MT/s
2-2-2
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
3
2003 Micron Technology, Inc.
Figure 2: Module Layout
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
REF
51
V
SS
101
A9
151
DQ42
3
V
SS
53
DQ19
103
V
SS
153
DQ43
5
DQ0
55
DQ24
105
A7
155
V
DD
7
DQ1
57
V
DD
107
A5
157
V
DD
9
V
DD
59
DQ25
109
A3
159
V
SS
11
DQS0
61
DQS3
111
A1
161
V
SS
13
DQ2
63
V
SS
113
V
DD
163
DQ48
15
V
SS
65
DQ26
115
A10
165
DQ49
17
DQ3
67
DQ27
117
BA0
167
V
DD
19
DQ8
69
V
DD
119
WE#
169
DQS6
21
V
DD
71
DNU
121
S0#
171
DQ50
23
DQ9
73
DNU
123
NC
173
V
SS
25
DQS1
75
V
SS
125
V
SS
175
DQ51
27
V
SS
77
DNU
127
DQ32
177
DQ56
29
DQ10
79
DNU
129
DQ33
179
V
DD
31
DQ11
81
V
DD
131
V
DD
181
DQ57
33
V
DD
83
DNU
133
DQS4
183
DQS7
35
CK0
85
NC
135
DQ34
185
V
SS
37
CK0#
87
V
SS
137
V
SS
187
DQ58
39
V
SS
89
DNU
139
DQ35
189
DQ59
41
DQ16
91
DNU
141
DQ40
191
V
DD
43
DQ17
93
V
DD
143
V
DD
193
SDA
45
V
DD
95
CKE1
145
DQ41
195
SCL
47
DQS2
97
NC
147
DQS5
197
V
DD
SPD
49
DQ18
99
A12
149
V
SS
199
NC
Table 4:
Pin Assignment
(200-Pin SODIMM Back)
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
2
V
REF
52
V
SS
102
A8
152
DQ46
4
V
SS
54
DQ23
104
V
SS
154
DQ47
6
DQ4
56
DQ28
106
A6
156
V
DD
8
DQ5
58
V
DD
108
A4
158
CK1#
10
V
DD
60
DQ29
110
A2
160
CK1
12
DM0
62
DM3
112
A0
162
V
SS
14
DQ6
64
V
SS
114
V
DD
164
DQ52
16
V
SS
66
DQ30
116
BA1
166
DQ53
18
DQ7
68
DQ31
118
RAS#
168
V
DD
20
DQ12
70
V
DD
120
CAS#
170
DM6
22
V
DD
72
DNU
122
S1#
172
DQ54
24
DQ13
74
DNU
124
NC
174
V
SS
26
DM1
76
V
SS
126
V
SS
176
DQ55
28
V
SS
78
DNU
128
DQ36
178
DQ60
30
DQ14
80
DNU
130
DQ37
180
V
DD
32
DQ15
82
V
DD
132
V
DD
182
DQ61
34
V
DD
84
DNU
134
DM4
184
DM7
36
V
DD
86
DNU
136
DQ38
186
V
SS
38
V
SS
88
V
SS
138
V
SS
188
DQ62
40
V
SS
90
V
SS
140
DQ39
190
DQ63
42
DQ20
92
V
DD
142
DQ44
192
V
DD
44
DQ21
94
V
DD
144
V
DD
194
SA0
46
V
DD
96
CKE0
146
DQ45
196
SA1
48
DM2
98
NC
148
DM5
198
SA2
50
DQ22
100
A11
150
V
SS
200
V
SS
U1
U2
U3
U4
U5
U6
U7
U8
U17
U9
U10
U11
U12
U13
U14
U15
U16
PIN 1
PIN 199
(all odd pins)
PIN 2
PIN 200
(all even pins)
Front View
Back View
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
U1
U2
U3
U4
U5
U6
U7
U8
U17
U9
U10
U11
U12
U16
U15
U14
U13
PIN 1
PIN 199
(all odd pins)
PIN 2
PIN 200
(all even pins)
Front View
Back View
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
4
2003 Micron Technology, Inc.
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
118, 119, 120
WE#,
CAS#,RAS#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
35, 37, 158, 160
CK0, CK0#
CK1, CK1#
Input
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK, and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
95, 96
CKE0, CKE1
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied and
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
121, 122
S0#, S1#
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
116, 117
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
99, 100, 101, 102, 105,106,
107, 108, 109, 110, 111, 112,
115
A0-A12
Input
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
1, 2
V
REF
Input
SSTL_2 reference voltage.
195
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
194, 196, 198
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
193
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
12, 26, 48, 62, 134, 148, 170,
184
DM0-DM7
Input
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
5
2003 Micron Technology, Inc.
11, 25, 47, 61, 133, 147, 169,
183
DQS0-DQS7
Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
5, 6, 7, 8, 13, 14, 17, 18, 19,
20, 23, 24, 29, 30, 31, 32, 41,
42, 43, 44, 49, 50, 53, 54, 55,
56, 59, 60, 65, 66, 67, 68, 127,
128, 129, 130, 135, 136, 139,
140, 141, 142, 145, 146, 151,
152, 153, 154, 163, 164, 165,
166, 171, 172, 175, 176, 177,
178, 181, 182, 187, 188, 189,
190
DQ0-DQ63
Input/
Output
Data I/Os: Data bus.
9, 10, 21, 22, 33, 34, 36, 45,
46, 57, 58, 69, 70, 81, 82, 92,
93, 94, 113, 114, 131, 132,
143, 144, 155, 156, 157, 167,
168, 179, 180, 191, 192
V
DD
Supply
Power Supply: +2.5V 0.2V.
3, 4, 15, 16, 27, 28, 38, 39, 40,
51, 52, 63, 64, 75, 76, 87, 88,
90, 103, 104, 125, 126, 137,
138, 149, 150, 159, 161, 162,
173, 174, 185, 186, 200
V
SS
Supply
Ground.
197
V
DDSPD
Supply
Serial EEPROM positive power supply: +2.3V to +3.6V
85, 97, 98, 123, 124, 199
NC
--
No Connect: These pins should be left unconnected.
71, 72, 73, 74, 77, 78, 79, 80,
83, 84, 86, 89, 91
DNU
--
Do Not Use: These pins are not connected on this module, but
are assigned pins on other modules in this product family.
Table 5:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
6
2003 Micron Technology, Inc.
Figure 3: Functional Block Diagram 512MB
A0
SA0
SERIAL PD
U17
SDA
A1
SA1
A2
SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs U1-U8
CKE1: DDR SDRAMs U9-U16
WE#: DDR SDRAMs
CAS#
CKE0
CKE1
WE#
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U8
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
S0#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
WP
SCL
U14
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S1#
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DM7
DQS7
DM2
DQS2
DM5
DQS5
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM4
DQS4
DM3
DQS3
DM CS# DQS
DM CS# DQS
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM6
DQS6
DM1
DQS1
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
V
DDSPD
V
DD
DDR SDRAMs
SPD/EEPROM
DDR SDRAMs U1, U2, U3, U7
U12, U13, U14, U16
CK0
CK0#
120
DDR SDRAMs U4, U5, U6, U8
U9, U10, U11, U15
CK1
CK1#
120
120
CK2
CK2#
NOTE:
1. All resistor values are 22
W unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at
www.micron.com/
numberguide
.
DDR SDRAMs: MT46V32M8S2FD
DDR SDRAMs: MT46V64M8S2FD
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
7
2003 Micron Technology, Inc.
Figure 4: Functional Block Diagram 1GB
A0
SA0
SERIAL PD
U17
SDA
A1
SA1
A2
SA2
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs U1-U8
CKE1: DDR SDRAMs U9-U16
WE#: DDR SDRAMs
CAS#
CKE0
CKE1
WE#
V
REF
V
SS
DDR SDRAMs
DDR SDRAMs
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U8
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U6
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM0
S0#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
WP
SCL
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U16
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S1#
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQS0
DM7
DQS7
DM2
DQS2
DM5
DQS5
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM4
DQS4
DM3
DQS3
DM CS# DQS
DM CS# DQS
U7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM6
DQS6
DM1
DQS1
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
U13
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
V
DDSPD
V
DD
DDR SDRAMs
SPD/EEPROM
DDR SDRAMs
U1, U2, U3, U7
U12, U13, U14, U16
CK0
CK0#
120
DDR SDRAMs
U4, U5, U6, U8
U9, U10, U11, U15
CK1
CK1#
120
120
CK2
CK2#
NOTE:
1. All resistor values are 22
W unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at
www.micron.com/
numberguide
.
DDR SDRAMs: MT46V32M8S2FD
DDR SDRAMs: MT46V64M8S2FD
512MB, 1GB (x64)
200-PIN DDR SODIMM
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General Description
The MT16VDDF6464H and MT16VDDF12864H are
high-speed CMOS, dynamic random-access, 512MB
and 1GB memory modules organized in a x64 configu-
ration. These modules use internally configured quad-
bank DRAM devices.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0A12 select
device row). The address bits registered coincident
with the READ or WRITE command are used to select
the device bank and the starting device column loca-
tion for the burst access.
DDR SDRAM modules provides for programmable
read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAM modules, the pipe-
lined, multibank architecture of DDR SDRAM modules
allows for concurrent operation, thereby providing
high effective bandwidth by hiding row precharge and
activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 256Mb or 512Mb DDR SDRAM data sheets.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
2
C bus
using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 5, Mode Register Definition Diagram, on page 9.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A12
specify the operating mode.
512MB, 1GB (x64)
200-PIN DDR SODIMM
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2003 Micron Technology, Inc.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1Ai when the burst length is set to two,
by A2Ai when the burst length is set to four and by
A3Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration. See Note 5 of Table 6, Burst Definition
Table, on page 10, for Ai values). The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. The programmed
burst length applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 5: Mode Register Definition
Diagram
Burst Length
CAS Latency BT
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
Operating Mode
A10
A12 A11
BA1 BA0
10
11
12
13
0*
14
* M14 and M13 (BA1 and BA0)
must be "0, 0" to select the
base mode register (vs. the
extended mode register).
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
Valid
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
M9
M10
M12 M11
0
0
-
M13
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NOTE:
1. For a burst length of two, A1-Ai select the two-data-ele-
ment block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai select the four-data-
element block; A0-A1 select the first access within the
block.
3. For a burst length of eight, A3-Ai select the eight-data-
element block; A0-A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
5. i = 9 (512MB);
i = 9,11 (1GB)
Figure 6: CAS Latency Diagram
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7A12
each set to zero, and bits A0A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9A12 each set
to zero, bit A8 set to one, and bits A0A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
All other combinations of values for A7A12 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
Table 6:
Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
2
A0
0
0-1
0-1
1
1-0
1-0
4
A1
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
-335
75
f 133
75
f 167
-262
75
f 133
75
f 133
-26A
75
f 133
75
f 133
-265
75
f 100
75
f 133
-202
75
f 100
75
f 125
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON T CARE
TRANSITIONING DATA
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BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Figure 7: Extended Mode Register
Definition Diagram
NOTE:
1. BA1 and BA0 (E14 and E13) must be "0, 1" to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
DLL
11
01
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9
7
6
5
4
3
8
2
1
0
Operating Mode
A10
A11
A12
BA1 BA0
10
11
12
13
14
DS
Operating Mode
Reserved
Reserved
0
0
Valid
0
1
DLL
Enable
Disable
E0
0
1
Drive Strength
Normal
Reduced
E1
E2
2
E0
E1,
E3
E4
0
0
0
0
0
E6 E5
E7
E8
E9
0
0
E10
E11
0
E12
0
0
E13
512MB, 1GB (x64)
200-PIN DDR SODIMM
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Commands
The Truth Tables below provides a general reference
of available commands. For a more detailed descrip-
tion of commands and operations, refer to the 256Mb
or 512Mb DDR SDRAM component data sheet.
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A12 provide device row address.
3. BA0BA1 provide device bank address; A0A9 (512MB) or A0A9, A11 (1GB) provide device column address; A10 HIGH
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0
BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0A12 provide the op-code
to be written to the selected mode register.
Table 8:
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION)
CS#
RAS# CAS#
WE#
ADDR
NOTES
DESELECT (NOP)
H
X
X
X
X
1
NO OPERATION (NOP)
L
H
H
H
X
1
ACTIVE (Select bank and activate row)
L
L
H
H
Bank/Row
2
READ (Select bank and column, and start READ burst)
L
H
L
H
Bank/Col
3
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
Bank/Col
3
BURST TERMINATE
L
H
H
L
X
4
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
L
L
L
H
X
6, 7
LOAD MODE REGISTER
L
L
L
L
Op-Code
8
Table 9:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
DM
DQS
WRITE Enable
L
Valid
WRITE Inhibit
H
X
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Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on V
DD
Supply
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on V
DD
Q Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on V
REF
and Inputs
Relative to V
SS
. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to V
SS
. . . . . . . . . . . . . -0.5V to V
DD
Q +0.5V
Operating Temperature
T
A
(ambient) . . . . . . . . . . . . . . . . . . . . .. 0C to +70C
Storage Temperature (plastic) . . . . . . -55C to +150C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 16W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 15, 14; notes appear on pages 2023; 0C
T
A
+70C
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
V
DD
2.3
2.7
V
32, 36
I/O Supply Voltage
V
DD
Q
2.3
2.7
V
32, 36, 39
I/O Reference Voltage
V
REF
0.49
V
DD
Q
0.51
V
DD
Q
V
6, 39
I/O Termination Voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
7, 39
Input High (Logic 1) Voltage
V
IH
(DC)
V
REF
+ 0.15
V
DD
+ 0.3
V
25
Input Low (Logic 0) Voltage
V
IH
(DC)
-0.3
V
REF
- 0.15
V
25
INPUT LEAKAGE CURRENT Any input
0V
V
IN
V
DD
, V
REF
pin 0V
V
IN
1.35V
(All other pins not under test = 0V)
Command/Address,
RAS#, CAS#, WE#
I
I
-32
32
A
47
S#, CKE, CK, CK#
-16
16
DM
-4
4
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V
V
OUT
V
DD
Q)
DQ, DQS
I
OZ
-10
10
A
47
OUTPUT LEVELS
High Current (V
OUT
= V
DD
Q - 0.373V, minimum V
REF
, minimum V
TT
)
Low Current (V
OUT
= 0.373V, maximum V
REF
, maximum V
TT
)
I
OH
-16.8
mA
33, 34
I
OL
16.8
mA
Table 11: AC Input Operating Conditions
Notes: 15, 14; notes appear on pages 2023; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNIT
S
NOTES
Input High (Logic 1) Voltage
V
IH
(AC)
V
REF
+ 0.310
V
12, 25, 35
Input Low (Logic 0) Voltage
V
IL
(AC)
V
REF
- 0.310
V
12, 25, 35
I/O Reference Voltage
V
REF
(AC)
0.49
V
DD
Q
0.49
V
DD
Q
V
6
512MB, 1GB (x64)
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Table 12: I
DD
Specifications and Conditions 512MB
Notes: 15, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 2023; 0C
T
A
+70C; V
DD
, V
DD
Q = +2.5V 0.2V
MAX
PARAMETER/CONDITION
SYM
-335
-262
-26A/-
265
-202
UNIT
S
NOTE
S
OPERATING CURRENT: One device bank; Active-
Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
I
DD0
a
1,032
1,032
872
992
mA
20, 42
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
I
OUT
= 0mA; Address and control inputs
changing once
per clock cycle
I
DD1
a
1,392
1,312
1,192
1,272
mA
20, 42
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
t
CK =
t
CK (MIN);
CKE = (LOW)
I
DD2P
b
64
64
64
64
mA
21, 28,
44
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
are idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other
control inputs changing once per clock
cycle. V
IN
= V
REF
for DQ, DQS, and DM
I
DD2F
b
800
720
720
720
mA
45
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
t
CK =
t
CK (MIN);
CKE = LOW
I
DD3P
b
480
400
400
480
mA
21, 28,
44
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active
;
t
RC =
t
RAS (MAX);
t
CK =
t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
I
DD3N
b
960
800
800
800
mA
41
OPERATING CURRENT: Burst = 2;
Reads; Continuous
burst; One device bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN);
I
OUT
=
0mA
I
DD4R
a
1,432
1,232
1,232
1,432
mA
20, 42
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank
active; Address and control
inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
I
DD4W
a
1,272
1,112
1,122
1,552
mA
20
AUTO REFRESH BURST CURRENT:
t
RC =
t
RFC
(MIN)
t
RFC =
7.8125s
I
DD5
b
4,080
3,760
3,760
3,920
mA
20, 44
I
DD5A
b
96
96
96
96
mA
24, 44
SELF REFRESH CURRENT: CKE
0.2V
I
DD6
b
64
64
64
64
mA
9
OPERATING CURRENT: Four device bank interleaving
READs
(Burst = 4) with auto precharge,
t
RC = minimum
t
RC allowed;
t
CK =
t
CK (MIN); Address and control inputs
change only during Active READ, or WRITE commands
I
DD7
a
3,272
2,832
2,832
2,952
mA
20, 43
NOTE:
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
DD
2p (CKE LOW) mode.
b - Value calculated reflects all module ranks in this operating condition.
512MB, 1GB (x64)
200-PIN DDR SODIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
15
2003 Micron Technology, Inc.
Table 13: I
DD
Specifications and Conditions 1GB
Notes: 15, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 2023; 0C
T
A
+70C; V
DD
, V
DD
Q = +2.5V 0.2V
MAX
PARAMETER/CONDITION
SYM
-335
-262
-26A/-
265
-202
UNIT
S
NOTE
S
OPERATING CURRENT: One device bank; Active-
Precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
I
DD0
1,080
1,080
960
960
mA
20, 42
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
I
OUT
= 0mA; Address and control inputs
changing once
per clock cycle
I
DD1
1,320
1,320
1,200
1,200
mA
20, 42
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
t
CK =
t
CK (MIN);
CKE = (LOW)
I
DD2P
80
80
80
80
mA
21, 28,
44
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
are idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other
control inputs changing once per clock
cycle. V
IN
= V
REF
for DQ, DQS, and DM
I
DD2F
720
720
640
640
mA
45
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
t
CK =
t
CK (MIN);
CKE = LOW
I
DD3P
560
560
480
480
mA
21, 28,
44
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active
;
t
RC =
t
RAS (MAX);
t
CK =
t
CK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
I
DD3N
720
720
640
640
mA
41
OPERATING CURRENT: Burst = 2;
Reads; Continuous
burst; One device bank active; Address and control inputs
changing once per clock cycle;
t
CK =
t
CK (MIN);
I
OUT
=
0mA
I
DD4R
1,360
1,360
1,200
1,200
mA
20, 42
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank
active; Address and control
inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
I
DD4W
1,280
1,280
1,120
1,120
mA
20
AUTO REFRESH BURST CURRENT:
t
RC =
t
RFC (MIN)
I
DD5
4,640
4,640
4,480
4,480
mA
20, 44
t
RC = 7.8125s
I
DD5A
160
160
160
160
mA
24, 44
SELF REFRESH CURRENT: CKE
0.2V
I
DD6
80
80
80
80
mA
9
OPERATING CURRENT: Four device bank interleaving
READs
(Burst = 4) with auto precharge,
t
RC = minimum
t
RC allowed;
t
CK =
t
CK (MIN); Address and control inputs
change only during Active READ, or WRITE commands
I
DD7
3,280
3,240
2,840
2,840
mA
20, 43
NOTE:
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
DD
2p (CKE LOW) mode.
b - Value calculated reflects all module ranks in this operating condition.
512MB, 1GB (x64)
200-PIN DDR SODIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
16
2003 Micron Technology, Inc.
Table 14: Capacitance
Note: 11; notes appear notes appear on pages 2023
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input/Output Capacitance: DQ, DQS,DM
C
IO
7
9
pF
Input Capacitance: Command and Address, RAS#, CAS#, WE#
C
I1
24
40
pF
Input Capacitance:CK, CK#, CKE, S#
C
I2
12
20
pF
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262)
Notes: 15, 1215, 29, 40; notes appear on pages 2023; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-335
-262
UNITS
NOTES
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
t
AC
-0.70
+0.70
-0.75
+0.75
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
t
CK
26
CK low-level width
t
CL
0.45
0.55
0.45
0.55
t
CK
26
Clock cycle time
CL=2.5
t
CK (2.5)
6
13
7.5
13
ns
40, 46
CL=2
t
CK (2)
7.5
13
7.5
13
ns
40, 46
DQ and DM input hold time relative to DQS
t
DH
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
t
DS
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
t
DIPW
1.75
1.75
ns
27
Access window of DQS from CK/CK#
t
DQSCK
-0.60
+0.60
-0.75
+0.75
ns
DQS input high pulse width
t
DQSH
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid, per group, per access
t
DQSQ
0.4
0.5
ns
22, 23
Write command to first DQS latching transition
t
DQSS
0.75
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.20
0.20
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.20
0.20
t
CK
Half clock period
t
HP
t
CH,
t
CL
t
CH,
t
CL
ns
8
Data-out high-impedance window from CK/CK#
t
HZ
+0.70
+0.75
ns
16, 37
Data-out low-impedance window from CK/CK#
t
LZ
-0.70
-0.75
ns
16, 38
Address and control input hold time (fast slew rate)
t
IH
F
0.75
0.90
ns
12
Address and control input setup time (fast slew rate)
t
IS
F
0.75
0.90
ns
12
Address and control input hold time (slow slew rate)
t
IH
S
0.8
1
ns
12
Address and control input setup time (slow slew rate)
t
IS
S
0.8
1
ns
12
Address and Control input pulse width (for each input)
t
IPW
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
t
MRD
12
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access
t
QH
t
HP -
t
QHS
t
HP -
t
QHS
ns
22, 23
Data hold skew factor
t
QHS
0.75
0.75
ns
ACTIVE to PRECHARGE command
t
RAS
42
70,000
40
120,000
ns
31
ACTIVE to READ with Auto precharge command
t
RAP
18
15
ns
512MB, 1GB (x64)
200-PIN DDR SODIMM
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2003 Micron Technology, Inc.
ACTIVE to ACTIVE/AUTO REFRESH command period
t
RC
60
60
ns
AUTO REFRESH command period
t
RFC
72
75
ns
44
ACTIVE to READ or WRITE delay
t
RCD
18
15
ns
PRECHARGE command period
t
RP
18
15
ns
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
t
CK
37
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK
ACTIVE bank a to ACTIVE bank b command
t
RRD
12
15
ns
DQS write preamble
t
WPRE
0.25
0.25
t
CK
DQS write preamble setup time
t
WPRES
0
0
ns
18, 19
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
t
CK
17
Write recovery time
t
WR
15
15
ns
Internal WRITE to READ command delay
t
WTR
1
1
t
CK
Data valid output window
NA
t
QH -
t
DQSQ
t
QH -
t
DQSQ
ns
22
REFRESH to REFRESH command interval
t
REFC
70.3
70.3
s
21
Average periodic refresh interval
t
REFI
7.8
7.8
s
21
Terminating voltage delay to V
DD
t
VTD
0
0
ns
Exit SELF REFRESH to non-READ command
t
XSNR
75
75
ns
Exit SELF REFRESH to READ command
t
XSRD
200
200
t
CK
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262) (Continued)
Notes: 15, 1215, 29, 40; notes appear on pages 2023; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-335
-262
UNITS
NOTES
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
18
2003 Micron Technology, Inc.
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202)
Notes: 15, 1215, 29, 40; notes appear on pages 2023; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-26A
-265
-202
UNITS
NOTES
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
t
AC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
CK high-level width
t
CH
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
CK low-level width
t
CL
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
26
Clock cycle time
CL=2.5
t
CK (2.5)
7.5
13
7.5
13
8
13
ns
40, 46
CL=2
t
CK (2)
7.5
13
10
13
10
13
ns
40, 46
DQ and DM input hold time relative to DQS
t
DH
0.5
0.5
0.6
ns
23, 27
DQ and DM input setup time relative to DQS
t
DS
0.5
0.5
0.6
ns
23, 27
DQ and DM input pulse width (for each input)
t
DIPW
1.75
1.75
2
ns
27
Access window of DQS from CK/CK#
t
DQSCK -0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
DQS input high pulse width
t
DQSH
0.35
0.35
0.35
t
CK
DQS input low pulse width
t
DQSL
0.35
0.35
0.35
t
CK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
t
DQSQ
0.5
0.5
0.6
ns
22, 23
Write command to first DQS latching transition
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
t
CK
DQS falling edge to CK rising - setup time
t
DSS
0.20
0.20
0.20
t
CK
DQS falling edge from CK rising - hold time
t
DSH
0.20
0.20
0.20
t
CK
Half clock period
t
HP
t
CH,
t
CL
t
CH,
t
CL
t
CH,
t
CL
ns
8
Data-out high-impedance window from CK/CK#
t
HZ
+0.75
+0.75
+0.8
ns
16, 37
Data-out low-impedance window from CK/CK#
t
LZ
-0.75
-0.75
-0.8
ns
16, 38
Address and control input hold time (fast slew
rate)
t
IH
F
0.90
0.90
1.1
ns
12
Address and control input setup time (fast slew rate)
t
IS
F
.900
0.90
1.1
ns
12
Address and control input hold time (slow slew rate)
t
IH
S
1
1
1.1
ns
12
Address and control input setup time (slow slew
rate)
t
IS
S
1
1
1.1
ns
12
Address and Control input pulse width (for each
input)
t
IPW
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
t
MRD
15
15
16
ns
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
t
QH
t
HP -
t
QHS
t
HP -
t
QHS
t
HP -
t
QHS
ns
22, 23
Data hold skew factor
t
QHS
0.75
0.75
1
ns
ACTIVE to PRECHARGE command
t
RAS
40
120,000
40
120,000
40
120,000
ns
31
ACTIVE to READ with Auto precharge command
t
RAP
20
20
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
t
RC
65
65
70
ns
AUTO REFRESH command period
t
RFC
75
75
80
ns
44
ACTIVE to READ or WRITE delay
t
RCD
20
20
20
ns
PRECHARGE command period
t
RP
20
20
20
ns
512MB, 1GB (x64)
200-PIN DDR SODIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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2003 Micron Technology, Inc.
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
37
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
ACTIVE bank a to ACTIVE bank b command
t
RRD
15
15
15
ns
DQS write preamble
t
WPRE
0.25
0.25
0.25
t
CK
DQS write preamble setup time
t
WPRES
0
0
0
ns
18, 19
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
t
CK
17
Write recovery time
t
WR
15
15
15
ns
Internal WRITE to READ command delay
t
WTR
1
1
1
t
CK
Data valid output window
NA
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
ns
22
REFRESH to REFRESH command interval
t
REFC
70.3
70.3
70.3
s
21
Average periodic refresh interval
t
REFI
7.8
7.8
7.8
s
21
Terminating voltage delay to V
DD
t
VTD
0
0
0
ns
Exit SELF REFRESH to non-READ command
t
XSNR
75
75
80
ns
Exit SELF REFRESH to READ command
t
XSRD
200
200
200
t
CK
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202) (Continued)
Notes: 15, 1215, 29, 40; notes appear on pages 2023; 0C
T
A
+70C; V
DD
= V
DD
Q = +2.5V 0.2V
AC CHARACTERISTICS
-26A
-265
-202
UNITS
NOTES
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
20
2003 Micron Technology, Inc.
Notes
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
4. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
REF
(or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
IL
(AC)
and V
IH
(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. V
REF
is expected to equal V
DD
Q/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
REF
may not exceed 2 percent of the
DC value. Thus, from V
DD
Q/2, V
REF
is allowed
25mV for DC error and an additional 25mV for
AC noise. This measurement is to be taken at the
nearest V
REF
bypass capacitor.
7. V
TT
is not applied directly to the device. V
TT
is a
system supply for signal termination resistors, is
expected to be set equal to V
REF
and must track
variations in the DC level of V
REF
.
8. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for-335 and -265 with the outputs open.
9. Enables on-chip refresh and address counters.
10. I
DD
specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. V
DD
= +2.5V 0.2V,
V
DD
Q = +2.5V 0.2V, V
REF
= V
SS
, f = 100 MHz, =
25C, V
OUT
(DC) = V
DD
Q/2, V
OUT
(peak to peak) T
A
= 0.2V. DM input is grouped with I/O pins, reflect-
ing the fact that they are matched in loading.
12. Command/Address input slew rate = 0.5V/ns. For
-262, -26A, and -265 with slew rates 1V/ns and
faster,
t
IS and
t
IH are reduced to 900ps; for -335,
they are reduced to 750ps. If the slew rate is less
than 0.5 V/ns, timing must be derated:
t
IS has an
additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns, while
t
IH remains
constant. If the slew rate exceeds 4.5V/ns, func-
tionality is uncertain.
13. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
REF
.
14. Inputs are not recognized as valid until V
REF
stabi-
lizes. Exception: during the period before V
REF
stabilizes, CKE
0.3 x V
DD
Q is recognized as LOW.
15. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
V
TT
.
16. tHZ and
t
LZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
17. The intent of the Don't Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above V
IH
DC (MIN) then it must
not transition low (below V
IH
DC) prior to
t
DQSH
(MIN).
18. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
t
DQSS.
20. MIN (
t
RC or
t
RFC) for I
DD
measurements is the
smallest multiple of
t
CK that meets the minimum
absolute Value for the respective parameter.
t
RAS
(MAX) for I
DD
measurements is the largest multi-
Output
(V
OUT
)
Reference
Point
50
V
TT
30pF
512MB, 1GB (x64)
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21
2003 Micron Technology, Inc.
ple of
t
CK that meets the maximum absolute
value for
t
RAS.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 7.8125s. However, an AUTO
REFRESH command must be asserted at least
once every 70.3s; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
22. The valid data window is derived by achieving
other specifications:
t
HP (
t
CK/2),
t
DQSQ, and
t
QH
(
t
QH =
t
HP -
t
QHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 8, Derating
Data Valid Window, shows derating curves for
duty cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, V
IL
(AC)
or V
IH
(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, V
IL
(DC)
or V
IH
(DC).
26. JEDEC specifies CK and CK# input slew rate must
be
1V/ns (2V/ns differentially).
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
DS and
t
DH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. V
DD
must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
Figure 8: Derating Data Valid Window
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
3.400
3.350
3.300
3.250
3.200
3.150
3.100
3.050
3.000
2.950
2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5 49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
ns
-335
-262/-26A/-265 @ tCK = 10ns
-202 @ tCK = 10ns
-262/-26A/-265 @ tCK = 7.5ns
-202 @ tCK = 8ns
NA
512MB, 1GB (x64)
200-PIN DDR SODIMM
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2003 Micron Technology, Inc.
30.
t
HP min is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not
allowed to be issued until
t
RAS(MIN) can be satis-
fied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
34. The voltage levels used are derived from a mini-
mum V
DD
level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 1.5V for a
pulse width
3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
IL
undershoot:
V
IL
(MIN) = -1.5V for a pulse width
3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
36. V
DD
and V
DD
Q must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
t
HZ(MAX) and the last DVW.
t
HZ
(MAX) will prevail over
t
DQSCK (MAX) +
t
RPST
(MAX) condition.
t
LZ (MIN) will prevail over
t
DQSCK (MIN) +
t
RPRE (MAX) condition.
38. For slew rates greater than 1V/ns the (LZ) transi-
tion will start about 310ps earlier.
39. During Initialization, V
DD
Q, V
TT
, and V
REF
must
be equal to or less than V
DD
+ 0.3V. Alternatively,
V
TT
may be 1.35V maximum during power up,
even if V
DD
/V
DD
Q are 0.0V, provided a minimum
of 42
W of series resistance is used between the V
TT
supply and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
512MB, 1GB (x64)
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2003 Micron Technology, Inc.
41. For -265, -26A, -262 and -335, I
DD
3
N
is specified to
be 35mA at 100 MHz.
42. Random addressing changing and 50 percent of
data changing at every transfer.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
REF later.
45. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is "worst case."
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
512MB, 1GB (x64)
200-PIN DDR SODIMM
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SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 11, Data Validity, and Figure 12, Defi-
nition of Start and Stop).
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shwon in Fig-
ure 13, Acknowledge Response From Receiver).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 11: Data Validity
Figure 12: Definition of Start and Stop
Figure 13: Acknowledge Response From Receiver
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
512MB, 1GB (x64)
200-PIN DDR SODIMM
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2003 Micron Technology, Inc.
Figure 14: SPD EEPROM Timing Diagram
Table 17: EEPROM Device Select Code
Most significant bit (b7) is sent first.
SELECT CODE
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
B0
Memory Area Select Code (two arrays)
1
0
1
0
SA2
SA1
SA0
RW
Protection Register Select Code
0
1
1
0
SA2
SA1
SA0
RW
Table 18: EEPROM Operating Modes
MODE
RW BIT
WC
BYTES
INITIAL SEQUENCE
Current Address Read
1
V
IH
or V
IL
1
START, Device Select, RW = `1'
Random Address Read
0
V
IH
or V
IL
1
START, Device Select, RW = `0', Address
1
V
IH
or V
IL
1
reSTART, Device Select, RW = `1'
Sequential Read
1
V
IH
or V
IL
1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = `0'
Page Write
0
V
IL
16
START, Device Select, RW = `0'
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
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NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
V
DDSPD
2.3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
0.7
V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT: SCL = SDA = V
DD
- 0.3V; All other inputs = V
DD
or V
SS
I
SB
30
A
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
I
CC
2
mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
SS
; V
DDSPD
= +2.3V
TO
+3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.2
0.9
s
1
Time the bus must be free before a new transition can start
t
BUF
1.3
s
Data-out hold time
t
DH
200
ns
SDA and SCL fall time
t
F
300
ns
2
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
0.6
s
Clock HIGH period
t
HIGH
0.6
s
Noise suppression time constant at SCL, SDA inputs
t
I
50
ns
Clock LOW period
t
LOW
1.3
s
SDA and SCL rise time
t
R
0.3
s
2
SCL clock frequency
f
SCL
400
KHz
Data-in setup time
t
SU:DAT
100
ns
Start condition setup time
t
SU:STA
0.6
s
3
Stop condition setup time
t
SU:STO
0.6
s
WRITE cycle time
t
WRC
10
ms
4
512MB, 1GB (x64)
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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2003 Micron Technology, Inc.
Table 21: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
0
Number of Bytes Used by Micron
128
80
80
1
Total Number of Bytes in SPD Device
256
08
08
2
Fundamental Memory Type
SDRAM DDR
07
07
3
Number of Rows Addresses on Assembly
13
0D
0D
4
Number of Column Addresses on Assembly
11, 12
0A
0B
5
Number of Physical Ranks on DIMM
2
02
02
6
Module Data With
64
40
40
7
Module Data With (Continued)
0
00
00
8
Moduel Voltage Interface Levels
SSTL 2.5V
04
04
9
SDRAM Cycle Time, (
t
CK), CAS Latency = 2.5
(See note 1)
6ns (-335)
7ns (-262/-26A)
7.5ns( -265)
8ns (-202)
60
70
75
80
60
70
75
80
10
SDRAM Access From Clock,(
t
AC),
CAS Latency = 2.5
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
11
Module Configuration Type
Non-ECC
00
00
12
Refresh Rate/Type
7.8s/SELF
82
82
13
SDRAM Device Width (Primary SDRAM)
x8
08
08
14
Error-checking SDRAM Data Width
Non-ECC
00
00
15
Minimum Clock Delay, Back-to-Back Random
Column Access
1 clock
01
01
16
Burst Lengths Supported
2, 4, 8
0E
0E
17
Number of Banks on SDRAM Device
4
04
04
18
CAS Latencies Supported
2, 2.5
0C
0C
19
CS Latency
0
01
01
20
WE Latency
1
02
02
21
SDRAM Module Attributes
Unbuffered/Diff. Clock
20
20
22
SDRAM Device Attributes: General
Fast/Concurrent AP
C0
C0
23
SDRAM Cycle Time, (
t
CK), CAS Latency = 2
(See note 1)
7.5ns (-335/-262/-26A)
10ns (-265/-202)
75
A0
75
A0
24
SDRAM Access From CK, (
t
AC), CAS Latency = 2
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
25
SDRAM Cycle Time, (
t
CK), CAS Latency = 1.5
N/A
00
00
26
SDRAM Access From CK, (
t
AC),
CAS Latency = 1.5
N/A
00
00
27
Minimum Row Precharge Time, (
t
RP)
18ns (-335)
15ns (-262)
20ns (-26A/-265/-202)
48
3C
50
48
3C
50
28
Minimum Row to Row Active, (
t
RRD)
12ns (-335)
15 ns (-262/-26A/-265/-202)
30
3C
30
3C
29
Minimum RAS# to CAS# Delay, (
t
RCD)
18ns (-335)
15ns (-262)
20ns (-26A/-265/-202)
48
3C
50
48
3C
50
512MB, 1GB (x64)
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2003 Micron Technology, Inc.
30
Minimum RAS# Pulse Width, (
t
RAS)
(See note 2)
42ns (-335)
45ns (-262/-26A/-265)
40ns (-202)
2A
2D
28
2A
2D
28
31
Module Rank Density
256MB, 512MB
40
80
32
Address and Command Setup Time, (
t
IS)
(See note 3)
0.8ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
33
Address and Command Hold Time, (
t
IH)
(See note 3)
0.8ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
34
Data/ Data Mask Input Setup Time, (
t
DS)
0.45ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
45
50
60
45
50
60
35
Data/ Data Mask Input Hold Time, (
t
DH)
0.45ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
45
50
60
45
50
60
36-40
Reserved
00
00
41
Minimum Active Auto Refresh Time (
t
RC)
60ns (-335/-262)
65ns (-26A/-265)
70ns (-202)
3C
41
46
3C
41
46
42
Minimum Auto Refresh to Active/Auto Refresh
Command Period, (
t
RFC)
72ns (-335)
75ns (-262/-26A/-265)
80ns (-202)
48
4B
50
48
4B
50
43
SDRAM Device Max Cycle Time (
t
CK
MAX
)
12ns (-335)
13ns (-262/-26A/-265/-202)
30
34
30
34
44
SDRAM Device Max DQS-DQ Skew Time
(
t
DQSQ)
0.40ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
28
32
3C
28
32
3C
45
SDRAM Device Max Read Data Hold Skew
Factor (
t
QHS)
0.5ns (-335)
0.75ns (-26A/-265)
1.0ns (-202)
50
75
A0
50
75
A0
46
Reserved
00
00
47
DIMM Height
01
01
4861
Reserved
00
00
62
SPD Revision
Release 1.0
10
10
63
Checksum for Bytes 0-62
-335
-262
-26A
-265
-202
30
BB
E8
18
B3
5F
FC
29
59
F4
64
Manufacturer's JEDEC ID Code
MICRON
2C
2C
65-71
Manufacturer's JEDEC ID Code (Continued)
00
00
72
Manufacturing Location
0112
010C
010D
73-90
Module Part Number (ASCII)
Variable Data
Variable Data
91
PCB Identification Code
1-9
01-09
01-09
92
Identification Code (Continued)
0
00
00
93
Year of Manufacture in BCD
Variable Data
Variable Data
Table 21: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
29
2003 Micron Technology, Inc.
NOTE:
1. Device latencies used for SPD values.
2. The value of
t
RAS used for -262/-26A/-265 modules is calculated from
t
RC -
t
RP. Actual device spec value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
94
Week of Manufacture in BCD
Variable Data
Variable Data
95-98
Module Serial Number
Variable Data
Variable Data
99-127
Manufacturer-Specific Data (RSVD)
Table 21: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
30
2003 Micron Technology, Inc.
Figure 15: 200-PIN SODIMM Dimensions 512MB
NOTE:
All dimensions are in inches (millimeters)
or typical where noted.
0.150 (3.80)
MAX
0.043 (1.10)
0.035 (0.90)
PIN 1
2.666 (67.72)
2.656 (67.45)
0.787 (20.00)
TYP
0.071 (1.80)
(2X)
0.024 (.61)
TYP
0.018 (.46)
TYP
0.079 (2.00) R
(2X)
PIN 199
PIN 200
PIN 2
FRONT VIEW
0.079 (2.00)
0.236 (6.00)
2.504 (63.60)
0.096 (2.44)
0.039 (.99)
TYP
1.255 (31.88)
1.245 (31.62)
TYP
BACK VIEW
U1
U2
U3
U4
U5
U6
U7
U8
U17
U9
U10
U11
U12
U13
U14
U15
U16
MAX
MIN
512MB, 1GB (x64)
200-PIN DDR SODIMM
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice..
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
31
2003 Micron Technology, Inc
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
Figure 16: 200-PIN SODIMM Dimensions 1GB
NOTE:
All dimensions are in inches (millimeters)
or typical where noted.
Data Sheet Designation
Released (No Mark): This data sheet contains mini-
mum and maximum limits specified over the complete
power supply and temperature range for production
devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.
U1
U2
U3
U4
U5
U6
U7
U8
U17
U9
U10
U11
U12
U16
U15
U14
U13
0.150 (3.80)
MAX
0.043 (1.10)
0.035 (0.90)
PIN 1
2.666 (67.72)
2.656 (67.45)
0.787 (20.00)
TYP
0.071 (1.80)
(2X)
0.024 (.61)
TYP
0.018 (.46)
TYP
0.079 (2.00) R
(2X)
PIN 199
PIN 200
PIN 2
FRONT VIEW
0.079 (2.00)
0.236 (6.00)
2.504 (63.60)
0.096 (2.44)
0.039 (.99)
TYP
1.255 (31.88)
1.245 (31.62)
TYP
BACK VIEW
MAX
MIN