2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

DRAM
MODULE

MT9LD272A(X), MT18LD472A(X)

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html

FEATURES

· JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin,

dual in-line memory module (DIMM)

· 16MB (2 Meg x 72) and 32MB (4 Meg x 72)
· Nonbuffered
· High-performance CMOS silicon-gate process
· Single +3.3V

0.3V power supply

· All inputs, outputs and clocks are TTL-compatible
· Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

· 2,048-cycle refresh distributed across 32ms
· FAST-PAGE-MODE (FPM) or Extended Data-Out

(EDO) PAGE MODE access cycles

· Serial presence-detect (SPD)

OPTIONS

MARKING

· Package

168-pin DIMM (gold)

· Timing

50ns access

-5*

60ns access

-6

· Access Cycles

FAST PAGE MODE

None

EDO PAGE MODE

*EDO version only

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

PIN

SYMBOL

127

DQ0

OE2#

DQ32

128

RFU

DQ1

RAS2#

DQ33

129 NC/RAS3#*

DQ2

CAS2#

DQ34

130

CAS6#

DQ3

CAS3#

DQ35

131

CAS7#

WE2#

132

RFU

DQ4

DQ36

133

DQ5

DQ37

134

DQ6

DQ38

135

DQ7

CB2

DQ39

136

CB6

DQ8

CB3

DQ40

137

CB7

138

DQ9

DQ16

DQ41

139

DQ48

DQ10

DQ17

DQ42

140

DQ49

DQ11

DQ18

DQ43

141

DQ50

DQ12

DQ19

100

DQ44

142

DQ51

DQ13

101

DQ45

143

DQ20

102

144

DQ52

DQ14

103

DQ46

145

DQ15

RFU

104

DQ47

146

RFU

CB0

105

CB4

147

CB1

106

CB5

148

DQ21

107

149

DQ53

DQ22

108

150

DQ54

DQ23

109

151

DQ55

110

152

WE0#

DQ24

111

RFU

153

DQ56

CAS0#

DQ25

112

CAS4#

154

DQ57

CAS1#

DQ26

113

CAS5#

155

DQ58

RAS0#

DQ27

114

156

DQ59

OE0#

115

RFU

157

DQ28

116

158

DQ60

DQ29

117

159

DQ61

DQ30

118

160

DQ62

DQ31

119

161

DQ63

120

162

121

163

A10

122

NC (A11)

164

NC (A12)

123

NC (A13)

165

SA0

SDA

124

166

SA1

SCL

125

RFU

167

SA2

RFU

126

RFU

168

PIN ASSIGNMENT (Front View)

168-Pin DIMM

KEY TIMING PARAMETERS

EDO Operating Mode

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

13ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

FPM Operating Mode

SPEED

RAC

CAC

-6

110ns

60ns

35ns

30ns

15ns

40ns

NOTE: Pin symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

PART NUMBERS

EDO Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT9LD272AG-5 X

2 Meg x 72 ECC

50ns

MT9LD272AG-6 X

2 Meg x 72 ECC

60ns

MT18LD472AG-5 X

4 Meg x 72 ECC

50ns

MT18LD472AG-6 X

4 Meg x 72 ECC

60ns

FPM Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT9LD272AG-6

2 Meg x 72 ECC

60ns

MT18LD472AG-6

4 Meg x 72 ECC

60ns

EDO PAGE MODE

EDO PAGE MODE, designated by the "X" version, is an

accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(

CP) to occur without the output data going invalid. This

elimination of CAS# output control provides for pipelined
READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.

During an application, if the DQ outputs are wire OR'd,

OE# must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after

OFF, which is refer-

enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM
data sheet for additional information on EDO functional-
ity.)

REFRESH

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is pre-
served by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-
ONLY, CBR or HIDDEN) so that all combinations of RAS#
addresses (A0-A9/A10) are executed at least every

REF,

regardless of sequence. The CBR REFRESH cycle will in-
voke the internal refresh counter for automatic RAS# ad-
dressing.

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-detect

(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM's SCL (clock) and SDA (data) signals,

GENERAL DESCRIPTION

The MT9LD272A(X) and MT18LD472A(X) are randomly

accessed 16MB and 32MB memories organized in a x72
configuration. They are specially processed to operate from
3V to 3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit is uniquely

addressed through the 21/22 address bits, which are en-
tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-
A10) at CAS# time.

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# was taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data-
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no WRITE will occur, and the data-outputs will drive
read data from the accessed location.

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition, which

is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.

SPD STOP CONDITION

All communications are terminated by a stop condition,

which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).

The SPD device will always respond with an acknowl-

edge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.

SCL

SDA

DATA STABLE

DATA
CHANGE

Figure 1

DATA VALIDITY

SCL

SDA

START
BIT

STOP
BIT

Figure 2

DEFINITION OF START AND STOP

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

Figure 3

ACKNOWLEDGE RESPONSE FROM RECEIVER

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

FUNCTIONAL BLOCK DIAGRAM

MT9LD272A(X) (16MB)

A0-A10

OE2#

WE2#

CAS4#

RAS2#

CAS5#

CAS7#

CAS6#

U1-U9 = MT4LC2M8B1 FAST PAGE MODE

U1-U9 = MT4LC2M8E7 EDO PAGE MODE

OE0#

WE0#

CAS0#

RAS0#

CAS1#

CAS3#

CAS2#

DQ0-DQ7

DQ8-DQ15

CB0-CB7

DQ16-DQ23

DQ32-DQ39

DQ40-DQ41

DQ48-DQ55

DQ56-DQ63

DQ24-DQ31

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ7

A0A10

WE#

OE#

RAS#

CAS#

SPD

SCL

SDA

SA0 SA1 SA2

U1-U9

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

FUNCTIONAL BLOCK DIAGRAM

MT18LD472A(X) (32MB)

U1-U18 = MT4LC4M4B1 FAST PAGE MODE

U1-U18 = MT4LC4M4E8 EDO PAGE MODE

OE0#

CAS1#

CAS2#

CAS3#

WE0#

CAS0#

OE2#

CAS5#

CAS6#

CAS7#

WE2#

CAS4#

A0-A10

RAS0#

RAS2#

SPD

SCL

SDA

SA0

SA1

SA2

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U10

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U11

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U12

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U13

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U14

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U15

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U16

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

U17

A0A10

WE#

OE#

RAS#

CAS#

DQ0-DQ3

DQ4-DQ7

DQ8-DQ11

DQ12-DQ15

DQ16-DQ19

DQ20-DQ23

DQ24-DQ27

DQ28-DQ31

DQ32-DQ35

DQ36-DQ39

DQ40-DQ43

DQ44-DQ47

CB4-CB7

DQ48-DQ51

DQ52-DQ55

DQ56-DQ59

DQ06-DQ63

U18

A0A10

U1-U18

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

PIN DESCRIPTIONS

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

30, 45

RAS0#, RAS2#

Input

Row-Address Strobe: RAS# is used to clock-in the row-
address bits. Two RAS# inputs allow for one x72 bank or
two x36 banks.

28, 29, 46, 47, 112,

CAS0#-CAS7#

Input

Column-Address Strobe: CAS# is used to clock-in the

113, 130, 131

column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS#
inputs allow byte access control for any memory bank
configuration.

27, 48

WE0#, WE2#

Input

Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.

31, 44

OE0#, OE2#

Input

Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.

33-38, 117-121

A0-A10

Input

Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.

2-5, 7-11, 13-17, 19-20,

DQ0-DQ63

Input/

Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to

55-58, 60, 65-67, 69-72,

Output

the addressed DRAM location. For READ access cycles,

74-77, 86-89,91-95,

DQ0-DQ63 act as outputs for the addressed DRAM

97-101, 103-104,

location.

139-142, 144, 149-151,

153-156, 158-161

21-22, 52-53, 105-106,

CB0-CB7

Input/Output

Check Bits.

136-137

42, 62, 111, 115,

RFU

Reserved for Future Use: These pins should be left

125-126, 128, 132, 146

unconnected.

6, 18, 26, 40, 41, 49, 59,

Supply

Power Supply: +3.3V

0.3V.

73, 84, 90, 102, 110,

124, 133, 143, 157, 168

1, 12, 23, 32, 43, 54, 64,

Supply

Ground.

68, 78, 85, 96, 107, 116,

127, 138, 148, 152, 162

SDA

Input/Output

Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.

SCL

Input

Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.

165-167

SA0-SA2

Input

Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

SERIAL PRESENCE-DETECT MATRIX

BYTE

DESCRIPTION

ENTRY (VERSION)

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

HEX

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

FAST PAGE MODE

EDO PAGE MODE

NUMBER OF ROW ADDRESSES

NUMBER OF COLUMN ADDRESSES

10 (16MB)

11 (32MB)

NUMBER OF BANKS

DATA WIDTH

x72

DATA WIDTH (continued)

NONE

VOLTAGE INTERFACE

LVTTL

RAS# ACCESS TIME (

RAC)

50ns (-5)

60ns (-6)

CAS# ACCESS TIME (

CAC)

13ns (-5)

15ns (-6)

MODULE CONFIGURATION TYPE

ECC

REFRESH RATES

15.625

s/NORMAL

DRAM WIDTH (PRIMARY DRAM)

x8 (16MB)

x4 (32MB)

ERROR CHECKING DRAM DATA WIDTH

x8 (16MB)

x4 (32MB)

15-61

RESERVED

SPD REVISION

REV. 0

CHECKSUM FOR BYTES 0-62

16MB -5 (EDO)

16MB -6 (EDO)

16MB -6 (FPM)

32MB -5 (EDO)

32MB -6 (EDO)

32MB -6 (FPM)

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71

MANUFACTURER'S JEDEC CODE (CONT.)

MANUFACTURING LOCATION

73-90

MODULE PART NUMBER (ASCII)

PCB IDENTIFICATION CODE

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

WEEK OF MANUFACTURE IN BCD

95-98

MODULE SERIAL NUMBER

99-125

MANUFACTURE SPECIFIC DATA (RSVD)

NOTE:

1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Pin Relative to V

................. -1V to +4.6V

Voltage on Inputs or I/O Pins

Relative to V

................................................ -1V to +4.6V

Operating Temperature, T

(ambient) .......... 0

C to +70

Storage Temperature (plastic) .................... -55

C to +125

Power Dissipation ............................................................. 9W

*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

SIZE

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

ALL

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

ALL

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

ALL

-0.5

0.8

INPUT LEAKAGE CURRENT:

CAS0#-CAS7#

16MB

-4

Any input 0V

+ 0.3V

32MB

-6

(All other pins not under test = 0V)

A0-A10

16MB

-18

32MB

-36

WE0#, WE2#,

16MB

-10

OE0#, OE2#

32MB

-18

RAS0#-RAS3#

16MB

-10

32MB

-18

OUTPUT LEAKAGE CURRENT:

DQ0-DQ63,

16MB

-5

DQ is disabled; 0V

OUT

+ 0.3V

CB0-CB7

32MB

-5

OUTPUT LEVELS:

ALL

2.4

Output High Voltage (I

OUT

= -2mA)

Output Low Voltage (I

OUT

= 2mA)

ALL

0.4

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 5, 6) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

SIZE

-5*

-6

UNITS

NOTES

STANDBY CURRENT: TTL

16MB

(RAS# = CAS# = V

)

32MB

STANDBY CURRENT: CMOS

16MB

(RAS# = CAS# = V

- 0.2V)

32MB

OPERATING CURRENT: Random READ/WRITE

16MB

990

900

3, 24

Average power supply current

32MB

1,980

1,800

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

OPERATING CURRENT: FAST PAGE MODE

16MB

720

3, 24

Average power supply current

32MB

1,440

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

OPERATING CURRENT: EDO PAGE MODE ("X" version only)

16MB

990

900

3, 24

Average power supply current

(X only)

32MB

1,980

1,800

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

REFRESH CURRENT: RAS#-ONLY

16MB

990

900

3, 24

Average power supply current

32MB

1,980

1,800

(RAS# cycling, CAS# = V

RC =

RC [MIN])

REFRESH CURRENT: CBR

16MB

990

900

3, 4

Average power supply current

32MB

1,980

1,800

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

* EDO version only

MAX

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

CAPACITANCE

PARAMETER

SYMBOL

16MB

32MB

UNITS

NOTES

Input Capacitance: A0-A10

Input Capacitance: WE0#, WE2#, OE0#, OE2#

Input Capacitance: RAS0#, RAS2#

Input Capacitance: CAS0#-CAS7#

Input Capacitance: SCL, SA0-SA2

Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA

MAX

FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column address to WE# delay time

AWD

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

CAS# to WE# delay time

CWD

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output disable

Output enable

OE# hold time from WE# during READ-MODIFY-WRITE cycle

OEH

Output buffer turn-off delay

OFF

19, 25, 26

OE# setup prior to RAS# during HIDDEN REFRESH cycle

ORD

FAST-PAGE-MODE READ or WRITE cycle time

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

FAST-PAGE-MODE READ-WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (FAST PAGE MODE)

RASP

125,000

Random READ or WRITE cycle time

110

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (2,048 cycles)

REF

RAS# precharge time

RAS# to CAS# precharge time

RPC

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ-WRITE cycle time

RWC

155

RAS# to WE# delay time

RWD

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

WRITE command pulse width

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address setup to CAS# precharge

ACH

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column-address to WE# delay time

AWD

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

Data output hold after CAS# LOW

COH

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

CAS# to WE# delay time

CWD

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output disable

Output enable

OE# hold time from WE# during

OEH

10/12*

READ-MODIFY-WRITE cycle

OE# HIGH hold time from CAS# HIGH

OEHC

OE# HIGH pulse width

OEP

OE# LOW to CAS# HIGH setup time

OES

Output buffer turn-off delay

OFF

19, 26

OE# setup prior to RAS#

ORD

during HIDDEN REFRESH cycle

EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (EDO PAGE MODE)

RASP

125,000

Random READ or WRITE cycle time

104

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (2,048 cycles)

REF

RAS# precharge time

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 29) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

RAS# to CAS# precharge time

RPC

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ WRITE cycle time

RWC

116

140

RAS# to WE# delay time

RWD

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

Output disable delay from WE# (CAS# HIGH)

WHZ

WRITE command pulse width

WE# pulse to disable at CAS# HIGH

WPZ

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

0.7 V

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

STANDBY CURRENT:

SCL = SDA = V

- 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

Time the bus must be free before a new transition can start

BUF

4.7

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

Start condition hold time

HD:STA

Clock HIGH period

HIGH

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

SDA and SCL rise time

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

Stop condition setup time

SU:STO

4.7

WRITE cycle time

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

NOTES

1. All voltages referenced to V

2. This parameter is sampled. V

= +3.3V; f = 1 MHz.

3. I

is dependent on output loading. Specified values

are obtained with minimum cycle time and the
outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate

cycle time at which proper operation over the full
temperature range is ensured.

6. An initial pause of 100

s is required after power-up,

followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the

REF refresh

requirement is exceeded.

7. AC characteristics assume

T = 5ns for FPM and 2.5ns

for EDO.

8. V

(MIN) and V

(MAX) are reference levels for

measuring timing of input signals. Transition times
are measured between V

and V

(or between V

and V

9. In addition to meeting the transition rate specifica-

tion, all input signals must transit between V

and

(or between V

and V

) in a monotonic manner.

10. If CAS# = V

, data output is High-Z.

11. If CAS# = V

, data output may contain data from the

last valid READ cycle.

12. Measured with a load equivalent to two TTL gates

and 100pF and V

= 0.8V and V

= 2V.

13. Requires that

AA and

RAC are not violated.

14. Requires that

AA and

CAC are not violated.

15. If CAS# is LOW at the falling edge of RAS#, Q will be

maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for

CP.

16. The

RCD (MAX) limit is no longer specified.

RCD

(MAX) was specified as a reference point only. If

RCD was greater than the specified

RCD (MAX)

limit, then access time was controlled exclusively by

CAC (

RAC [MIN] no longer applied). With or

without the

RCD (MAX) limit,

AA and

CAC must

always be met.

17. The

RAD (MAX) limit is no longer specified.

RAD

(MAX) was specified as a reference point only. If

RAD was greater than the specified

RAD (MAX)

limit, then access time was controlled exclusively by

AA (

RAC and

CAC no longer applied). With or

without the

RAD (MAX) limit,

AA,

RAC and

CAC

must always be met.

18. Either

RCH or

RRH must be satisfied for a READ

cycle.

19.

OFF (MAX) defines the time at which the output

achieves the open circuit condition and is not
referenced to V

or V

20. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.

21. LATE WRITE and READ-MODIFY-WRITE cycles

must have both

OD and

OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW after

OEH is met. If CAS# goes HIGH prior to OE# going

back LOW, the DQs will remain open.

22. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.

23.

WCS,

RWD,

AWD and

CWD are not restrictive

operating parameters.

WCS applies to EARLY

WRITE cycles.

RWD,

AWD and

CWD apply to

READ-MODIFY-WRITE cycles. If

WCS

(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If

WCS <

WSC (MIN) and

RWD

RWD (MIN),

AWD

AWD (MIN) and

CWD

CWD (MIN), the cycle is a READ-MODIFY-WRITE

and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.

WCS,

RWD,

CWD and

AWD are not applicable in a LATE

WRITE cycle.

24. Column address changed once each cycle.
25. The 3ns minimum parameter guaranteed by design.
26. With the FPM option,

OFF is determined by the first

RAS# or CAS# signal to transition HIGH. In compari-
son,

OFF on an EDO option is determined by the

latter of the RAS# and CAS# signals to transition
HIGH.

27. Applies to both FPM and EDO modules.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

NOTES (continued)

28. The SPD EEPROM WRITE cycle time (

WR) is the

time from a valid stop condition of a write sequence
to the end of the EEPROM internal erase/program
cycle. During the WRITE cycle, the EEPROM bus
interface circuit are disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not
respond to its slave address.

29. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not possible.

30. V

overshoot: V

(MAX) = V

+ 2V for a pulse

width

10ns, and the pulse width cannot be greater

than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

10ns, and the pulse

width cannot be greater than one third of the cycle
rate.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

READ CYCLE

,,,

tRRH

,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tOFF

tRCH

ROW

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

,,,

,,,,

,,,

t OD

t OE

OE#

V
V

IH
IL

COLUMN

,,,

,,,,

CAS#

WE#

,,,

NOTE 1

tACH

DON'T CARE

UNDEFINED

NOTE: 1. For EDO,

OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM,

OFF is referenced from rising edge of RAS# or

CAS#, whichever occurs first.

*EDO version only

OFF (EDO)

OFF (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RAS

10,000

RC (EDO)

104

RC (FPM)

110

RCD (EDO)

RCD (FPM)

RCH

RCS

RRH

RSH

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CRP

CSH (EDO)

CSH (FPM)

OD (EDO)

OD (FPM)

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EARLY WRITE CYCLE

DON'T CARE

UNDEFINED

,,,

V
V

IH
IL

,,,

VALID DATA

ROW

COLUMN

ROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

,,,

tDH

WE#

CAS#

tACH

,,,

*EDO version only

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

RWL

WCH

WCR

WCS

WP (FPM)

WP (EDO)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (FPM)

10,000

CAS (EDO)

10,000

CRP

CSH (FPM)

CSH (EDO)

CWL (FPM)

CWL (EDO)

RAD (FPM)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

FAST-PAGE-MODE READ CYCLE

,,,

,,,,

,,,

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

tRCS

tCAH

tASC

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRCH

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

DON'T CARE

UNDEFINED

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CPA

CRP

CSH

-6

SYMBOL

MIN

MAX

UNITS

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EDO-PAGE-MODE READ CYCLE

,,,

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

DON'T CARE

UNDEFINED

tOD

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tCAC

tCPA

tAA

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

RAS#

OE#

tCAS

CAS#

WE#

tCOH

tOEP

tOEHC

tOES

tACH

,,,,

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OEHC

OEP

OES

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

COH

CPA

CRP

CSH

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

FAST/EDO-PAGE-MODE EARLY WRITE CYCLE

,,,

tDS

tDH

tDS

tDH

tDS

tDH

tWCR

VALID DATA

tRWL

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD

tACH

tAR

COLUMN

ROW

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

RAS#

OE#

V
V

IH
IL

,,,

,,,,

,,,

DON'T CARE

UNDEFINED

,,,

*EDO version only

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

PC (FPM)

RAD (EDO)

RAD (FPM)

RAH

RASP

125,000

RCD (EDO)

RCD (FPM)

RSH

RWL

WCH

WCR

WCS

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CRP

CSH (EDO)

CSH (FPM)

CWL (EDO)

CWL (FPM)

PC (EDO)

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

,,,

VALID D

OUT

VALID D

ROW

,,,

COLUMN

ROW

,,,

,,,,

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

,,,

WE#

tACH

CAS#

DON'T CARE

UNDEFINED

,,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OD (EDO)

OD (FPM)

OEH (EDO)

10/12**

OEH (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RAS

10,000

RCD (EDO)

RCD (FPM)

RCS

RSH

RWC (EDO)

116

140

RWC (FPM)

155

RWD (EDO)

RWD (FPM)

RWL

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

AWD (EDO)

AWD (FPM)

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CRP

CSH (EDO)

CSH (FPM)

CWD (EDO)

CWD (FPM)

CWL (EDO)

CWL (FPM)

* EDO version only
**16MB DIMM

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

NOTE: 1.

PC is for LATE WRITE cycles only.

FAST/EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

* EDO version only
**16MB DIMM

,,,

,,,,

,,,

DON'T CARE

UNDEFINED

tOE

OPEN

D OUT

VALID

DIN

VALID

D OUT

VALID

D IN

VALID

D OUT

VALID

D IN

VALID

OPEN

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCLZ

tCAC

tRAC

tWP

tCWL

tRWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tRCS

tRWD

tASR

tRAH

tASC

tRAD

tAR

tCAH

tASC

tCAH

tASC

tCAH

tCP

tCAS

tRSH

tCP

tRP

tRASP

tCAS

tCP

tCAS

tRCD

tCSH

tPC

tCRP

ROW

COLUMN

ROW

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

WE#

tPRWC

,,,

tOEH

tOD

NOTE 1

,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OD (FPM)

OEH (EDO)

10/12**

OEH (FPM)

PC (EDO)

PC (FPM)

PRWC (EDO)

PRWC (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RASP

125,000

RCD (EDO)

RCD (FPM)

RCS

RSH

RWD (EDO)

RWD (FPM)

RWL

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

AWD (EDO)

AWD (FPM)

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CPA

CRP

CSH (EDO)

CSH (FPM)

CWD (EDO)

CWD (FPM)

CWL (EDO)

CWL (FPM)

OD (EDO)

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

V
V

IH
IL

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

t RASP

t RP

ROW

COLUMN (A)

COLUMN (N)

ROW

V
V

IH
IL

OE#

V
V

IOH
IOL

tCRP

t CSH

t CAS

t RCD

tASR

t RAH

tRAD

t ASC

tAR

t CAH

t ASC

t CAH

t ASC

t CAH

t CP

t RSH

VALID DATA

,,,

,,,,

t RCS

t RCH

t WCS

tOE

VALID

DATA (B)

VALID DATA (A)

t WHZ

tCAC

tCPA

tAA

tCAC

tAA

OPEN

tPC

RAC

tCOH

t WCH

t DS

t DH

tPC

COLUMN (B)

t ACH

CAS#

t CAS

t CP

DON'T CARE

UNDEFINED

,,,

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RSH

WCH

WCS

WHZ

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

COH

CPA

CRP

CSH

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

ROW

VALID

DATA

VALID DATA

,,,

OPEN

tCRP

tRCD

tCAS

tRSH

tRASP

tRP

tPC

tASC

tCAH

tAR

tASR

tRAD

tRAH

tWCS

tWP

tRWL

tRCS

tDH

tDS

tCAC

t OFF

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

V
V

OH
OL

WE#

V
V

IH
IL

,,,

tCSH

,,,

COLUMN

tCP

tASC

tCAH

tCWL

tWCH

t CLZ

tAA

RAC

DON'T CARE

UNDEFINED

NOTE 1

OE#

V
V

IH
IL

ROW

COLUMN

tCAS

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

NOTE: 1. Do not drive data prior to tristate.

-6

SYMBOL

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWL

WCH

WCS

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

CWL

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

EDO READ CYCLE

(with WE#-controlled disable)

,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tRCH

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tCSH

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

,,,

,,,,

,,,

t OD

t OE

OE#

V
V

IH
IL

COLUMN

,,,

,,,,

WE#

tWHZ

tWPZ

tCP

tASC

tRCS

COLUMN

tCLZ

DON'T CARE

UNDEFINED

CAS#

,,,

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

RAC

RAD

RAH

RCD

RCH

RCS

WHZ

WPZ

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

RAS#-ONLY REFRESH CYCLE

,,,

,,,,

,,,

ROW

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

tRC

tRAS

tRP

tCRP

tASR

tRAH

ROW

OPEN

V
V

OH
OL

tRPC

WE#

V
V

IH
IL

,,,

,,,,

,,,

,,,,

*EDO version only

CBR REFRESH CYCLE

(Addresses, OE# = DON'T CARE)

tRP

V
V

IH
IL

RAS#

tRAS

NOTE 1

OPEN

tCHR

tCSR

V
V

IH
IL

V
V

OH
OL

CAS#

tRP

tRAS

tRPC

tCSR

tRPC

tCHR

tCP

V
V

IH
IL

tWRP

tWRH

,,,

WE#

tWRP

tWRH

DON'T CARE

UNDEFINED

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RC (FPM)

110

RC (EDO)

104

RPC (FPM)

RPC (EDO)

WRH

WRP

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASR

CHR

CRP

CSR

RAH

RAS

10,000

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

HIDDEN REFRESH CYCLE

20, 27

(WE# = HIGH; OE# = LOW)

,,,

DON'T CARE

UNDEFINED

tCLZ

tOFF

,,,

OPEN

VALID DATA

OPEN

COLUMN

ROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP

tRCD

tRSH

tRAS

tRC

tRP

tCHR

tRAS

V
V

IOH
IOL

V
V

IH
IL

ADDR

V
V

IH
IL

CAS#

V
V

IH
IL

RAS#

,,,

,,,,

,,,

V
V

IH
IL

tOE

tOD

OE#

tORD

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CHR

CLZ (FPM)

CLZ (EDO)

CRP

OD (FPM)

OD (EDO)

OFF (FPM)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF (EDO)

ORD

RAC

RAD (FPM)

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

*EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM60.p65 Rev. 6/98

1998, Micron Technology, Inc.

2, 4 MEG x 72

NONBUFFERED DRAM DIMMs

OBSOLETE

NOTE:

1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

168-PIN DIMM

DF-12 (16MB)

.200 (5.08)

MAX

.054 (1.37)
.046 (1.17)

1.005 (25.53)

.995 (25.27)

PIN 1 (PIN 85 on backside)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00) R(2X)

FRONT VIEW

.128 (3.25)
.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

5.256 (133.50)
5.244 (133.20)

168-PIN DIMM

DF-13 (32MB)

.350 (8.89)

MAX

.054 (1.37)
.046 (1.17)

PIN 1

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

.250 (6.35) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00) R(2X)

PIN 84

FRONT VIEW

BACK VIEW

PIN 168

.128 (3.25)
.118 (3.00)

(2X)

PIN 85

2.625 (66.68)

1.661 (42.18)

1.005 (25.53)

.995 (25.27)

5.256 (133.50)
5.244 (133.20)

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