PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

SYNCHRONOUS
DRAM MODULE

MT9LSDT6472A - 512MB
MT18LSDT12872A - 1GB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· PC100- and PC133-compliant
· JEDEC-standard 168-pin, dual in-line memory

module (DIMM)

· Unbuffered, ECC-optimized pinout
· 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
· Single +3.3V power supply
· Fully synchronous; all signals registered on positive

Edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal SDRAM banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes Concurrent Auto

Precharge, and Auto Refresh Modes

· Self Refresh Mode
· 64ms, 8,192-cycle refresh
· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD)

Figure 1: 168-PIN DIMM (MO-161)

OPTIONS

MARKING

· Package

168-pin DIMM (gold)

· Frequency/CAS Latency

7.5ns (133 MHz)/CL = 2

-13E

7.5ns (133 MHz)/CL = 3

-133

10ns (100 MHz)/CL = 2

-10E

Table 1:

Address Table

512MB

MODULE

1GB

MODULE

Refresh Count

Device Banks

4 (BA0, BA1)

Device Configuration

64 Meg x 8

Row Addressing

8K (A0A12)

Column Addressing

2K (A0A9, A11) 2K (A0A9, A11)

Module Banks

1 (S0,S2)

2 (S0,S2; S1,S3)

Table 2:

Timing parameters

MODULE

MARKINGS

PC100

CL -

RCD -

PC133

CL -

RCD -

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

Table 3:

Part Numbers

PARTNUMBER

NOTE:

1. The designators for component and PCB revision

are the last two characters of each part number
Consult factory for current revision codes. Example:
MT9LSDT6472AG-133B1.

CONFIGURATION

SYSTEM

BUS

SPEED

MT9LSDT6472AG-13E_

64 Meg x 72

133 MHz

MT9LSDT6472AG-133_

64 Meg x 72

133 MHz

MT9LSDT6472AG-10E_

64 Meg x 72

100 MHz

MT18LSDT12872AG-13E_

128 Meg x 72

133 MHz

MT18LSDT12872AG-133_

128 Meg x 72

133 MHz

MT18LSDT12872AG-10E_

128 Meg x 72

100 MHz

Standard

Low Profile

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 2: Pin Locations (168-Pin DIMM)

PIN Locations (168-PIN Low Profile DIMM)

Table 4:

Pin Assignment
(168-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

CB1

DQ0

DQ21

DQ1

S2#

DQ22

DQ2

DQMB2

DQ23

DQ3

DQMB3

WE#

DQ24

DQ4

28 DQMB0

DQ25

DQ5

29 DQMB1

DQ26

DQ6

S0#

DQ27

DQ7

CB2

DQ8

CB3

DQ28

DQ29

DQ9

DQ16

DQ30

DQ10

DQ17

DQ31

DQ11

DQ18

DQ12

DQ19

CK2

DQ13

A10

BA1

DQ20

DQ14

SDA

DQ15

SCL

CB0

CK0

CKE1

Table 5:

Pin Assignment
(168-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

106

CB5

127

148

DQ32

107

128

CKE0

149

DQ53

DQ33

108

129

S3#

150

DQ54

DQ34

109

130 DQMB6

151

DQ55

DQ35

110

131 DQMB7 152

111

CAS#

132

153

DQ56

DQ36

112 DQMB4 133

154

DQ57

DQ37

113 DQMB5 134

155

DQ58

DQ38

114

S1#

135

156

DQ59

DQ39

115

RAS#

136

CB6

157

DQ40

116

137

CB7

158

DQ60

117

138

159

DQ61

DQ41

118

139

DQ48

160

DQ62

DQ42

119

140

DQ49

161

DQ63

DQ43

120

141

DQ50

162

100

DQ44

121

142

DQ51

163

CK3

101

DQ45

122

BA0

143

164

102

123

A11

144

DQ52

165

SA0

103

DQ46

124

145

166

SA1

104

DQ47

125

CK1

146

167

SA2

105

CB4

126

A12

147

168

Front View

Back View (Populated only for 1GB module)

Indicates a V

PIN 1

PIN 41

PIN 84

PIN 85

PIN125

PIN 168

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

See Figure 11, 512MB Module Dimensions and Figure 12, 1GB Module Dimensions for module dimensions.

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Table 6:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

27, 111, 115

RAS#, CAS#,

WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.

42, 79, 125, 163

CK0-CK3

Input

Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the
internal burst counter and controls the output registers.

63, 128

CKE0, CKE1

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND OPERATION (burst access in progress). CKE is synchronous
except after the device enters power- down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during power-
down and self refresh modes, providing low standby power.

30, 45,114, 129

S0# -S3#

Input

Chip Select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All com- mands are masked when S#
is registered HIGH. S# is considered part of the command code.

28, 29, 46, 47, 112, 113, 130,

131

DQMB0-DQMB7

Input

Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input data
is masked when DQMB is sampled HIGH during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency)
when DQMB is sampled HIGH during a READ cycle.

39, 122

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

33 - 38, 117 - 121, 123, 126

A0-A12

Input

Address Inputs: Provide the row address for ACTIVE commands, and
the column address and auto prcharge bit (A10) for READ/WRITE
commands, to select one location out of the memory arrary in the
respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10
LOW< device bank selected by BA0, BA1) or all device banks (A10
HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.

165-167

SA0-SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

21, 22, 52, 53, 105, 106, 136,

137

CB0-CB7

Input/

Output

Check Bits. ECC, 1-bit error detection and correction.

2-5, 7-11, 13-17, 19, 20, 55-58,
60, 65-67, 69-72, 74-77, 86-89,

91-95, 97-101, 103, 104,

139-142, 144, 149-151,

153-156,158-161

DQ0-DQ63

Input/

Output

Data I/O: Data bus.

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 3: Functional Block Diagram

Single Bank Module

DQM CS#

SA0

SPD

SDA

SA1

SA2

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQMB7

DQM CS#

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQMB6

DQM CS#

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQMB5

DQM CS#

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQMB4

DQM CS#

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMB3

DQM CS#

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQMB2

DQM CS#

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMB1

DQM CS#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQMB0

S2#

S0#

RAS#

CAS#

CKE0

WE#

RAS#: SDRAMs

CAS#: SDRAMs

CKE0: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

BA0: SDRAMs

BA1: SDRAMs

A0-A11

BA0

BA1

DQM CS#

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

SDRAMs

10pF

CK1, CK3

U1
U2
U3
U4
U5

CK0

U6
U7
U8
U9

CK2

3.3pF

SCL
WP

U10

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

Note:
1. All resistor values are 10

W unless otherwise specified.

2. Per industry standard, Micron modules use various component speed grades as

referenced in the module part numbering guide at

www.micron.com/

numberguide

SDRAMs = MT48LC64M8A2TG

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 4: Functional Block Diagram

Dual Bank Module

DQM CS#

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQMB7

DQM CS#

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQMB6

DQM CS#

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQMB5

DQM CS#

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQMB4

DQM CS#

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMB3

DQM CS#

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQMB2

DQM CS#

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMB1

DQM CS#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQMB0

S2#

S0#

DQM CS#

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQM CS#

U12

DQM CS#

U14

DQM CS#

U16

DQM CS#

U18

S1#

DQM CS#

U11

DQM CS#

U13

DQM CS#

U17

DQM CS#

U19

DQM CS#

U15

S3#

SA0

SPD

SDA

SA1

SA2

CKE1

CKE0

CAS#

RAS#

WE#

CKE: SDRAMs U11-U19

CKE: SDRAMs U1-U9

CAS#: SDRAMs

RAS#: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

BA0: SDRAMs

BA1: SDRAMs

A0-A11

BA0

BA1

SDRAMs

10K

SCL
WP

U10

U1
U2
U3
U4
U5

CK0

U6
U7
U8
U9

CK2

3.3pF

U11
U12
U13
U14

CK3

3.3pF

U15
U16
U17
U18
U19

CK1

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

Note:
1. All resistor values are 10

W unless otherwise specified.

2. Per industry standard, Micron modules use various component speed grades as

referenced in the module part numbering guide at

www.micron.com/

numberguide

SDRAMs = MT48LC64M8A2TG

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

General Description

The MT9LSDT6472A and MT18LSDT12872A mod-

ules are high-speed CMOS, dynamic random-access,
512MB and 1GB DIMMs organized in a x72 configura-
tion. These modules use internally configured quad-
bank SDRAMs with a synchronous interface (all signals
are registered on the positive edge of the clock signal
CK).

Read and write accesses to the SDRAM modules are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0A12
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An AUTO PRE-
CHARGE function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.

These modules use an internal pipelined architec-

ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.

The modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
syn-chronously burst data at a high data rate with
automatic column-address generation, the ability to
interleave between internal device banks in order to
hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access. For more information regarding SDRAM
operation, refer to the 512Mb SDRAM component data
sheet.

Serial Presence-Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I

C bus

using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses.

SDRAM Functional Description

In general, the 512Mb SDRAMs are quad-bank

DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edge of the clock signal, CK). The four banks of the x8
configured devices used for these modules are config-
ured as 8,192 bit-rows by 2,048 bit-columns, by 8
input/output bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed; BA0 and BA1 select the device bank, A0A12
select the device row. The address bits A0A9 regis-
tered coincident with the READ or WRITE command
are used to select the starting column location for the
burst access.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simul-

taneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP. Starting at some point

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 5, Mode Register Definition
Diagram. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the
device loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the mode register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 5, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1
A9, A11 when the burst length is set to two; A2A9, A11
when the burst length is set to four; and by A3A9, A11
when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select
the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached, as
shown in Table 7, Burst Definition Table, on page 9.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 9.

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 5: Mode Register Definition

Diagram

NOTE:

1. For full-page accesses: y = 2,048

2. For a burst length of two, A1

A9, A11 select the

block of two burst; A0 selects the starting column
within the block.

3. For a burst length of four, A2

A9, A11 select the

block of four burst; A0

A1 select the starting col-

umn within the block.

4. For a burst length of eight, A3

A9, A11 select the

block of eight burst; A0

A2 select the starting col-

umn within the block.

5. For a full-page burst, the full row is selected and

A9, A11 select the starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

7. For a burst length of one, A0

A9, A11 select the

unique column to be accessed, and Mode Register
bit M3 is ignored.

Table 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n= A0

A9,

A11

(location 0-y)

Cn, Cn+1, Cn+2

Cn+3, Cn+4...

...Cn-1,

Cn...

Not Supported

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is reg-
istered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
Diagram. Table 8, CAS Latency Table, indicates the
operating frequencies at which each CAS latency set-
ting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 6: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with
future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

Table 8:

CAS Latency Table

SPEED

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHz)

CAS LATENCY = 2

CAS LATENCY = 3

-13E

£ 133

£ 143

-133

£ 100

£ 133

-10E

£ 100

N/A

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Commands

The Truth Table, below, provides a quick reference

of available commands. This is followed by written
description of each command. For a more detailed

description of commands and operations, refer to the
512Mb SDRAM component data sheet.

NOTE:

1. A0A12 provide row address; BA0- BA1 determine which device bank is made active.

2. A0A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW

disables the auto-precharge feature; BA0BA1 determine which device bank is being read from or written to.

3. A10 LOW: BA0BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged

and BA0, BA1 are "Don't Care."

4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
6. A0A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

Table 9:

Truth Table SDRAM Commands and DQMB Operation

CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table

NAME (FUNCTION)

CS# RAS# CAS# WE# DQMB

ADDR

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/

Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE
burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)

4, 5

LOAD MODE REGISTER

Op-code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

, V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs NC or I/O Pins

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(Commercial) . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation, single bank . . . . . . . . . . . . . . . . 9W
Power Dissipation, dual bank . . . . . . . . . . . . . . . . 18W

Table 10: DC Electrical Characteristics and Operating Conditions - 512MB Module

Notes: 1, 5, 6; notes appear on page 17; V

= V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

£ VIN £ V

(All other pins not under test = 0V)

Command and
Address Inputs,
CKE

-45

µA

CK0, S0#

-25

µA

CK2, S2#

-20

µA

DQMB

-5

µA

OUTPUT LEAKAGE CURRENT: DQ pins are
disabled; 0V

£ V

OUT

£ V

-5

µA

OUTPUT LEVELS:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

Table 11: DC Electrical Characteristics and Operating Conditions - 1GB Module

Notes: 1, 5, 6; notes appear on page 17; V

= V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

£ VIN £ V

(All other pins not under test = 0V)

Command and
Address Inputs

-90

µA

CKE

-45

µA

CK0, CK1, S0#, S1#

-25

µA

CK2, CK3, S2#, S3#

-20

µA

DQMB

-10

µA

OUTPUT LEAKAGE CURRENT: DQ pins are
disabled; 0V

£ V

OUT

£ V

-10

µA

OUTPUT LEVELS:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

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Table 12: I

Specifications and Conditions 512MB Module

Notes: 1, 5, 6, 11, 13; notes appear on page 17; V

= V

Q = +3.3v ±0.3v; SDRAM component values only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or

WRITE;

RC =

RC (MIN)

1,935 1,800 1,800

3, 18, 19, 30

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All

device banks active after

RCD met; No accesses in progress

720

3, 12, 19, 30

OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active

1,620 1,620 1,620

3, 18, 19, 30

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

3,600 3,330 3,330

3, 12

CKE = HIGH; CS# = HIGH

RFC = 7.8125µs

18, 19, 30, 31

SELF REFRESH CURRENT: CKE

£ 0.2V

Table 13: I

Specifications and Conditions 1GB Module

Notes: 1, 5, 6, 11, 13; notes appear on page 17; V

, V

Q = +3.3V ±0.3V; SDRAM component values only

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or

WRITE;

RC =

RC (MIN)

1,953 1,818 1,818

3, 18, 19, 30

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH;

All device banks active after

RCD met; No accesses in progress

738

3, 12, 19, 30

OPERATING CURRENT: Burst Mode; Continuous burst; READ
or WRITE; All device banks active

1,638 1,638 1,638

3, 18, 19, 30

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

7,200 6,660 6,660

3, 12

CKE = HIGH; CS# = HIGH

RFC = 7.8125µs

180

18, 19, 30, 31

SELF REFRESH CURRENT: CKE

£ 0.2V

108

NOTE:

a - Value calculated as one module bank in this condition, and all other module banks in Power-Down Mode (I

DD2

b - Value calculated reflects all module banks in this condition.

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Table 14: Capacitance 512MB Module

Note 2; notes appear on page 17

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#

30.4

Input Capacitance: CK0

12.5

17.5

Input Capacitance: CK2

13.3

17.3

Input Capacitance: S0#

12.5

Input Capacitance: S2#

15.2

Input Capacitance: CKE

30.4

Input Capacitance: DQMB

2.5

3.8

Input/Output Capacitance: SCL, SA, SDA

Input/Output Capacitance: DQ

Table 15: Capacitance 1GB Module

Note 2; notes appear on page 17

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#

60.8

Input Capacitance: CK0, CK1

12.5

17.5

Input Capacitance: CK2, CK3

13.3

17.3

Input Capacitance: S0#, S1#

12.5

Input Capacitance: S2#, S3#

15.2

Input Capacitance: CKE

30.4

Input Capacitance: DQMB

7.6

Input/Output Capacitance: SCL, SA, SDA

Input/Output Capacitance: DQ

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Table 16: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 17
Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters

ACCHARACTERISTICS

-13E

-133

-10E

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access timefrom CLK (pos.edge)

CL=3

AC(3)

5.4

CL=2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL=3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE holdt ime

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (noload)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192rows)

REF

AUTOREFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b
command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK

7ns

7.5ns

7ns

Exit SELFREFRESH to ACTIVE command

XSR

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Table 17: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 17

PARAMETER

SYMBOL

-13E

-133

-10E

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE
command

CL = 3

ROH(3)

CL = 2

ROH(2)

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Notes

1. All voltages referenced to V

2. This parameter is sampled. V

, V

DDQ

= +3.3V;

= 25°C; pin under test biased at 1.4V; f = 1

MHz.

3. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be
repeated any time the

REF refresh requirement is

exceeded.

7. AC characteristics assume

T = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

3V, with timing referenced to 1.5V crossover
point. If the input transition time is longer than
1ns, then the timing is referenced at V

(MAX)

and V

(MIN) and no longer at the ISV crossover

point.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 10ns for -10E;

CK = 7.5ns for -133

and -13E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-

ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133;

and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.

AC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

28. Parameter guaranteed by design.
29. For -13E, CL = 2 and

CK = 7.5ns; for -133, CL = 3

and

CK = 7.5ns; for -10E, CL=2 and

CK = 10ns

30. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

31. Refer to device data sheet for timing waveforms.
32. The value of

RAS used in -13E speed grade mod-

ules is calculated from

RC -

RP.

33. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

50pF

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 7 and Figure 8).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in
Figure 9).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line
and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is gen-
erated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave
will terminate further data transmissions and await
the stop condition to return to standby power mode.

Figure 7: Data Validity

Figure 8: Definition of Start and Stop

Figure 9: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

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Table 18: EEPROM Device Select Code

The most significant bit (b7) is sent first

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 19: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

VIH or VIL

Start, Device Select, RW = 1

RandomAddressRead

VIH or VIL

Start, Device Select, RW= 0, Address

VIH or VIL

RESTART, Device Select, RW= 1

Sequential Read

VIH or VIL

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

£ 16

START, Device Select, RW = 0

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions

= +3.3V ±0.3V; all voltages referenced to V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

-10

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

-10

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other

inputs = GND or 3.3V ±10%

CCS

µA

POWER SUPPLY CURRENT:

Write

Read

3
1

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Figure 10: SPD EEPROM Timing Diagram

NOTE:

1. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

= +3.3V ±0.3V; all voltages referenced to V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

3.5

µs

Time the bus must be free before a new transition can
start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

ClockHIGHperiod

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

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Table 22: Seriea Presence-Detect Matrix

= +3.3V ±0.3V; "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT9LSDT6472A

MT18LSDT12872A

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

SDRAM

NUMBER OF ROW ADDRESSES

NUMBER OF COLUMN ADDRESSES

NUMBER OF MODULE BANKS

1 or 2

MODULE DATA WIDTH

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS

LVTTL

SDRAM CYCLE TIME,

(CAS LATENCY = 3)

7ns (-13E)

70
75
80

75
75
80

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 3)

5.4ns (-13E/-133)

6ns (-10E)

54
60

MODULE CONFIGURATION TYPE

ECC

REFRESH RATE/TYPE

7.8125µs/SELF

SDRAM WIDTH (PRIMARY SDRAM)

ERROR-CHECKING SDRAM DATA WIDTH

MINIMUM CLOCK DELAY FROM BACK-TO-BACK

RANDOM COLUMN ADDRESSES,

CCD

BURST LENGTHS SUPPORTED

1, 2, 4, 8, PAGE

NUMBER OF BANKS ON SDRAM DEVICE

CAS LATENCIES SUPPORTED

2, 3

CS LATENCY

WE LATENCY

SDRAM MODULE ATTRIBUTES

UNBUFFERED

SDRAM DEVICE ATTRIBUTES:GENERAL

SDRAM CYCLE TIME ,

(CAS LATENCY = 2) 10 (-133/-10E) A0

7.5ns (13E)

10ns (-133/-10E)

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 2)

5.4ns (-13E)

6ns (-133/-10E)

54
60

SDRAM CYCLE TIME,

CK (CAS LATENCY = 1)

SDRAM ACCESS FROM CLK,

AC (CAS LATENCY = 1)

MINIMUM ROW PRECHARGE TIME,

15ns (-13E)

20ns (-133/-10E)

0F
14

MINIMUM ROW ACTIVE TO ROW ACTIVE,

RRD

14ns (-13E)
15ns (-133)
20ns (-10E)

0E
0F
14

MINIMUM RAS# TO CAS# DELAY,

RCD

15ns (-13E)

20ns (-133/-10E)

0F
14

MINIMUM RAS# PULSE WIDTH,

RAS (See note 1)

45ns (-13E)

44ns (133)

50ns (-10E)

2C
32

MODULE BANK DENSITY

512MB

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

NOTE:

1. The value of

RAS used for -13E modules is calculated from

RC -

RP. Actual device specification value is 37ns.

COMMAND AND ADDRESS SETUP TIME,

AS,

CMS 1.5ns (-13E/-133)

2ns (-10E)

15
20

COMMAND AND ADDRESS HOLD TIME,

AH,

CMH 0.8ns (-13E/-133)

1ns (-10E)

08
10

DATA SIGNAL INPUT SETUP TIME,

1.5ns (-13E/-133)

2ns (-10E)

15
20

DATA SIGNAL INPUT HOLD TIME,

0.8ns (-13E/-133

1ns (-10E))

08
10

36-61

RESERVED

SPD REVISION

REV. 1.2

CHECKSUM FOR BYTES 0-62

(-13E)
(-133)
(-10E)

24
6C

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71

MANUFACTURER'S JEDEC ID CODE(CONT.)

MANUFACTURING LOCATION

1 - 11

01 - 0B

73-90

MODULE PARTNUMBER (ASCII)

Variable Data

PCB IDENTIFICATION CODE

1 - 9

01-09

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

Variable Data

WEEK OF MANUFACTURE IN BCD

Variable Data

95-98

MODULE SERIAL NUMBER

Variable Data

99-125

MANUFACTURER-SPECIFIC DATA (RSVD)

126

SYSTEM FREQUENCY

100 MHz (-13E/

-133/-10E)

127

SDRAM COMPONENT & CLOCK DETAIL

Table 22: Seriea Presence-Detect Matrix (Continued)

= +3.3V ±0.3V; "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT9LSDT6472A

MT18LSDT12872A

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 11: 512MB Module Dimensions

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

.125 (3.18)

MAX

.054 (1.37)
.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)
.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.380 (35.05)
1.370 (34.80)

5.256 (133.50)
5.244 (133.20)

U10

STANDARD PCB

.125 (3.18)

MAX

.054 (1.37)
.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)
.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.131 (28.73)
1.119 (28.42)

5.256 (133.50)
5.244 (133.20)

U10

LOW PROFILE PCB

MAX

MIN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

512MB / 1GB (x72)

168-PIN SDRAM DIMM

ADVANCE

64, 128 Meg x72 SDRAM DIMM

SD9_18C64_128X72AG_A.fm - Rev. A 11/02 EN

Figure 12: 1GB Module Dimensions

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

Advance: This data sheet contains initial descrip-

tions of products still under deveopment.

.157 (3.99)

MAX

.054 (1.37)
.046 (1.17)

PIN 1

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)
.118 (3.00)

PIN 84

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.131 (28.73)
1.119 (28.42)

5.256 (133.50)
5.244 (133.20)

U10

LOW PROFILE PCB

U11

U12

U13

U14

U15

U16

U17

U18

U19

PIN 85

PIN 168

BACK VIEW

.157 (3.99)

MAX

.054 (1.37)
.046 (1.17)

PIN 1

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

4.550 (115.57)

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.079 (2.00) R

(2X)

.039 (1.00)R (2X)

FRONT VIEW

.128 (3.25)
.118 (3.00)

PIN 84

(2X)

.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.380 (35.05)
1.370 (34.80)

5.256 (133.50)
5.244 (133.20)

U10

STANDARD PCB

U11

U12

U13

U14

U15

U16

U17

U18

U19

PIN 85

PIN 168

BACK VIEW

MAX

MIN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT18LSDT12872AG-13E_

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT18LSDT12872AG-13E_

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT18LSDT12872AG-13E_