Document Outline

• Features/Options
• Ball Assignment, 66-Ball FBGA (Top View)
• General Description
  • Table 1, VPP Voltage Ranges
• Device Marking
  • Table 2, Cross Reference for Abbreviated Device Marks
• Archetecture and Memory Organization
• Part Numbering Information
  • Figure 1, Part Number Chart
  • Table 3, Valid Part Number Combinations
• Block Diagram
• Flash Functional Block Diagram
• Ball Descriptions
• Ball Descriptions (continued)
• Truth Table - Flash
• Truth Table - SRAM
• Figure 2, Bottom Boot Block Device
• Figure 3, Top Boot Block Device
• Flash Memory Operating Modes
  • Command State Machine
  • Operations
  • Command Definition
  • Status Register
  • Table 4, Command State Machine Codes For Device Mode Selection
  • Command State Machine Operations
  • Table 5, Command Definitions
  • Table 6, Command Descriptions
  • Table 6, Command Descriptions (continued)
  • CLEAR STATUS REGISTER
  • READ Operations
    • Read Array
    • Read Chip Protection Identification Data
    • Read Query
    • Read Status Register
  • Programming Operations
  • ERASE Operations
  • Table 7, Bus Operations
  • Table 8, Status Register Bit Definition
  • Figure 4, Automated Word Programming Flowchart
  • Figure 5, PROGRAM SUSPEND/PROGRAM RESUME Flowchart
  • Figure 6, BLOCK ERASE Flowchart
  • Figure 7, ERASE SUSPEND/ERASE RESUME Flowchart
  • READ-While-WRITE/ERASE Concurrency
    • Figure 8, READ-While-WRITE Concurrency
    • Figure 9a, Top Boot Block Device
    • Figure 9b, Bottom Boot Block Device
  • Block Locking
    • Locked State
    • Unlocked State
    • Locked Down State
    • Table 9, Block Locking State Transition
    • Reading a Block's Lock Status
    • Table 10, Chip Protection Configuration Addressing
    • Locking Operations During ERASE SUSPEND
    • Status Register Error Checking
  • Chip Protection Register
    • Reading the Chip Protection Register
    • Figure 10, Protection Register Memory Map
  • Page Read Mode
  • Asynchronous READ Cycle
  • Standby Mode
  • Automatic Power Save (APS) Mode
  • VPP/VCC Program and Erase Voltages
  • Device Reset
  • Power-Up Sequence
  • Table 11, VPP Ranges (V)
• Flash Electrical Specifications
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • Figure 11, Output Load Circuit
  • Combined DC Characteristics
  • Combined DC Characteristics (continued)
  • Flash READ Cycle Timing Requirement VCC = 1.65V-1.95V
  • Flash READ Cycle Timing Requirement VCC = 1.80V-2.20V
  • Flash WRITE Cycle Timing Requirements
  • Flash ERASE and PROGRAM Cycle Timing Requirements
  • Flash Timing Diagrams
    • Two-Cycle PROGRAMMING/ERASE Operation
    • Single Asynchronous READ Operation
    • Asynchronous Page Mode READ Operation
    • RESET Operation
  • Table 12, CFI
  • Table 12, CFI (continued)
• SRAM Operating Modes
  • SRAM READ Array
  • SRAM WRITE Array
  • SRAM Functional Block Diagram
  • Timing Test Conditions
  • SRAM READ Cycle Timing
  • SRAM WRITE Cycle Timing
  • SRAM Timing Diagrams
    • READ Cycle 1 (S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH)
    • READ Cycle 2 (S_WE# = VIH)
    • WRITE Cycle (S_WE# Control)
    • WRITE Cycle 2 (S_CE1# Control)
• 66-Ball FBGA