PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

09005aef8076894f
1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

DOUBLE DATA RATE
(DDR) SDRAM

MT46V256M4 64 MEG X 4 X 4 BANKS
MT46V128M8 32 MEG X 8 X 4 BANKS
MT46V64M16 16 MEG X 16 X 4 BANKS

For the latest data sheet revisions, please refer to the
Micron Web site: www.micron.com/datasheets

Features

· V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture (x16 has two one per byte)

· Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

· Differential clock inputs (CK and CK#)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Data mask (DM) for masking write data (x16 has two

one per byte)

· Programmable burst lengths: 2, 4, or 8
· Auto Refresh and Self Refresh Modes
· Longer lead TSOP for improved reliability (OCPL)
· 2.5V I/O (SSTL_2 compatible)
· Concurrent auto precharge option is supported
·

RAS lockout supported (

RAP =

RCD)

NOTE:

1. Supports PC2100 modules with 2.5-3-3 timing

2. Supports PC1600 modules with 2-2-2 timing,

* Minimum clock rate @ CL= 2.5
** CL = CAS (Read) Latency

OPTIONS

MARKING

· Configuration

256 Meg x 4 (64 Meg x 4 x 4 banks)

256M4

128 Meg x 8 (32 Meg x 8 x 4 banks)

128M8

64 Meg x 16 (16 Meg x 16 x 4 banks)

64M16

· Plastic Package OCPL

66-pin TSOP(400 mil width, 0.65mm
pin pitch)

66-pin TSOP Lead-Free (400 mil width,
0.65mm pin pitch)

· Timing Cycle Time

7.5ns @ CL = 2.5 (DDR266B)

1, 2

-75

· Temperature Rating

Commercial Temperature
(0

°C to +70°C)

None

Key Timing Parameters

SPEED

GRADE

CLOCKRATE

DATA-OUT

WINDOW*

ACCESS

WINDOW

DQSDQ

SKEW

CL=2**

CL=2.5**

-75

100 MHz

133MHz

2.5ns

±0.75ns

+0.5ns

256 MEG X 4 128 MEG X 8 64 MEG X 16

Configuration

64 Meg x 4 x 4

banks

32 Meg x 8 x 4

banks

16 Meg x 16 x 4

banks

Refresh Count

Row Addressing

16K (A0A13)

Bank Addressing

4(BA0,BA1)

Column Addressing

4K(A0A9,

A11, A12)

2K(A0A9, A11)

1K(A0A9)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

DQ15

DQ14
DQ13

DQ12
DQ11

DQ10
DQ9

DQ8

NC
V

UDQS

DNU

REF

UDM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

x16

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5
DQ6

VssQ

DQ7

LDQS

A13

DNU

LDM

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

x16

DQ7

DQ6

DQ5

DQ4

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

NC
V

DQ3

NC
NC
V

DQ2

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

DQ0

DQ1

DQ2

DQ3

NC
NC

A13

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

DQ0

NC
NC

DQ1

NC
NC

A13

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

Figure 1: Pin Assignment (Top View)

66-pin TSOP

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN

1Gb DDR SDRAM Part Numbers

General Description

The 1Gb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing
1,073,741,824 bits. It is internally configured as a quad-
bank DRAM.

The 1Gb DDR SDRAM uses a double data rate archi-

tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 1Gb DDR SDRAM effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.

The 1Gb DDR SDRAM operates from a differential

clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.

As with standard SDR SDRAMs, the pipelined,

multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive option outputs are SSTL_2, Class II compatible.

NOTE: 1. The functionality and the timing specifica-

tions discussed in this data sheet are for the
DLL-enabled mode of operation.

2. Throughout the data sheet, the various fig-

ures and text refer to DQs as "DQ." The DQ
term is to be interpreted as any and all DQ
collectively, unless specifically stated other-
wise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.

3. Complete functionality is described

throughout the document and any page or
diagram may have been simplified to con-
vey a topic and may not be inclusive of all
requirements.

4. Any specific requirement takes precedence

over a general statement.

Configuration

MT46V

Package

Speed

Special

Options

Temperature

Configuration

256 Meg x4

128 Meg x8

64 Meg x16

256M4

128M8

64M16

Package

400 mil TSOP

400 mil TSOP Lead-Free

Speed Grade

tCK=7.5ns, CL = 2.5

-75

Operating Temp

Standard

Example Part Number: MT46V64M16TG-75

Special Options

Standard

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16TOC.fm - Rev. A 3/03 EN

TABLE OF CONTENTS

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1Gb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16LOF.fm - Rev. A 3/03 EN

List of Figures

Figure 1:

Pin Assignment (Top View) 66-pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2:

Functional Block Diagram 256 Meg x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 3:

Functional Block Diagram 128 Meg x8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 4:

Functional Block Diagram 64 Meg x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 5:

Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 6:

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 7:

Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 8:

Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9:

Example: Meeting

RCD (

RRD) MIN When 2 <

RCD (

RRD) MIN/

£3 . . . . . . . . . . . . . . . . . . . . . .18

Figure 10:

READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11:

READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 12:

Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13:

Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 14:

Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 15:

Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 16:

READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 17:

READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 18:

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 19:

WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20:

Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 21:

Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 22:

Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 23:

WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 24:

WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 25:

WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 26:

WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 27:

WRITE to Precharge Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 28:

WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 29:

PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 30:

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 31:

Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 32:

SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 33:

Derating Data Valid Window (

QH -

DQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 34:

Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 35:

Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 36:

Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 37:

Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 38:

x4, x8 Data Output Timing

DQSQ,

QH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 39:

x16 Data Output Timing

DQSQ,

QH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 40:

Data Output Timing

AC and

DQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 41:

Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 42:

Initialize And Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 43:

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 44:

Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 45:

Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 46:

Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 47:

Bank Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 48:

Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 49:

Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 50:

Write - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 51:

66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16LOT.fm - Rev. A 3/03 EN

List of Tables

Table 1:

Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 2:

Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 3:

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 4:

Truth Table Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 5:

Truth Table DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6:

Truth Table CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 7:

Truth Table Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 8:

Truth Table Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 9:

DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 10:

AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 11:

Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 12:

Capacitance (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 13:

Capacitance (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 14:

Specifications and Conditions (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 15:

Specifications and Conditions (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 16:

Test Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 17:

Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .52

Table 18:

Input Slew Rate Derating Values for Addresses and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 19:

Input Slew Rate Derating Values for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 20:

Normal Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 21:

Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Table 1:

Ball/Pin Descriptions

TSOP

NUMBERS

SYMBOL

TYPE

DESCRIPTION

45, 46

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK and
negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal
clock, input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),
or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the outputs. CKE
must be maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER- DOWN.
Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_2 input but will detect an LVCMOS

LOW level after V

is applied

and until CKE is first brought

HIGH, after which it becomes a SSTL_2 input

only.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.

23, 22,

RAS#, CAS#,

WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins are
input-only, the DM loading is designed to match that of DQ and DQS pins.
For the x16, LDM is DM for DQ0DQ7 and UDM is DM for DQ8DQ15. Pin
20 is a NC on x4 and x8.

20, 47

LDM, UDM

26, 27

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.

29, 30, 31, 32,
35, 36, 37, 38,

39, 40, 28

41, 42

A0, A1, A2, A3,
A4, A5, A6, A7,

A8, A9, A10,

A11, A12

A13

Input

Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands,
to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or
all banks (A10 HIGH). The address inputs also provide the op-code during a
MODE REGISTER SET command. BA0 and BA1 define which mode register
(mode register or extended mode register) is loaded during the LOAD
MODE REGISTER command.

2, 4, 5,

7, 8, 10,

11, 13, 54,
56, 57, 59,
60, 62, 63,

DQ0DQ2
DQ3DQ5
DQ6DQ8

DQ9DQ11

DQ12DQ14

DQ15

I/O

Data Input/Output: Data bus for x16
(DQ4DQ15 are NC for the x4)
(DQ8DQ16 are NC for the x8)

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

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1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Functional Description

The 1Gb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing
1,073,741,824 bits. The 1Gb DDR SDRAM is internally
configured as a quad-bank DRAM.

The 1Gb DDR SDRAM uses a double data rate archi-

tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 1Gb DDR SDRAM consists of a
single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O
pins.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A13 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.

Prior to normal operation, the DDR SDRAM must

be initialized. The following sections provide detailed
information covering device initialization, register def-
inition, command descriptions, and device operation.

Initialization

DDR SDRAMs must be powered up and initialized

in a predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Power must first be applied to V

and V

simultaneously, and then to VREF (and to the system
V

). V

must be applied after V

Q to avoid device

latch-up, which may cause permanent damage to the
device. VREF can be applied any time after V

Q but is

expected to be nominally coincident with V

. Except

for CKE, inputs are not recognized as valid until after
V

REF

is applied. CKE is an SSTL_2 input but will detect

an LVCMOS LOW level after V

is applied. After CKE

passes through V

, it will transition to a SSTL 2 signal

and remain as such until power is cycled. Maintaining
an LVCMOS LOW level on CKE during power-up is
required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until
driven in normal operation (by a read access). After all

power supply and reference voltages are stable, and
the clock is stable, the DDR SDRAM requires a 200µs
delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a DESE-

LECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP com-
mand, a PRECHARGE ALL command should be
applied. Next a LOAD MODE REGISTER command
should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by
another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL
and to program the operating parameters. Two-hun-
dred clock cycles are required between the DLL reset
and any READ command. A PRECHARGE ALL com-
mand should then be applied, placing the device in the
all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed (

RFC must be satisfied.) Addition-

ally, a LOAD MODE REGISTER command for the mode
register with the reset DLL bit deactivated (i.e., to pro-
gram operating parameters without resetting the DLL)
is required. Following these requirements, the DDR
SDRAM is ready for normal operation.

Register Definition

Mode Register

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 5 on page 12. The mode register is programmed
via the MODE REGISTER SET command (with BA0 = 0
and BA1 = 0) and will retain the stored information
until it is programmed again or the device loses power
(except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified opera-
tion.

Mode register bits A0-A2 specify the burst length, A3

specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A13 specify the
operating mode.

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Figure 5. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two,
by A2-Ai when the burst length is set to four and by A3-
Ai when the burst length is set to eight (where Ai is the
most significant column address bit for a given config-
uration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 2, Burst
Definition, on page 13.

Figure 5: Mode Register Definition

M3 = 0

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M15 and M14 (BA1 and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

A13

M13

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

NOTE:

1. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

2. For a burst length of two, A1-Ai select the two-

data-element block; A0 selects the first access
within the block.

3. For a burst length of four, A2-Ai select the four-

data-element block; A0-A1 select the first access
within the block.

4. For a burst length of eight, A3-Ai select the eight-

data-element block; A0-A2 select the first access
within the block.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 6.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 3
indicates the operating frequencies at which each CAS
latency setting can be used.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

Figure 6: CAS Latency

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7-A13
each set to zero, and bits A0-A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9-A13 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.

All other combinations of values for A7-A13 are

reserved for future use and/or test modes. Test modes
and reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.

Table 2:

Burst Definition

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN A

BURST

TYPE=

SEQUENTIAL

TYPE=

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Table 3:

CAS Latency (CL)

SPEED

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

CL = 2

CL = 2.5

-75

£ f £ 100

£ f £ 133

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDQSCK

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable, and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7. The extended mode register
is programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiat-
ing any subsequent operation. Violating either of these
requirements could result in unspecified operation.

Output Drive Strength

The normal drive strength for all outputs are speci-

fied to be SSTL_2, Class II. The x16 supports a pro-
grammable option for reduced drive. This option is
intended for the support of the lighter load and/or
point-to-point environments. The selection of the
reduced drive strength will alter the DQ pins and DQS
pins from SSTL_2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of
the SSTL_2, Class II drive strength.

DLL Enable/Disable

When the part is running without the DLL enabled,

device functionality may be altered. The DLL must be
enabled for normal operation. DLL enable is required

during power-up initialization and upon returning to
normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device
exits self refresh mode, the DLL is enabled automati-
cally.) Any time the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.

Figure 7: Extended Mode Register

Definition

NOTE:

1. E15 and E14 (BA1 and BA0) must be "0, 1" to

select the Extended Mode Register vs. the base
Mode Register.

2. The reduced drive strength option is not sup-

ported on the x4 and x8 versions, and is only
available on the x16 version.

3. The QFC# option is not supported.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

Reduced

E1,

Operating Mode

A10

A11

A12

BA1 BA0

E6 E5

E10

E11

E12

E13

A13

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

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Commands

Table 4 and Table 5 provide a quick reference of

available commands. This is followed by a verbal
description of each command. Two additional Truth

Tables, Table 7 on page 41, and Table 8 on page 43,
appear following the Operation section, provide cur-
rent state/next state information.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A13 provide the op-code to
be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A13 provide row address.
4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i=9 for x16, i=9, 11 for x8, and i=9,11, 12 for x4) A10 HIGH

enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0-BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; for within the Self Refresh mode all inputs and I/Os are "Don't Care" except

for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts

with auto precharge enabled and for write bursts.

9. DESELECT and NOP are functionally interchangeable.

NOTE:

1. Used to mask write data; provided coincident with the corresponding data.

Table 4:

Truth Table Commands

Note 1 applies to all commands

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 5:

Truth Table DM Operation

Note 1 applies to all commands

NAME (FUNCTION)

Write Enable

Valid

Write Inhibit

1Gb: x4, x8, x16

DDR SDRAM

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DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations
already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR SDRAM to perform a NOP
(CS# is LOW with RAS#, CAS#, and WE# equal HIGH).
This prevents unwanted commands from being regis-
tered during idle or wait states. Operations already in
progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0A13.

See mode register descriptions in the Register Defini-
tion section. The LOAD MODE REGISTER command
can only be issued when all banks are idle, and a sub-
sequent executable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0A13 selects the row.
This row remains active (or open) for accesses until a
precharge command is issued to that bank. A pre-
charge command must be issued before opening a dif-
ferent row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11,
12 for x4) selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst

write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0Ai (where i = 9 for x16; 9, 11 for x8; or 9,
11, 12 for x4) selects the starting column location. The
value on input A10 determines whether or not auto

precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coinci-
dent with the data. If a given DM signal is registered
LOW, the corresponding data will be written to mem-
ory; if the DM signal is registered HIGH, the corre-
sponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (

RP) after the precharge

command is issued. Except in the case of concurrent
auto precharge, where a READ or WRITE command to
a different bank is allowed as long as it does not inter-
rupt the data transfer in the current bank and does not
violate any other timing parameters. Input A10 deter-
mines whether one or all banks are to be precharged,
and in the case where only one bank is to be pre-
charged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as "Don't Care." Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command
will be treated as a NOP if there is no open row in that
bank (idle state), or if the previously open row is
already in the process of precharging.

Auto Precharge

Auto precharge is a feature which performs the

same individual-bank precharge function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable auto pre-
charge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is
addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst. Auto precharge is nonpersistent in that it
is either enabled or disabled for each individual Read
or Write command. This device supports concurrent
auto precharge if the command to the other bank does
not interrupt the data transfer to the current bank.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. This "ear-
liest valid stage" is determined as if an explicit
PRECHARGE command was issued at the earliest pos-
sible time, without violating

RAS (MIN), as described

1Gb: x4, x8, x16

DDR SDRAM

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for each burst type in the Operation section of this
data sheet. The user must not issue another command
to the same bank until the precharge time (

RP) is

completed.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate read bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet. The
open page which the READ burst was terminated from
remains open.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) refresh in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required. All banks must be idle before an
AUTO REFRESH command is issued.

The addressing is generated by the internal refresh

controller. This makes the address bits a "Don't Care"
during an AUTO REFRESH command. The 1Gb DDR
SDRAM requires AUTO REFRESH cycles at an average
interval of 7.8125µs (maximum).

To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command
and the next AUTO REFRESH command is 9 x 7.8125µs
(70.3µs). Note the JEDEC specifications only allows 8 x
7.8125µs, thus the Micron specification exceeds the

JEDEC requirement by one clock. This maximum
absolute interval is to allow future support for DLL
updates internal to the DDR SDRAM to be restricted to
AUTO REFRESH cycles, without allowing excessive
drift in

AC between updates.

Although not a JEDEC requirement, to provide for

future functionality features, CKE must be active
(High) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends

RFC later.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). The DLL is automatically disabled upon enter-
ing SELF REFRESH and is automatically enabled upon
exiting SELF REFRESH (A DLL reset and 200 clock
cycles must then occur before a READ command can
be issued). Input signals except CKE are "Don't Care"
during SELF REFRESH. VREF voltage is also required
for the SELF REFRESH full duration.

The procedure for exiting self refresh requires a

sequence of commands. First, CK and CK# must be
stable prior to CKE going back HIGH. Once CKE is
HIGH, the DDR SDRAM must have NOP commands
issued for

XSNR because time is required for the com-

pletion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL require-
ments is to apply NOPs for

XSNR time, then a DLL

Reset and NOPs for 200 additional clock cycles before
applying any other command.

1Gb: x4, x8, x16

DDR SDRAM

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Operations

Bank/Row Activation

Before any READ or WRITE commands can be

issued to a bank within the DDR SDRAM, a row in that
bank must be "opened." This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 8.

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,
subject to the

RCD specification.

RCD (MIN) should

be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a

RCD

specification of 20ns with a 133 MHz clock (7.5ns
period) results in 2.7 clocks rounded to 3. This is
reflected in Figure 9, which covers any case where 2 <

RCD (MIN)/

£ 3. (Figure 9 also shows the same

case for

RCD; the same procedure is used to convert

other specification limits from time units to clock
cycles).

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by

RRD.

Figure 8: Activating a Specific Row in a

Specific Bank

Figure 9: Example: Meeting

RCD (

RRD) MIN When 2 <

RCD (

RRD) MIN/

£3

CS#

WE#

CAS#

RAS#

CKE

A0-A13

RA = Row Address
BA = Bank Address

HIGH

BA0, BA1

CK#

COMMAND

BA0, BA1

ACT

NOP

RRD

tRCD

CK#

Bank x

Bank y

A0-A13

Row

NOP

RD/WR

NOP

Bank y

Col

NOP

DON'T CARE

NOP

1Gb: x4, x8, x16

DDR SDRAM

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READs

READ bursts are initiated with a READ command, as

shown in Figure 10 on page 20.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst.

NOTE:

For the READ commands used in the follow-

ing illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid nomi-
nally at the next positive or negative clock edge (i.e., at
the next crossing of CK and CK#). Figure 11 on page 21
shows general timing for each possible CAS latency
setting. DQS is driven by the DDR SDRAM along with
output data. The initial LOW state on DQS is known as
the read preamble; the LOW state coincident with the
last data-out element is known as the read postamble.

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-
Z. A detailed explanation of

DQSQ (valid data-out

skew),

QH (data-out window hold), the valid data win-

dow are depicted in Figure 38 on page 60 and Figure 39
on page 61. A detailed explanation of

DQSCK (DQS

transition skew to CK) and

AC (data-out transition

skew to CK) is depicted in Figure 40 on page 62.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data
can be maintained. The first data element from the
new burst follows either the last element of a com-
pleted burst or the last desired data element of a longer
burst which is being truncated. The new READ com-
mand should be issued x cycles after the first READ

command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 12 on page 22. A
READ command can be initiated on any clock cycle
following a previous READ command. Nonconsecutive
read data is shown for illustration in Figure 13 on
page 23. Full-speed random read accesses within a
page (or pages) can be performed as shown in
Figure 14 on page 24.

Data from any READ burst may be truncated with a

BURST TERMINATE command, as shown in Figure 15
on page 25. The BURST TERMINATE latency is equal
to the read (CAS) latency, i.e., the BURST TERMINATE
command should be issued x cycles after the READ
command, where x equals the number of desired data
element pairs (pairs are required by the 2n-prefetch
architecture).

Data from any READ burst must be completed or

truncated before a subsequent WRITE command can
be issued. If truncation is necessary, the BURST TER-
MINATE command must be used, as shown in
Figure 16 on page 26. The

DQSS (NOM) case is shown;

the

DQSS (MAX) case has a longer bus idle time.

(

DQSS [MIN] and

DQSS [MAX] are defined in the sec-

tion on WRITEs.)

A READ burst may be followed by, or truncated with,

a PRECHARGE command to the same bank provided
that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles after the
READ command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture). This is shown in Figure 17
on page 27. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until both

RAS and

RP has been met. Note that

part of the row precharge time is hidden during the
access of the last data elements.

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WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 18.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst and after the

WR time.

NOTE:

For the WRITE commands used in the follow-

ing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write pream-
ble; the LOW state on DQS following the last data-in
element is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (

DQSS) is

specified with a relatively wide range (from 75 per-
cent to 125 percent of one clock cycle). All of the
WRITE diagrams show the nominal case, and where
the two extreme cases (i.e.,

DQSS [MIN] an

DQSS

[MAX]) might not be

intuitive, they have also been

included. Figure 19 on page 29 shows the nominal
case and the extremes of

DQSS for a burst of 4.

Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain
High-Z and any additional input data will be
ignored.

Data for any WRITE burst may be concatenated

with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from
the new burst is applied after either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new WRITE
command should be issued x cycles after the first
WRITE command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture).

Figure 20 on page 30 shows concatenated bursts of

4. An example of nonconsecutive WRITEs is shown in
Figure 21 on page 31. Full-speed random write
accesses within a page or pages can be performed as
shown in Figure 22 on page 32.

Figure 18: WRITE Command

Data for any WRITE burst may be followed by a sub-

sequent READ command. To follow a WRITE without
truncating the WRITE burst,

WTR should be met as

shown in Figure 23 on page 33.

Data for any WRITE burst may be truncated by a

subsequent READ command, as shown in Figure 24 on
page 34.

Note that only the data-in pairs that are registered

prior to the

WTR period are written to the internal

array, and any subsequent data-in should be masked
with DM as shown in Figure 25 on page 35.

Data for any WRITE burst may be followed by a sub-

sequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst,

WR should be

met as shown in Figure 26 on page 36.

Data for any WRITE burst may be truncated by a

subsequent PRECHARGE command, as shown in
Figure 27 on page 37 and Figure 28 on page 38. Note
that only the data-in pairs that are registered prior to
the

WR period are written to the internal array, and

any subsequent data-in should be masked with DM as
shown in Figures 27 and 28. After the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until

RP is met.

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

EN AP

DIS AP

CK#

CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge

DON'T CARE

x4: A0A9, A11, A12

x8: A0A9, A11

x16: A0A9

x4: A13
x8: A13

x16: A11, A12, A13

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DDR SDRAM

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PRECHARGE

The PRECHARGE command as shown in Figure 29,

is used to deactivate the open row in a particular bank
or the open row in all banks. The bank(s) will be avail-
able for a subsequent row access some specified time
(

RP) after the PRECHARGE command is issued. Input

A10 determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as "Don't Care." Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.

Figure 29: PRECHARGE Command

Power-down (CKE Not Active)

Unlike SDR SDRAMs, DDR SDRAMs require CKE to

be active at all times an access is in progress, from the
issuing of a READ or WRITE command until comple-
tion of the access. Thus a clock suspend is not sup-
ported. For READs, an access completion is defined
when the Read Postamble is satisfied; for WRITEs, an
access completion is defined when the Write Recovery
time (

WR) is satisfied.

Power-down as shown in Figure 30 on page 40, is

entered when CKE is registered LOW and all Table 6
(page 40)criteria are met. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK#, and
CKE. For maximum power savings, the DLL is frozen
during precharge power-down mode. Exiting power-
down requires the device to be at the same voltage and
frequency as when it entered power-down. However,
power-down duration is limited by the refresh require-
ments of the device (

REFC).

While in power-down, CKE LOW and a stable clock

signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are "Don't Care."
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.

CS#

WE#

CAS#

RAS#

CKE

A10

BA0,1

HIGH

ALL BANKS

ONE BANK

A0A9, A11, A12, A13

CK#

BA = Bank Address (if A10 is LOW;
otherwise "Don't Care")

DON'T CARE

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Figure 30: Power-Down

NOTE:

1. CKE

is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND

is the command registered at clock edge n, and ACTION

is a result of COMMAND

4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop low during a column access. For a READ, this means CKE must stay high until after the Read Postamble time;

for a WRITE, CKE must stay high until the WRITE Recovery Time (

WR) has been met.

6. Upon exit of the Self Refresh mode the DLL is automatically enabled, but a DLL Reset must still occur. A minimum of 200 clock

cycles is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be issued on any
clock edges occurring during the

XSNR period.

No READ/WRITE
access in progress

Exit power-down mode

Enter power-down mode

CKE

CK#

COMMAND

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOP

VALID

Ta0

Ta1

Ta2

VALID

DON'T CARE

Table 6:

Truth Table CKE

Notes: 1-6

CKE

n-1

CKE

CURRENT STATE

COMMAND

ACTION

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Power-Down

DESELECT or NOP

Exit Power-Down

Self Refresh

DESELECT or NOP

Exit Self Refresh

All Banks Idle

DESELECT or NOP

Precharge Power-Down Entry

Bank(s) Active

DESELECT or NOP

Active Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

See Table 7 on page 41

1Gb: x4, x8, x16

DDR SDRAM

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NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Table 6 on page 40) and after

XSNR has been met (if

the previous state was self refresh).

2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those

allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle:The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no regis-

ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or

allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands
to the other bank are determined by its current state and Table 7, Truth Table Current State Bank n - Command to Bank n, on
page 41 and according to Table 8, Truth Table Current State Bank n - Command to Bank m, on page 43.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is met, the

bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met. Once

RCD is met,

the bank will be in the "row active" state.
Read w/Auto-
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

Table 7:

Truth Table Current State Bank n - Command to Bank n

(Notes: 1-6; notes appear below and on next page)

CURRENT

STATE

CS#

RAS# CAS#

WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Idle

ACTIVE (select and activate row)

AUTO REFRESH

LOAD MODE REGISTER

Row
Active

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

Read
(Auto-
Precharge
Disabled)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

10, 12

PRECHARGE (truncate READ burst, start PRECHARGE)

BURST TERMINATE

Write
(Auto-
Precharge
Disabled)

READ (select column and start READ burst)

10, 11

WRITE (select column and start new WRITE burst)

PRECHARGE (truncate WRITE burst, start PRECHARGE)

8, 11

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Write w/Auto-
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RFC is met. Once

RFC is

met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode

MRD has been met.

Once

MRD is met, the DDR SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met. Once

RP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10.READs or WRITEs listed in the Command/Action column include Reads or Writes with auto precharge enabled and READs or

WRITEs with auto precharge disabled.

11.Requires appropriate DM masking.
12.A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to

end the READ burst prior to asserting a WRITE command.

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSNR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands

shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable).
Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no regis-

ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated
Read with Auto Precharge Enabled: See following text 3a
Write with Auto Precharge Enabled: See following text 3a

a. The read with auto precharge enabled or write with auto precharge enabled states can each

be broken into two parts: the access period and the precharge period. For read with auto pre-
charge, the precharge period is defined as if the same burst was executed with auto precharge
disabled and then followed with the earliest possible PRECHARGE command that still accesses
all of the data in the burst. For write with auto precharge, the precharge period begins when

WR ends, with

WR measured as if auto precharge was disabled. The access period starts with

registration of the command and ends where the precharge period (or

RP) begins.

Table 8:

Truth Table Current State Bank n - Command to Bank m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE

CS#

RAS#

CAS#

WE#

COMMAND/ACTION

NOTES

Any

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row
Activating,
Active, or
Precharging

ACTIVE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Read
(Auto-
Precharge
Disabled)

ACTIVE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

7, 9

PRECHARGE

Write
(Auto-
Precharge
Disabled)

ACTIVE (select and activate row)

READ (select column and start READ burst)

7, 8

WRITE (select column and start new WRITE burst)

PRECHARGE

Read
(With Auto-
Precharge)

ACTIVE (select and activate row)

READ (select column and start new READ burst)

7, 3a

WRITE (select column and start WRITE burst)

7, 9, 3a

PRECHARGE

Write
(With Auto-
Precharge)

ACTIVE (select and activate row)

READ (select column and start READ burst)

7, 3a

WRITE (select column and start new WRITE burst)

7, 3a

PRECHARGE

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

This device supports concurrent auto precharge such that when a read with auto pre-
charge is enabled or a write with auto precharge is enabled any command to other
banks is allowed, as long as that command does not interrupt the read or write data
transfer already in process. In either case, all other related limitations apply (e.g., con-
tention between read data and write data must be avoided).

b. The minimum delay from a read or write command with auto precharge enabled, to a com-

mand to a different bank is summarized below.

NOTE:

= CAS Latency (CL) rounded up to the next integer

BL = Bust Length

4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or

WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to

end the READ burst prior to asserting a WRITE command.

FROM COMMAND

TO COMMAND

MINIMUM DELAY

(WITH CONCURRENT AUTO PRECHARGE)

WRITE w/AP

READ or READ w/AP

[1 + (BL/2)] *

CK +

WTR

WRITE or WRITE w/AP

(BL/2) *

PRECHARGE

ACTIVE

READ w/AP

READ or READ w/AP

(BL/2) *

WRITE or WRITE w/AP

[CL

(BL/2)] *

PRECHARGE

ACTIVE

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Supply Voltage

Relative to Vss ............................................... -1V to +3.6V
V

Q Supply Voltage

Relative to V

..............................................-1V to +3.6V

REF

and Inputs Voltage

Relative to V

..............................................-1V to +3.6V

I/O Pins Voltage
Relative to V

................................ -0.5V to V

Q +0.5V

Operating Temperature, T

(ambient, Commercial)............................... 0°C to +70°C
Storage Temperature (plastic) ...............-55°C to +150°C
Power Dissipation........................................................ 1W
Short Circuit Output Current .................................50mA

Table 9:

DC Electrical Characteristics and Operating Conditions

0°C

£ T

£ +70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V

Notes: 15, 16, notes appear on page 54-57

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

36, 41,

I/O Supply Voltage

2.3

2.7

36, 41,

I/O Reference Voltage

REF

0.49 x V

0.51 x V

6, 44

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 44

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

, V

REF

PIN 0V

£ VIN £ 1.35V

(All other pins not under test = 0V)

-2

µA

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ VOUT £

)

-5

µA

OUTPUT LEVELS: Full drive option - x4, x8, x16

High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

minimum V

)

-16.8

37, 39

Low Current (V

OUT

= 0.373V, maximum V

REF

maximum V

)

16.8

OUTPUT LEVELS: Reduced drive option - x16 only

High Current (V

OUT

= V

Q - 0.763V, minimum V

REF

minimum V

)

OHR

-9

38, 39

Low Current (V

OUT

= 0.763V, maximum V

REF

maximum V

)

OLR

Table 10: AC Input Operating Conditions

0°C

£ T

£ +70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V

Notes: 15, 14, 16, notes appear on page 54-57

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

14, 28, 40

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

14, 28, 40

I/O Reference Voltage

REF

(

)

0.49 x V

0.51 x V

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Table 14: I

Specifications and Conditions (x4, x8)

0°C

£ T

£ +70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V

Notes: 15, 10, 12, 14; notes appear on page 54-57; See also Table 16, I

Test Cycle Times, on page 51

MAX

PARAMETER/CONDITION

SYMBOL

-75

UNITS

NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cycle; Address and control inputs
changing once every two clock cycles

145

22, 48

OPERATING CURRENT: One bank; Active-Read-Precharge;

Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address

and control inputs

changing once per clock cycle

180

22, 48

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

Power-down mode;

CK =

CK (MIN);

CKE = (LOW)

23, 32, 50

IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;

CK =

CK (MIN);

CKE = HIGH; Address and other control inputs

changing once per clock

cycle. V

= V

REF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;

CK =

CK (MIN); CKE = LOW

23, 32, 50

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;

One bank active

;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2;

Reads; Continuous burst;

One bank active; Address and control inputs changing once per

clock cycle;

CK =

CK (MIN);

OUT

= 0mA

200

22, 48

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank

active; Address and control inputs changing once per

clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

210

AUTO REFRESH BURST CURRENT:

RC =

RFC(MIN)

330

RFC = 7.8us,

27, 50

SELF REFRESH CURRENT: CKE

£ 0.2V

Standard

OPERATING CURRENT: Four bank interleaving READs

(Burst = 4) with auto precharge,

RC = minimum

RC allowed;

CK =

CK (MIN); Address and control inputs change only during

Active READ, or WRITE commands

485

22, 49

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Table 15: I

Specifications and Conditions (x16)

0°C

£ T

£ +70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V

Notes: 15, 10, 12, 14; notes appear on page 54-57; See also Table 16, I

Test Cycle Times, on page 51

MAX

PARAMETER/CONDITION

SYMBOL

-75

UNITS

NOTES

OPERATING CURRENT: One bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cycle; Address and control inputs
changing once every two clock cycles

145

22, 48

OPERATING CURRENT: One bank; Active-Read-Precharge;

Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address

and control inputs

changing once per clock cycle

195

22, 48

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

Power-down mode;

CK =

CK (MIN);

CKE = (LOW)

23, 32, 50

IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;

CK =

CK (MIN);

CKE = HIGH; Address and other control inputs

changing once per clock

cycle. V

= V

REF

for DQ, DQS, and DM

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode;

CK =

CK (MIN); CKE = LOW

23, 32, 50

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;

One bank active

;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and

DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2;

Reads; Continuous burst;

One bank active; Address and control inputs changing once per

clock cycle;

CK =

CK (MIN);

OUT

= 0mA

245

22, 48

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank

active; Address and control inputs changing once per

clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing

twice per clock cycle

250

AUTO REFRESH BURST CURRENT:

RC =

RFC(MIN)

330

RFC = 7.8us,

27, 50

SELF REFRESH CURRENT: CKE

£ 0.2V

Standard

OPERATING CURRENT: Four bank interleaving READs

(Burst = 4) with auto precharge,

RC = minimum

RC allowed;

CK =

CK (MIN); Address and control inputs change only during

Active READ, or WRITE commands

495

22, 49

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Table 17: Electrical Characteristics and Recommended AC Operating Conditions

0°C

£ T

£ +70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V

Notes: 15, 1417, 33, notes appear on page 54-57

AC CHARACTERISTICS

-75

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.75

+0.75

CK high-level width

0.45

0.55

CK low-level width

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

45, 52

CL=2

CK (2)

45, 52

DQ and DM input hold time relative to DQS

0.5

26, 31

DQ and DM input setup time relative to DQS

0.5

26, 31

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.5

25, 26

Write command to first DQS latching transition

DQSS

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.75

18,42

Data-out low-impedance window from CK/CK#

-0.75

18,43

Address and control input hold time (slew rate

³ 1V/ns)

.90

Address and control input setup time (slew rate

³ 1V/ns)

.90

Address and control input hold time (slew rate @ 0.5V/ns)

Address and control input setup time (slew rate @ 0.5V/ns)

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

QHS

25, 26

Data Hold Skew Factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

120

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

DQS read postamble

RPST

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

20, 21

DQS write postamble

WPST

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (DVW)

N/A

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

127.5

Exit SELF REFRESH to READ command

XSRD

200

1Gb: x4, x8, x16

DDR SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs (except for I

measurements) measured

with equivalent load:

4. AC timing and IDD tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(AC)

and V

(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. V

is the magnitude of the difference between

the input level on CK and the input level on CK#.

9. The value of V

and V

are expected to equal

Q/2 of the transmitting device and must track

variations in the DC level of the same.

10. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle times at CL = 2.5 with the outputs
open.

11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

13. This parameter is sampled. V

=+2.5V±0.2V,

Q=+2.5V±0.2V, V

REF

, f=100MHz, T

=25°C

OUT

(DC)=V

Q/2, V

OUT

(peak to peak)=0.2V.

DM input is grouped with I/O pins, reflecting the
fact that they are matched in loading.

14. For slew rates less than 1V/ns and and greater

than or equal to 0.5V/ns. If the slew rate is less
than 0.5V/ns, timing must be derated:

IS has an

additional 50ps per each 100mV/ns reduction in
slew rate from the 500mV/ns.

IH has 0ps added,

that is, it remains constant. If the slew rate
exceeds 4.5V/ns, functionality is uncertain.

15. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

16. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE 0.3 x V

Q is recognized as LOW.

17. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is
V

18.

HZ and

LZ transitions occur in the same access

time windows as data valid transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

19. The intent of the Don't Care state after completion

of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above V

DC(MIN) then it must

not transition low (below V

DC) prior to

DQSH(MIN).

20. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

22.

MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the mini-

Output
(V

OUT

)

Reference

Point

30pF

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

mum absolute value for the respective parame-
ter.

RAS (MAX) for I

measurements is the

largest multiple of

CK that meets the maxi-

mum absolute value for

RAS.

23. The refresh period is 64ms. This equates to an

average refresh rate of 7.8125µs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3µs; burst refreshing or post-
ing by the DRAM controller greater than eight
refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/group

will not differ by more than this maximum
amount for any given device.

25.

The data valid window is derived by achieving
other specifications -

HP (

CK/2),

DQSQ, and

QH (

QH =

HP -

QHS). The data valid window

derates in direct proportion to the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55, because functionality
is uncertain when operating beyond a 45/55
ratio. The data valid window derating curves are
provided in Figure 33 for duty cycles ranging
between 50/50 and 45/55.

26. Referenced to each output group: x4 = DQS with

DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.

27. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

28. To maintain a valid level, the transitioning edge of

the input must:
a.

Sustain a constant slew rate from the current
AC level through to the target AC level,
V

(AC)

or V

(AC).

b. Reach at least the target AC level.
c.

After the AC target level is reached, continue
to maintain at least the target DC level,
V

(DC) or V

(DC).

29. The Input capacitance per pin group will not dif-

fer by more than this maximum amount for any
given device.

30. CK and CK# input slew rate must be

³ 1V/ns

(

³ 2V/ns if measured differentially).

31. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. For

If slew rate exceeds 4V/ns, functionality is uncer-
tain.

32. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Cl o ck Du ty C y c le

---- -75 @

CK = 10ns

---- -75 @

CK = 7.5ns

Figure 33: Derating Data Valid Window (

QH -

DQSQ)

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

33. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

34.

HP (MIN) is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK# inputs, collectively during bank active.

35. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS (MIN) can be satis-

fied prior to the internal precharge command
being issued.

36. Any positive glitch must be less than 1/3 of the

clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either
-300mV or 2.2V, whichever is more positive.

37. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 34

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 34.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 35.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 35.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature. f ) The
full variation in the ratio of the nominal pull-
up to pull-down current should be unity ±10
percent, for device drain-to-source voltages
from 0.1V to 1.0V.

Figure 34: Full Drive Pull-Down

Characteristics

Figure 35: Full Drive Pull-Up

Characteristics

38. Reduced Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 36.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 36.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 37.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of
Figure 37.

100

120

140

160

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

OUT

)

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V )

OUT

)

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

Figure 36: Reduced Drive Pull-Down

Characteristics

Figure 37: Reduced Drive Pull-Up

Characteristics

39.

The voltage levels used are derived from a mini-
mum

level and the referenced test load. In

practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.

40.

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not

be greater than

1/3

of the cycle rate. V

under-

shoot: V

(MIN) = -1.5V for a pulse width

£ 3ns

and the pulse width can not be greater than

1/3

of the cycle rate.

41. V

and V

Q must track each other.

42. This maximum value is derived from the refer-

enced test load. In practice, the values obtained in
a typical terminated design may reflect up to
310ps less for

HZ (MAX) and the last DVW.

(MAX) will prevail over

DQSCK (MAX) +

RPST

(MAX) condition.

LZ (MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

43. For slew rates of greater than 1V/ns the (LZ) tran-

sition will start about 310ps earlier.

44. During initialization, V

Q, V

, and V

REF

must be

equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if
V

Q are 0V, provided a minimum of 42

W of

series resistance is used between the V

supply

and the input pin.

45. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

46. Not used.
47. Reserved for future use.
48. Random addressing changing 50 percent of data

changing at every transfer.

49. Random addressing changing 100 percent of data

changing at every transfer.

50. CKE must be active (HIGH) during the entire time

a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

RFC has been satisfied.

51. I

2N specifies the DQ, DQS and DM to be driven

to a valid high or low logic level. I

2Q is similar

to I

2F except I

2Q specifies the address and

control inputs to remain stable. Although I

2F,

2N, and I

2Q are similar, I

2F is "worst

case."

52. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset fol-
lowed by 200 clock cycles before any Read com-
mand.

0.0

0.5

1.0

1.5

OUT

(V)

)

-80

-70

-60

-50

-40

-30

-20

-10

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

)

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

NOTE:

The above characteristics are specified under best, worst, and nominal process variation/conditions.

Table 20: Normal Output Drive Characteristics

VOLTAGE

(V)

PULL-DOWN CURRENT (mA)

PULL-UP CURRENT (mA)

NOMINAL

LOW

NOMINAL

HIGH

MINIMUM

MAXIMUM

NOMINAL

LOW

NOMINAL

HIGH

MINIMUM

MAXIMUM

0.1

6.0

6.8

4.6

9.6

-6.1

-7.6

-4.6

-10.0

0.2

12.2

13.5

9.2

18.2

-12.2

-14.5

-9.2

-20.0

0.3

18.1

20.1

13.8

26.0

-18.1

-21.2

-13.8

-29.8

0.4

24.1

26.6

18.4

33.9

-24.0

-27.7

-18.4

-38.8

0.5

29.8

33.0

23.0

41.8

-29.8

-34.1

-23.0

-46.8

0.6

34.6

39.1

27.7

49.4

-34.3

-40.5

-27.7

-54.4

0.7

39.4

44.2

32.2

56.8

-38.1

-46.9

-32.2

-61.8

0.8

43.7

49.8

36.8

63.2

-41.1

-53.1

-36.0

-69.5

0.9

47.5

55.2

39.6

69.9

-43.8

-59.4

-38.2

-77.3

1.0

51.3

60.3

42.6

76.3

-46.0

-65.5

-38.7

-85.2

1.1

54.1

65.2

44.8

82.5

-47.8

-71.6

-39.0

-93.0

1.2

56.2

69.9

46.2

88.3

-49.2

-77.6

-39.2

-100.6

1.3

57.9

74.2

47.1

93.8

-50.0

-83.6

-39.4

-108.1

1.4

59.3

78.4

47.4

99.1

-50.5

-89.7

-39.6

-115.5

1.5

60.1

82.3

47.7

103.8

-50.7

-95.5

-39.9

-123.0

1.6

60.5

85.9

48.0

108.4

-51.0

-101.3

-40.1

-130.4

1.7

61.0

89.1

48.4

112.1

-51.1

-107.1

-40.2

-136.7

1.8

61.5

92.2

48.9

115.9

-51.3

-112.4

-40.3

-144.2

1.9

62.0

95.3

49.1

119.6

-51.5

-118.7

-40.4

-150.5

2.0

62.5

97.2

49.4

123.3

-51.6

-124.0

-40.5

-156.9

2.1

62.8

99.1

49.6

126.5

-51.8

-129.3

-40.6

-163.2

2.2

63.3

100.9

49.8

129.5

-52.0

-134.6

-40.7

-169.6

2.3

63.8

101.9

49.9

132.4

-52.2

-139.9

-40.8

-176.0

2.4

64.1

102.8

50.0

135.0

-52.3

-145.2

-40.9

-181.3

2.5

64.6

103.8

50.2

137.3

-52.5

-150.5

-41.0

-187.6

2.6

64.8

104.6

50.4

139.2

-52.7

-155.3

-41.1

-192.9

2.7

65.0

105.4

50.5

140.8

-52.8

-160.1

-41.2

-198.2

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

NOTE:

The above characteristics are specified under best, worst, and nominal process variation/conditions.

Table 21: Reduced Output Drive Characteristics

VOLTAGE

(V)

PULL-DOWN CURRENT (mA)

PULL-UP CURRENT (mA)

NOMINAL

LOW

NOMINAL

HIGH

MINIMUM

MAXIMUM

NOMINAL

LOW

NOMINAL

HIGH

MINIMUM

MAXIMUM

0.1

3.4

3.8

2.6

5.0

-3.5

-4.3

-2.6

-5.0

0.2

6.9

7.6

5.2

9.9

-6.9

-7.8

-5.2

-9.9

0.3

10.3

11.4

7.8

14.6

-10.3

-12.0

-7.8

-14.6

0.4

13.6

15.1

10.4

19.2

-13.6

-15.7

-10.4

-19.2

0.5

16.9

18.7

13.0

23.6

-16.9

-19.3

-13.0

-23.6

0.6

19.9

22.1

15.7

28.0

-19.4

-22.9

-15.7

-28.0

0.7

22.3

25.0

18.2

32.2

-21.5

-26.5

-18.2

-32.2

0.8

24.7

28.2

20.8

35.8

-23.3

-30.1

-20.4

-35.8

0.9

26.9

31.3

22.4

39.5

-24.8

-33.6

-21.6

-39.5

1.0

29.0

34.1

24.1

43.2

-26.0

-37.1

-21.9

-43.2

1.1

30.6

36.9

25.4

46.7

-27.1

-40.3

-22.1

-46.7

1.2

31.8

39.5

26.2

50.0

-27.8

-43.1

-22.2

-50.0

1.3

32.8

42.0

26.6

53.1

-28.3

-45.8

-22.3

-53.1

1.4

33.5

44.4

26.8

56.1

-28.6

-48.4

-22.4

-56.1

1.5

34.0

46.6

27.0

58.7

-28.7

-50.7

-22.6

-58.7

1.6

34.3

48.6

27.2

61.4

-28.9

-52.9

-22.7

-61.4

1.7

34.5

50.5

27.4

63.5

-28.9

-55.0

-22.7

-63.5

1.8

34.8

52.2

27.7

65.6

-29.0

-56.8

-22.8

-65.6

1.9

35.1

53.9

27.8

67.7

-29.2

-58.7

-22.9

-67.7

2.0

35.4

55.0

28.0

69.8

-29.2

-60.0

-22.9

-69.8

2.1

35.6

56.1

28.1

71.6

-29.3

-61.2

-23.0

-71.6

2.2

35.8

57.1

28.2

73.3

-29.5

-62.4

-23.0

-73.3

2.3

36.1

57.7

28.3

74.9

-29.5

-63.1

-23.1

-74.9

2.4

36.3

58.2

28.3

76.4

-29.6

-63.8

-23.2

-76.4

2.5

36.5

58.7

28.4

77.7

-29.7

-64.4

-23.2

-77.7

2.6

36.7

59.2

28.5

78.8

-29.8

-65.1

-23.3

-78.8

2.7

36.8

59.6

28.6

79.7

-29.9

-65.8

-23.3

-79.7

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 39: x16 Data Output Timing

DQSQ,

QH, and Data Valid Window

NOTE:

1. DQ transitioning after DQS transition define

DQSQ window. LDQS defines the lower byte and UDQS defines the

upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3.

DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last

valid DQ transition.

QH is derived from

HP:

QH =

HP -

QHS.

HP is the lesser of

CL or

CH clock transition collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is

QH minus

DQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

DQ (Last data valid)

LDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ0 - DQ7 and LDQS, collectively

T2n

T3n

CK#

T2n

T3n

tQH

tDQSQ

Data Valid

window

Data Valid

window

DQ (Last data valid)

UDQS

DQ (Last data valid)

DQ (First data no longer valid)

DQ8 - DQ15 and UDQS, collectively

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Data Valid

window

Upper Byte

Lower Byte

Data Valid

window

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 42: Initialize And Load Mode Registers

NOTE:

1. V

is not applied directly to the device; however,

VTD should be greater than or equal to zero to avoid device latch-up.

Q, V

, and V

REF

, must be equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up,

even if V

Q are 0V, provided a minimum of 42 ohms of series resistance is used between the V

supply and the input

pin. Once initialized, V

REF

must always be powered with in specified range.

2. Reset the DLL with A8 = H while programming the operating parameters.
3.

MRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can

be issued.

4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any

bank. If another LMR command is issued, the same operating parameter, previously issued, must be used.

6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE com-

mand, RA = Row Address, BA = Bank Address.

VTD

CKE

LVCMOS
LOW LEVEL

BA0, BA1

200 cycles of CK

Load Extended

Mode Register

Load Mode

tMRD

tRP

tRFC

Power-up: V

and CK stable

T = 200µs

High-Z

DQS

High-Z

A0-A9,

A11, A12, A13

A10

ALL BANKS

CK#

REF

COMMAND

LMR

NOP

PRE

LMR

ACT5

tIS tIH

BA0 = H,

BA1 = L

tIS

tIH

BA0 = L,

BA1 = L

tIS

tIH

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

CODE CODE

tIS

tIH

CODE CODE

PRE

ALL BANKS

tIS

tIH

Ta0

Tb0

Tc0

Td0

Te0

Tf0

(

)

(

)

DON'T CARE

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tRP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

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-75

SYMBOL

MIN

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UNITS

0.45

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0.55

CK (2.5)

7.5

CK (2)

.90

MRD

RFC

120

VTD

-75

SYMBOL

MIN

MAX

UNITS

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 44: Auto Refresh Mode

NOTE:

1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active

during clock positive transitions.

3. NOP or COMMAND INHIBIT are the only commands allowed until after

RFC time, CKE must be active during clock positive tran-

sitions.

4. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active

banks).

5. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.

CK#

COMMAND

NOP2

VALID

NOP 2

NOP2

PRE

CKE

A0-A9, A11

A12, A13

A10

BA0, BA1

Bank(s)4

NOP2, 3

AR6

NOP2, 3

ACT

NOP2

ONE BANK

ALL BANKS

DQS

tRFC5

tRP

tRFC

Ta0

Tb0

Ta1

Tb1

Tb2

DON'T CARE

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SYMBOL

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MAX

UNITS

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0.55

CK (2.5)

7.5

CK (2)

.90

RFC

120

-75

SYMBOL

MIN

MAX

UNITS

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 45: Self Refresh Mode

NOTE:

1. Clock must be stable until after the self refresh command has been registered. A change in clock frequency is

allowed before Ta0, provided it is within the specified

CK limits. Regardless, the clock must be stable before exiting

self refresh mode. That is, the clock must be cycling within specifications by Ta0.

2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command.
3. Auto Refresh is not required at this point, but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5.

XSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until

Tb1.

XSRD (200 cycles of a valid CK and CKE = high) is required before any READ command can be applied.

7. As a general rule, any time Self Refresh Mode is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have

been refreshed via the Auto Refresh command at the distributed refresh rate,

REFI, or faster. However, the following exception

is allowed. Self Refresh Mode may be re-entered anytime after exiting, if the following conditions are all met:

a. The DRAM had been in the Self Refresh Mode for a minimum of 200ms prior to exiting.
b.

XSNR and

XSRD are not violated.

c. At least two Auto Refresh commands are performed during each

REFI interval while the DRAM remains out of Self

Refresh mode.

8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.

CK#

COMMAND

NOP

ADDR

CKE

DQS

NOP

tCK

tIS

Enter Self Refresh Mode

Exit Self Refresh Mode

Ta1

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-75

SYMBOL

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

.90

RFC

120

XSNR

127.5

XSRD

200

-75

SYMBOL

MIN

MAX

UNITS

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 48: Bank Write - Without Auto Precharge

NOTE:

1. DIn = data-in. from column n; subsequent elements are provided in the programmed order.

2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. "Don't Care" if A10 is HIGH at T8.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. See Figure 41, "Data Input Timing," on page 62 for detailed DQ timing.

CK#

CKE

A10

BA0, BA1

RCD

RAS

T5n

T4n

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DQS

tDS

tDH

DON'T CARE

TRANSITIONING DATA

DQSS (NOM)

WPRE

WPRES

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

x4: A13

x8: A12, A13

x16: A11, A12, A13

-75

SYMBOL

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

0.5

DQSH

0.35

DQSL

0.35

DQSS

0.75

1.25

DSS

0.2

DSH

0.2

RAS

120,000

RCD

WPRE

0.25

WPRES

WPST

0.4

0.6

-75

SYMBOL

MIN

MAX

UNITS

1Gb: x4, x8, x16

DDR SDRAM

PRELIMINARY

09005aef8076894f

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN

Figure 50: Write - DM Operation

NOTE:

1. DIn = data-in from column n; subsequent elements are provided in the programmed order.

CK#

CKE

A10

BA0, BA1

RCD

RAS

tRP

tWR

T5n

T4n

NOP6

COMMAND

ACT

Col n

WRITE2

NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6

DQSL

DQSH

WPST

Bank x4

DQS

DQSS (NOM)

WPRES

WPRE

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

x4: A13

x8: A21, A13

x16: A11, A12, A13

DON'T CARE

TRANSITIONING DATA

-75

SYMBOL

MIN

MAX

UNITS

0.45

0.55

0.45

0.55

CK (2.5)

7.5

CK (2)

0.5

DQSH

0.35

DQSL

0.35

DQSS

0.75

1.25

DSS

0.2

DSH

0.2

RAS

120,000

RCD

WPRE

0.25

WPRES

WPST

0.4

0.6

-75

SYMBOL

MIN

MAX

UNITS

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT46V256M4

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT46V256M4