256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

PRELIMINARY

Architecture

32 Meg x 4

16 Meg x 8

8 Meg x 16

Configuration

8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks

Refresh Count

Row Addressing

4K (A0A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

2K (A0A9, A11)

1K (A0A9)

512 (A0 A8)

DOUBLE DATA RATE
(DDR) SDRAM

MT46V32M4 8 Meg x 4 x 4 banks
MT46V16M8 4 Meg x 8 x 4 banks
MT46V8M16 2 Meg x 16 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site:

www.micron.com/dramds

FEATURES

· 167 MHz Clock, 333 Mb/s/p data rate
· V

= +2.5V ±0.2V, V

Q = +2.5V ±0.2V

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)

· Internal, pipelined double-data-rate (DDR)

architecture; two data accesses per clock cycle

· Differential clock inputs (CK and CK#)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· DLL to align DQ and DQS transitions with CK
· Four internal banks for concurrent operation
· Data mask (DM) for masking write data (x16 has

two - one per byte)

· Programmable burst lengths: 2, 4, or 8
· Concurrent Auto Precharge option supported
· Auto Refresh and Self Refresh Modes
· FBGA package available
· 2.5V I/O (SSTL_2 compatible)
·

RAS lockout (

RAP =

RCD)

· Backwards compatible with DDR200 and DDR266

OPTIONS PART NUMBER

· Configuration

32 Meg x 4 (8 Meg x 4

x 4 banks)

32M4

16 Meg x 8 (4 Meg x 8 x 4 banks)

16M8

8 Meg x 16 (2 Meg x 16 x 4 banks)

8M16

· Plastic Package

66-Pin TSOP (OCPL)

T G

60-Ball FBGA (16x9mm)

· Timing - Cycle Time

6ns @ CL = 2.5 (DDR333BFBGA)

-6

6ns @ CL = 2.5 (DDR333BTSOP)

-6T

7.5ns @ CL = 2 (DDR266A)

-75Z

· Self Refresh

Standard

none

NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing

2. Supports PC2100 modules with 2-3-3 timing

CONFIGURATION

DDR333 COMPATIBILITY

DDR333 meets or surpasses all DDR266 timing re-

quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and

RAS lockout

for improved timing performance. The 128Mb, DDR333
device will support an (

REFI) average periodic refresh

interval of 15.6µs.

The standard 66-pin TSOP package is offered for

point-to-point applications where the FBGA package
is intended for the multi-drop systems.

The Micron 128Mb data sheet provides full specifi-

cations and functionality unless specified herein.

KEY TIMING PARAMETERS

SPEED

CLOCK RATE

DATA-OUT

ACCESS DQS-DQ

GRADE

CL = 2

CL = 2.5

WINDOW

SKEW

-6

133 MHz

167 MHz

2.15ns

±0.70ns

+0.35ns

-6T

133 MHz

167 MHz

2.0ns

±0.75ns

+0.45ns

-75Z

133 MHz

2.5ns

±0.75ns

+0.50ns

NOTE:

1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock

rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).

3. Slower speeds are included in the 128Mb base data

sheet (-75, -8).

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

FBGA PACKAGE PINOUT

DQ14
DQ12
DQ10

DQ8

REF

DQ15

A12
A11

A8
A6
A4

DQ13
DQ11

DQ9

UDQS

UDM

CK#
CKE

A9
A7
A5

DQ2
DQ4
DQ6

LDQS

LDM
WE#

RAS#

BA1

A0
A2

DQ0

CAS#

CS#

BA0
A10

A1
A3

DQ1
DQ3
DQ5
DQ7

A13

x16 (Top View)

NC
NC
NC
NC

REF

A12
A11

A8
A6
A4

DQ3

DQ2
DQS

CK#
CKE

A9
A7
A5

DQ0

DQ1

NC
NC

WE#

RAS#

BA1

A0
A2

CAS#

CS#

BA0
A10

NC
NC
NC
NC

A13

x4 (Top View)

NC
NC
NC
NC

REF

DQ7

A12
A11

A8
A6
A4

DQ6
DQ5
DQ4
DQS

CK#
CKE

A9
A7
A5

DQ1
DQ2
DQ3

NC
NC

WE#

RAS#

BA1

A0
A2

DQ0

CAS#

CS#

BA0
A10

A1
A3

NC
NC
NC
NC

A13

x8 (Top View)

FBGA PACKAGE MARKING

FBGA 60-BALL PACKAGE DIMENSION

Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.

Top mark contains five fields

12345

· Field 1 (Product Family)

DRAM

DRAM - ES

· Field 2 (Product Type)

2.5 Volt, DDR SDRAM, 60-ball

· Field 3 (Width)

x4 devices

x8 devices

x16 devices

· Field 4 (Density / Size)

128Mb

· Filed 5 (Speed Grade)

-6

-75Z

-75

-8

Example top mark for a MT46V32M4FJ-6: DLBFJ

1.20 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: Ø .33mm

0.850 ±0.075

16.00 ±0.10

8.00 ±0.05

SEATING PLANE

0.10 C

BALL A1

BALL A9

PIN A1 ID

61X

0.45

SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS Ø 0.40

5.50 ±0.05

11.00

1.00

TYP

0.80 TYP

1.80
CTR

9 .00 ±0.10

3.20 ±0.05

4.50 ±0.05

6.40

Bottom View

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

66-PIN TSOP PACKAGE PIN ASSIGMENT

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

DQ15

DQ14
DQ13

DQ12
DQ11

DQ10
DQ9

DQ8

NC
V

UDQS

DNU

REF

UDM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

x16

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5
DQ6

VssQ

DQ7

LDQS

DNU

LDM

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

x16

DQ7

DQ6

DQ5

DQ4

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

NC
V

DQ3

NC
NC
V

DQ2

NC
NC
V

DQS

DNU

REF

DM
CK#
CK
CKE
NC

A12
A11
A9
A8
A7
A6
A5
A4

DQ0

DQ1

DQ2

DQ3

NC
NC

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

DQ0

NC
NC

DQ1

NC
NC

DNU

WE#

CAS#
RAS#

CS#

BA0
BA1

A10/AP

A0
A1
A2
A3

66-PIN TSOP PACKAGE DIMENSION

SEE DETAIL A

0.10

0.65 TYP

0.71

10.16 ±0.08

0.15

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ± 0.08

0.32 ± .075 TYP

+0.03

-0.02

+0.10

-0.05

1.20 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

0.10 (2X)

GAGE PLANE

(TOP VIEW)

NOTE:

1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm

per side.

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

(continued on next page)

PIN DESCRIPTIONS

BALL / PIN NUMBERS

FBGA

TSOP

SYMBOL

TYPE

DESCRIPTION

G2, G3

45, 46

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

CKE

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V

is applied.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.

H7, G8, G7

23, 22, 21

RAS#, CAS#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE#

command being entered.

Input

Input Data Mask: DM is an input mask signal for write data. Input

F7, 3F

20, 47

LDM, UDM

data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8

J8,J7

26, 27

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

K7, L8, L7

29-32

A0, A1, A2

Input

Address Inputs: Provide the row address for ACTIVE commands, and

M8, M2, L3

32, 35, 36

A3, A4, A5

the column address and auto precharge bit (A10) for READ/WRITE

L2, K3, K2

36, 38, 39

A6, A7, A8

commands, to select one location out of the memory array in the

J3, K8, J2

40, 29, 41

A9, A10, A11

respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

PIN DESCRIPTIONS (continued)

BALL / PIN NUMBERS

FBGA

TSOP

SYMBOL

TYPE

DESCRIPTION

A8, B9, B7

2, 4, 5,

DQ0-2

I/O

Data Input/Output: Data bus for x16

C9, C7, D9

7, 8, 10

DQ3-5

D7, E9, E1

11, 13, 54

DQ6-8

D3, D1, C3

56, 57, 59

DQ9-11

C1, B3, B1,

60, 62, 63,

DQ12-14

DQ15

A8, B7, C7,

2, 5, 8,

DQ0-2

I/O

Data Input/Output: Data bus for x8

D7, D3, C3,

11, 56, 59

DQ3-5

B3, A2

62, 65

DQ6-7

B7, D7, D3,

5, 11, 56

DQ0-2

I/O

Data Input/Output: Data bus for x4

DQ2

DQS

I/O

Data Strobe: Output with read data, input with write data. DQS is

E7, E3

16, 51

LDQS, UDQS

edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.

14, 17, 25,

No Connect: These pins should be left unconnected.

43, 53

19, 50

DNU

Do Not Use: Must float to minimize noise on Vref

B2, D2, C8, 3, 9, 15, 55,

Supply

DQ Power Supply: +2.5V ±0.2V. Isolated on the die for improved

E8, A9

noise immunity.

A1, E2, B8,

6, 12, 52,

Supply

DQ Ground. Isolated on the die for improved noise immunity.

58, 64

F8, M7, A7

1, 18, 33

Supply

Power Supply: +2.5V ±0.2V.

A1, A3, F2,

34, 48, 66

Supply

Ground.

REF

Supply

SSTL_2 reference voltage.

A13

Address input A13 for 1Gb devices.

A12

For 256Mb and greater devices.

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

GENERAL DESCRIPTION

The DDR333 SDRAM is a high-speed CMOS, dy-

namic random-access memory that operates at a fre-
quency of 167 MHz (

CK=6ns) with a peak data trans-

fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.

The standard DDR200/DDR266 data sheets also

pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-

ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.

In addition to the standard 66-pin TSOP package,

a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para-
sitic parameters and a smaller footprint.

CAPACITANCE (TSOP)

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C

70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance:

DQs, DQS, DM (for x4 or x8 devices)

0.50

13, 24

DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),

0.50

13, 24

DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)

0.50

13, 24

Delta Input Capacitance: Command and Address

0.50

13, 29

Delta Input Capacitance: CK, CK#

0.25

p F

13, 29

Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)

4.0

5.0

Input Capacitance: Command and Address

2.0

3.0

Input Capacitance: CK, CK#

2.0

3.0

p F

Input Capacitance: CKE

2.0

3.0

CAPACITANCE (FBGA)

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C

70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Delta Input/Output Capacitance:

DQs, DQS, DM (for x4 or x8 devices)

0.50

13, 24

DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),

0.50

13, 24

DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)

0.50

13, 29

Delta Input Capacitance: Command and Address

0.50

13, 29

Delta Input Capacitance: CK, CK#

0.25

p F

13, 29

Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)

3.50

4.00

Input Capacitance: Command and Address

1.50

2.50

Input Capacitance: CK, CK#

1.50

2.50

p F

Input Capacitance: CKE

1.50

2.50

PRELIMINARY

256Mb: x4, x8, x16 DDR333 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mx4x8x16DDR333.p65 Rev. A; Pub. 10/01

128Mb: x4, x8, x16

DDR333 SDRAM Addendum

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C

70°C; V

Q = +2.5V ±0.2V, V

= +2.5V ±0.2V)

AC CHARACTERISTICS

-6 (FBGA)

-6T (TSOP)

-75Z

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS NOTES

Access window of DQs from CK/CK#

-0.7

+0.7

-0.7

+0.7

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5

CK (2.5)

7.5

45,52

CL = 2

CK (2)

7.5

45,52

DQ and DM input hold time relative to DQS

0.45

0.50

26,31

DQ and DM input setup time relative to DQS

0.45

0.50

26,31

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60

+0.60

-0.60

+0.60

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.35

0.45

0.50

25, 26

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

18,42

Data-out low-impedance window from CK/CK#

-0.70

-0.75

18,43

Address and control input hold time (fast slew rate)

0.75

0.90

Address and control input setup time (fast slew rate)

0.75

0.90

Address and control input hold time (slow slew rate)

0.80

Address and control input setup time (slow slew rate)

0.80

Address and control input pulse width

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

25, 26

QHS

Data Hold Skew Factor

QHS

0.50

0.60

0.75

ACTIVE to AUTOPRECHARGE command

RAP

ACTIVE to PRECHARGE command

RAS

70,000

120,000

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

20, 21

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

140.6

µs

Average periodic refresh interval

REFI

15.6

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT46V8M16