Document Outline
- Features/Options
- General Description
- Functional Block Diagram 128K x 18
- Functional Block Diagram 64K x 32/36
- General Description (continued)
- TQFP Pin Assignment Table
- Pin Assignment (Top View) 100-Pin TQFP
- TQFP Pin Descriptions
- TQFP Pin Descriptions (continued)
- Interleaved Burst Address Table (Mode = NC or HIGH)
- Linear Burst Address Table (Mode = LOW)
- Partial Truth Table for WRITE Commands (x18)
- Partial Truth Table for WRITE Commands (x32/x36)
- Truth Table
- Absolute Maximum Ratings
- 3.3V I/O DC Electrical Characteristics and Operating Conditions
- 2.5V I/O DC Electrical Characteristics and Operating Conditions
- IDD Operating Conditions and Maximum Limits
- TQFP Capacitance
- TQFP Thermal Resistance
- Electrical Characteristics and Recommended AC Operating Conditions
- 3.3V I/O AC Test Conditions
- 2.5V I/O AC Test Conditions
- 3.3V I/O Output Load Equivalents
- 2.5V I/O Output Load Equivalents
- Load Derating Curves
- SNOOZE MODE
- SNOOZE MODE Electrical Characteristics
- SNOOZE MODE Waveform
- READ Timing
- WRITE Timing
- READ/WRITE Timing
- 100-Pin Plastic TQFP (JEDEC LQFP)
- Revision History
1
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
2002, Micron Technology, Inc.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
2Mb SYNCBURST
TM
SRAM
FEATURES
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Single-cycle deselect (Pentium
BSRAM-compatible)
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion
and address pipelining
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down for portable applications
100-pin TQFP package
Low capacitive bus loading
x18, x32, and x36 options available
OPTIONS
MARKING
Timing (Access/Cycle/MHz)
3.5ns/5ns/200 MHz
-5
3.5ns/6ns/166 MHz
-6
4.0ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
Configurations
3.3V I/O
128K x 18
MT58L128L18P
64K x 32
MT58L64L32P
64K x 36
MT58L64L36P
2.5V I/O
128K x 18
MT58L128V18P
64K x 32
MT58L64V32P
64K x 36
MT58L64V36P
Package
100-pin TQFP
T
Operating Temperature Range
Commercial (0C to +70C)
None
Part Number Example:
MT58L128L18PT-10
MT58L128L18P, MT58L64L32P, MT58L64L36P;
MT58L128V18P, MT58L64V32P, MT58L64V36P
3.3V V
DD
, 3.3V or 2.5V I/O, Pipelined, Single-
Cycle Deselect
GENERAL DESCRIPTION
The Micron
SyncBurst
TM
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron's 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#), and global write
(GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK), and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one
to four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
*JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP*
2
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
FUNCTIONAL BLOCK DIAGRAM
128K x 18
SA0, SA1, SA
ADDRESS
REGISTER
ADV#
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC#
17
17
15
17
BWb#
BWa#
CE#
18
BYTE "b"
WRITE REGISTER
BYTE "a"
WRITE REGISTER
ENABLE
REGISTER
18
SA0'
SA1'
OE#
SENSE
AMPS
128K x 9 x 2
MEMORY
ARRAY
ADSP#
9
9
2
SA0-SA1
MODE
CE2
CE2#
GW#
BWE#
DQs
DQPa
DQPb
2
18
OUTPUT
REGISTERS
18
E
18
BYTE "b"
WRITE DRIVER
BYTE "a"
WRITE DRIVER
OUTPUT
BUFFERS
PIPELINED
ENABLE
9
9
INPUT
REGISTERS
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
ADDRESS
REGISTER
ADV#
CLK
BINARY
COUNTER
CLR
Q1
Q0
ADSP#
ADSC#
MODE
16
16
14
16
BWd#
BWc#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE "d"
WRITE REGISTER
BYTE "c"
WRITE REGISTER
BYTE "b"
WRITE REGISTER
BYTE "a"
WRITE REGISTER
ENABLE
REGISTER
DQs
DQPa
DQPb
DQPc
DQPd
4
OUTPUT
REGISTERS
SENSE
AMPS
64K x 8 x 4
(x32)
64K x 9 x 4
(x36)
MEMORY
ARRAY
36
36
36
36
OUTPUT
BUFFERS
E
BYTE "a"
WRITE DRIVER
BYTE "b"
WRITE DRIVER
BYTE "c"
WRITE DRIVER
BYTE "d"
WRITE DRIVER
PIPELINED
ENABLE
INPUT
REGISTERS
SA0, SA1, SA
BWb#
BWa#
SA0'
SA1'
SA0-SA1
9
9
9
9
9
9
9
9
36
FUNCTIONAL BLOCK DIAGRAM
64K x 32/36
3
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
GENERAL DESCRIPTION (continued)
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
pins are only available on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
t
KQHZ nanoseconds after the rising edge
of clock.
Micron's 2Mb SyncBurst SRAMs operate from a
+3.3V V
DD
power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to Micron's Web site (
www.micron.com/
sramds
) for the latest data sheet.
*Pin 50 is reserved for address expansion.
**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
TQFP PIN ASSIGNMENT TABLE
PIN #
x18
x32/x36
1
NC
NC/
DQPc
**
2
NC
DQc
3
NC
DQc
4
V
DD
Q
5
V
S S
6
NC
DQc
7
NC
DQc
8
DQb
DQc
9
DQb
DQc
10
V
S S
11
V
DD
Q
12
DQb
DQc
13
DQb
DQc
14
V
DD
15
V
DD
16
NC
17
V
S S
18
DQb
DQd
19
DQb
DQd
20
V
DD
Q
21
V
S S
22
DQb
DQd
23
DQb
DQd
24
DQPb
DQd
25
NC
DQd
PIN #
x18
x32/x36
PIN #
x18
x32/x36
PIN #
x18
x32/x36
26
V
S S
27
V
DD
Q
28
NC
DQd
29
NC
DQd
30
NC
NC/
DQPd
**
31
MODE
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
S S
41
V
DD
42
DNU
43
DNU
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
NC/
SA
*
76
V
S S
77
V
DD
Q
78
NC
DQb
79
NC
DQb
80
SA
NC/DQPb**
81
SA
82
SA
83
ADV#
84
ADSP#
85
ADSC#
86
OE#
87
BWE#
88
GW#
89
CLK
90
V
S S
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc#
96
NC
BWd#
97
CE2
98
CE#
99
SA
100
SA
51
NC
NC/
DQPa
**
52
NC
DQa
53
NC
DQa
54
V
DD
Q
55
V
S S
56
NC
DQa
57
NC
DQa
58
DQa
59
DQa
60
V
S S
61
V
DD
Q
62
DQa
63
DQa
64
ZZ
65
V
DD
66
NC
67
V
S S
68
DQa
DQb
69
DQa
DQb
70
V
DD
Q
71
V
S S
72
DQa
DQb
73
DQa
DQb
74
DQPa
DQb
75
NC
DQb
4
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
PIN ASSIGNMENT (Top View)
100-Pin TQFP
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
NC/
SA
*
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x18
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
NC/
DQPb
**
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/
DQPa
**
NC/
SA
*
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
NC/
DQPc
**
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/
DQPd
**
x32/x36
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
*Pin 50 is reserved for address expansion.
**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
5
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
37
37
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
36
36
SA1
meet the setup and hold times around the rising edge of CLK.
32-35, 44-49, 32-35, 44-49,
SA
80-82, 99,
81, 82, 99,
100
100
93
93
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
94
94
BWb#
individual bytes to be written and must meet the setup and hold
95
BWc#
times around the rising edge of CLK. A byte write enable is LOW
96
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
87
87
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
88
88
GW#
Input
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
89
89
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
98
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
92
92
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
97
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
86
OE#
Input
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
83
83
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
84
84
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
(continued)
6
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
85
85
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
31
MODE
Input
Mode: This input selects the burst sequence. A LOW on this pin
selects "linear burst." NC or HIGH on this pin selects "interleaved
burst." Do not alter input state while device is operating.
64
64
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
(a)
58, 59,
(a)
52, 53,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated with
62, 63, 68, 69, 56-59, 62, 63
Output DQa pins; Byte "b" is associated with DQb pins. For the x32 and x36
72, 73
versions, Byte "a" is associated with DQa pins; Byte "b" is
(b)
8, 9, 12,
(b)
68, 69,
DQb
associated with DQb pins; Byte "c" is associated with DQc pins;
13, 18, 19, 22, 72-75, 78, 79
Byte "d" is associated with DQd pins. Input data must meet setup
23
and hold times around the rising edge of CLK.
(c)
2, 3, 6-9,
DQc
12, 13
(d)
18, 19,
DQd
22-25, 28, 29
74
51
NC/
DQPa
NC/
No Connect/Parity Data I/Os: On the x32 version, these pins are No
24
80
NC/
DQPb
I/O
Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b"
1
NC
/DQPc
parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte
30
NC/
DQPd
"b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.
14, 15, 41, 65, 14, 15, 41, 65,
V
DD
Supply Power Supply:
See DC Electrical Characteristics and Operating
91
91
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77
Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21,
V
SS
Supply Ground:
GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39, 42, 43 38, 39, 42, 43
DNU
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 16,
16, 66
NC
No Connect: These signals are not internally connected and may be
25, 28-30,
connected to ground to improve package heat dissipation.
51-53, 56, 57,
66, 75, 78, 79,
95, 96
50
50
NC/
SA
No Connect: This pin is reserved for address expansion.
7
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
FUNCTION
GW#
BWE#
BWa#
BWb#
READ
H
H
X
X
READ
H
L
H
H
WRITE Byte "a"
H
L
L
H
WRITE Byte "b"
H
L
H
L
WRITE All Bytes
H
L
L
L
WRITE All Bytes
L
X
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
GW#
BWE#
BWa#
BWb#
BWc#
BWd#
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte "a"
H
L
L
H
H
H
WRITE All Bytes
H
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
8
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa pins and DQPa. BWb# enables WRITEs to DQb pins and DQPb. BWc# enables WRITEs to
DQc pins and DQPc. BWd# enables WRITEs to DQd pins and DQPd. DQPa and DQPb are only available on the x18 and x36
versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
TRUTH TABLE
OPERATION
ADDRESS CE# CE2# CE2
ZZ
ADSP# ADSC# ADV# WRITE# OE# CLK
DQ
USED
DESELECT Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
9
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
.................................. -0.5V to +4.6V
Voltage on V
DD
Q Supply
Relative to V
SS
.................................. -0.5V to +4.6V
V
IN
.............................................. -0.5V to V
DD
Q + 0.5V
Storage Temperature (plastic) ........... -55C to +150C
Junction Temperature** ................................... +150C
Short Circuit Output Current .......................... 100mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
**Maximum junction temperature depends upon pack-
age type, cycle time, loading, ambient temperature,
and airflow. See Micron Technical Note TN-05-14 for
more information.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1, 4
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
3.135
3.6
V
1
Isolated Output Buffer Supply
V
DD
Q
3.135
3.6
V
1, 5
NOTE: 1. All voltages referenced to V
SS
(GND).
2. Overshoot:
V
IH
+4.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.7V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = 10A.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. AC load current is higher
than the shown DC values. AC I/O curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be connected together for 3.3V I/O.
10
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
NOTE: 1. All voltages referenced to V
SS
(GND).
2. Overshoot:
V
IH
+4.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.7V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = 10A.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O. AC load current is higher
than the shown DC values. AC I/O curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be connected together for 3.3V I/O.
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V +0.3V/-0.165V; V
DD
Q = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
V
IH
Q
1.7
V
DD
Q + 0.3
V
1, 2
Inputs
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Q (DQx)
Output High Voltage
I
OH
= -2.0mA
V
OH
1.7
V
1, 4
I
OH
= -1.0mA
V
OH
2.0
V
1, 4
Output Low Voltage
I
OL
= 2.0mA
V
OL
0.7
V
1, 4
I
OL
= 1.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
3.135
3.6
V
1
Isolated Output Buffer Supply
V
DD
Q
2.375
2.9
V
1
11
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
NOTE: 1. V
DD
Q = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; V
DD
Q = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times
and greater output loading.
3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device
is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25C and 10ns cycle time.
5. This parameter is sampled.
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A
= 25C; f = 1 MHz;
C
I
2.7
3.5
p F
5
Input/Output Capacitance (DQ)
V
DD
= 3.3V
C
O
4
5
p F
5
Address Capacitance
C
A
2.5
3.5
p F
5
Clock Capacitance
C
CK
2.5
3.5
p F
5
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0C
T
A
+70C; V
DD
= +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYM
TYP
-5
-6
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
100
400
340
280
225
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
ADSC#, ADSP#, GW#, BWx#, ADV#
I
DD
1
30
100
85
70
65
mA
2, 3, 4
V
IH
; All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
0.5
10
10
10
10
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
6
25
25
25
25
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
I
SB
4
30
100
85
70
65
mA
3, 4
V
IH
; All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
MAX
12
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Thermal Resistance
Test conditions follow standard test methods
JA
40
C/W
1
(Junction to Ambient)
and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
JC
8
C/W
1
(Junction to Top of Case)
NOTE: 1. Typical values are measured at 3.3V, 25C and 10ns cycle time.
13
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0C
T
A
+70C; V
DD
= +3.3V +0.3V/-0.165V)
-5
-6
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Clock
Clock cycle time
t
KC
5.0
6.0
7.5
10
ns
Clock frequency
f
KF
200
166
133
100
MHz
Clock HIGH time
t
KH
1.6
1.7
1.9
3.2
ns
2
Clock LOW time
t
KL
1.6
1.7
1.9
3.2
ns
2
Output Times
Clock to output valid
t
KQ
3.5
3.5
4.0
5.0
ns
Clock to output invalid
t
KQX
1.0
1.5
1.5
1.5
ns
3
Clock to output in Low-Z
t
KQLZ
0
1.5
1.5
1.5
ns
3, 4, 5, 6
Clock to output in High-Z
t
KQHZ
3.5
3.5
4.0
5.0
ns
3, 4, 5, 6
OE# to output valid
t
OEQ
3.5
3.5
4.0
5.0
ns
7
OE# to output in Low-Z
t
OELZ
0
0
0
0
ns
3, 4, 5, 6
OE# to output in High-Z
t
OEHZ
3.0
3.5
4.0
4.5
ns
3, 4, 5, 6
Setup Times
Address
t
AS
1.5
1.5
1.5
2.2
ns
8, 9
Address status (ADSC#, ADSP#)
t
ADSS
1.5
1.5
1.5
2.2
ns
8, 9
Address advance (ADV#)
t
AAS
1.5
1.5
1.5
2.2
ns
8, 9
Write signals
t
WS
1.5
1.5
1.5
2.2
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
t
DS
1.5
1.5
1.5
2.2
ns
8, 9
Chip enables (CE#, CE2#, CE2)
t
CES
1.5
1.5
1.5
2.2
ns
8, 9
Hold Times
Address
t
AH
0.5
0.5
0.5
0.5
ns
8, 9
Address status (ADSC#, ADSP#)
t
ADSH
0.5
0.5
0.5
0.5
ns
8, 9
Address advance (ADV#)
t
AAH
0.5
0.5
0.5
0.5
ns
8, 9
Write signals
t
WH
0.5
0.5
0.5
0.5
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
t
DH
0.5
0.5
0.5
0.5
ns
8, 9
Chip enables (CE#, CE2#, CE2)
t
CEH
0.5
0.5
0.5
0.5
ns
8, 9
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (V
DD
Q = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (V
DD
Q = +2.5V +0.4V/-0.125V) unless otherwise noted.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured 500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough
discussion on these parameters.
7. OE# is a "Don't Care" when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup
and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
14
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
Q
50
V = 1.5V
Z = 50
O
T
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
3.3V I/O AC TEST CONDITIONS
Input pulse levels ................. V
IH
= (V
DD
/2.2) + 1.5V
................... V
IL
= (V
DD
/2.2) - 1.5V
Input rise and fall times .................................... 1ns
Input timing reference levels ..................... V
DD
/2.2
Output reference levels ........................... V
DD
Q/2.2
Output load ........................... See Figures 1 and 2
LOAD DERATING CURVES
The Micron 128K x 18, 64K x 32, and 64K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Q
50
V = 1.25V
Z = 50
O
T
Figure 3
Q
225
225
5pF
+2.5V
Figure 4
2.5V I/O AC TEST CONDITIONS
Input pulse levels ............. V
IH
= (V
DD
/2.64) + 1.25V
............... V
IL
= (V
DD
/2.64) - 1.25V
Input rise and fall times .................................... 1ns
Input timing reference levels ................... V
DD
/2.64
Output reference levels .............................. V
DD
Q/2
Output load ........................... See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
15
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down"
mode in which the device is deselected and current is
reduced to I
SB
2Z
. The duration of SNOOZE MODE is
dictated by the length of time the ZZ pin is in a HIGH
state. After the device enters SNOOZE MODE, all in-
puts except ZZ become gated inputs and are ignored.
The ZZ pin is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE. When
the ZZ pin becomes a logic HIGH, I
SB
2Z
is guaranteed
after the setup time
t
ZZ is met. Any READ or WRITE
operation pending when the device enters SNOOZE
MODE is not guaranteed to complete successfully.
Therefore, SNOOZE MODE must not be initiated until
valid pending operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Current during SNOOZE MODE
ZZ
V
IH
I
SB
2Z
10
mA
ZZ active to input ignored
t
ZZ
2(
t
KC)
ns
1
ZZ inactive to input sampled
t
RZZ
2(
t
KC)
ns
1
ZZ active to snooze current
t
ZZI
2(
t
KC)
ns
1
ZZ inactive to exit snooze current
t
RZZI
0
ns
1
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
t
ZZ
I
SUPPLY
CLK
ZZ
t
RZZ
ALL INPUTS
(except ZZ)
DON'T CARE
I
ISB2Z
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
16
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
READ TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
ADV#
suspends
burst.
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
(NOTE 4)
Burst continued with
new base address.
DON'T CARE
UNDEFINED
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
AS
1.5
1.5
1.5
2.2
ns
t
ADSS
1.5
1.5
1.5
2.2
ns
t
AAS
1.5
1.5
1.5
2.2
ns
t
WS
1.5
1.5
1.5
2.2
ns
t
CES
1.5
1.5
1.5
2.2
ns
t
AH
0.5
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
0.5
ns
t
AAH
0.5
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
0.5
ns
READ TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
KC
5.0
6.0
7.5
10
ns
f
KF
200
166
133
100
MHz
t
KH
1.6
1.7
1.9
3.2
ns
t
KL
1.6
1.7
1.9
3.2
ns
t
KQ
3.5
3.5
4.0
5.0
ns
t
KQX
1.0
1.5
1.5
1.5
ns
t
KQLZ
0
1.5
1.5
1.5
ns
t
KQHZ
3.5
3.5
4.0
5.0
ns
t
OEQ
3.5
3.5
4.0
5.0
ns
t
OELZ
0
0
0
0
ns
t
OEHZ
3.0
3.5
4.0
4.5
ns
17
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON'T CARE
UNDEFINED
NOTE: 1. D(A2) refers to input for address A2. Q(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device;
or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
DS
1.5
1.5
1.5
2.2
ns
t
CES
1.5
1.5
1.5
2.2
ns
t
AH
0.5
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
0.5
ns
t
AAH
0.5
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
0.5
ns
t
DH
0.5
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
0.5
ns
WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
KC
5.0
6.0
7.5
10
ns
f
KF
200
166
133
100
MHz
t
KH
1.6
1.7
1.9
3.2
ns
t
KL
1.6
1.7
1.9
3.2
ns
t
OEHZ
3.0
3.5
4.0
4.5
ns
t
AS
1.5
1.5
1.5
2.2
ns
t
ADSS
1.5
1.5
1.5
2.2
ns
t
AAS
1.5
1.5
1.5
2.2
ns
t
WS
1.5
1.5
1.5
2.2
ns
18
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
READ/WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
(NOTE 5)
DON'T CARE
UNDEFINED
A3
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
t
ADSS
1.5
1.5
1.5
2.2
ns
t
WS
1.5
1.5
1.5
2.2
ns
t
DS
1.5
1.5
1.5
2.2
ns
t
CES
1.5
1.5
1.5
2.2
ns
t
AH
0.5
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
0.5
ns
t
DH
0.5
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
0.5
ns
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
READ/WRITE TIMING PARAMETERS
-5
-6
-7.5
-10
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
t
KC
5.0
6.0
7.5
10
ns
f
KF
200
166
133
100
MHz
t
KH
1.6
1.7
1.9
3.2
ns
t
KL
1.6
1.7
1.9
3.2
ns
t
KQ
3.5
3.5
4.0
5.0
ns
t
KQLZ
0
1.5
1.5
1.5
ns
t
OELZ
0
0
0
0
ns
t
OEHZ
3.0
3.5
4.0
4.5
ns
t
AS
1.5
1.5
1.5
2.2
ns
19
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
100-PIN PLASTIC TQFP (JEDEC LQFP)
14.00 0.10
1.40 0.05
16.00 0.20
0.10
+0.10
-0.05
0.15
+0.03
-0.02
22.10
+0.10
-0.20
0.32
+0.06
-0.10
20.10 0.10
0.65 TYP
0.625
1.60 MAX
DETAIL A
SEE DETAIL A
0.60 0.15
1.00 TYP
GAGE PLANE
0.25
0.10
PIN #1 ID
NOTE: 1. All dimensions in millimeters MAX or typical here noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
DATA SHEET DESIGNATIONS
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
20
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L128L18P_C.p65 Rev. C, Pub. 11/02
2002, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
PIPELINED, SCD SYNCBURST SRAM
NOT RECOMENDED FOR NEW DESIGNS
REVISION HISTORY
Added "NOT RECOMENDED FOR NEW DESIGNS," REV. C, Pub. 11/02, FINAL ........................ November/22/02
Removed 165-pin FBGA package, Rev. 6/01 .................................................................................................. June/7/01
Removed FBGA Part Marking Guide, REV 8/00, FINAL ........................................................................ August/22/00
Changed FBGA capacitance values, REV 8/00, FINAL ............................................................................. August/7/00
C
I
; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF
C
O
; TYP 4pF from 6pF; MAX. 5pF from 7pF
C
CK
; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF
Removed IT References, REV 7/00, FINAL ..................................................................................................... July/14/00
Added FBGA Part Marking Guide
Added Revision History to Datasheet
Removed IT from Part Number Example, REV 6/00, FINAL ....................................................................... June/21/00
Added # of datalines to the databus in x32/36 Block Diagram
Added Note - "Preliminary Package Data" to FBGA Capacitance and Thermal Resistance Tables
Changed heading on Mechanical Drawing from BGA to FBGA
Added 165-Pin FBGA package, REV 3/00, FINAL ..................................................................................... March/3/00
Added PRELIMINARY PACKAGE DATA to diagram
PDF 
ZIP