PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

DDR SDRAM
DIMM MODULE

MT8VDDT3232U

128MB

MT8VDDT6432U

256MB

For the latest data sheet, please refer to the Micron

â Web

site:

www.micron.com/moduleds

Features

· 100-pin, dual in-line memory module (DIMM)
· Fast data transfer rate PC2100 and PC2700
· Utilizes 266 MT/s or 333 MT/s DDR SDRAM

components

· 128MB (32 Meg x 32) and 256MB (64 Meg x 32)
· V

= V

Q = +2.5V

· 2.5V I/O (SSTL_2 compatible)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/

received with data--i.e., source-synchronous data
capture

· Differential clock inputs CK and CK#
· Four internal device banks for concurrent operation
· Programmable burst lengths: 2, 4, or 8
· Auto precharge option
· Serial Presence Detect (SPD) with EEPROM
· Programmable READ CAS latency
· Auto Refresh and Self Refresh Modes

15.625µs (128MB), 7.8125µs (256MB) maximum
average periodic refresh interval

Figure 1: 100-Pin DIMM (MO-161)

OPTIONS

MARKING

· Package

100-pin DIMM (gold)

· Frequency/CAS Latency

6ns/167 MHz (333MT/s) CL = 2.5

-6

7.5ns/133 MHz (266 MT/s) CL = 2.5

-75

Table 1:

Address Table

MT8VDDT3232U MT8VDDT6432U

Refresh Count

Row Addressing

8K (A0A11)

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Device Configuration

16 Meg x 8

32 Meg x 8

Column Addressing

1K (A0A9)

Module Rank Addressing

2 (S0#, S1#)

Table 2:

Part Numbers and Timing Parameters

PART NUMBER

MODULE
DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA BIT RATE

LATENCY

(CL -

RCD -

RP)

MT8VDDT3232UG-6__

128MB

32 Meg x 32

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT3232UG-75__

128MB

32 Meg x 32

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT8VDDT6432UG-6__

256MB

64 Meg x 32

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT8VDDT6432UG-75__

256MB

64 Meg x 32

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult
factory for current revision codes. Example: MT8VDDT3232UG-75B1

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

NOTE:

Pin 21 is No Connect for the 128MB module, or A12 for the 256MB module.

Figure 2: Module Layout

Table 3:

Pin Assignment
(100-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

DQ0

DQ18

DQ11

DQ19

DQ1

DQS0

CK0

A10

DQ24

CK0#

DQ25

DQ2

BA0

DQ3

CKE1

WE#

DQS3

NC/

A12

S0#

DQ26

DQ8

DQ16

DQ9

DQ27

DQ17

SA0

DQS1

DQS2

REF

DQ10

Table 4:

Pin Assignment
(100-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

DQ4

DQ22

DQ15

DQ23

DQ5

BA1

DM0

CK1

RAS#

DQ28

CK1#

DQ29

DQ6

CAS#

DQ7

CKE0

S1#

DM3

A11

DNU

DQ30

DQ12

DQ20

DQ13

DQ31

DQ21

SDA

DM1

DM2

100

SCL

DQ14

PIN100

PIN 50

PIN 23

PIN 1

PIN 51

PIN 73

Indicates a V

or V

DDQ

Indicates a V

Front View

Back View

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

REF

Input

SSTL_2 reference voltage.

32, 79, 81

WE#, CAS#, RAS#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.

17, 18, 67, 68

CK0, CK0#,

CK1, CK1#

Input

Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQ and DQS) is referenced to the crossings of CK and CK#.

20, 70

CKE0, CKE1

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank).CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK#, and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V

is applied.

33, 82

S0#, S1#

Input

Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.

31, 78

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

(256MB)

, 23, 24, 26-29,

71-74, 76, 77

A0-A11

(128MB)

A0-A12

(256MB)

Input

Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.

4, 12, 37, 45

DQS0-DQS3

Input/

Output

Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.

54, 62, 87, 95

DM0-DM3

Input

Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.

1, 3, 6, 7, 9,10, 13, 15, 34, 36,

39, 40, 42, 43, 46, 48, 51, 53,
56, 57, 59, 60, 63, 65, 84, 86,

89, 90, 92, 93, 96, 98

DQ0-DQ31

Input/

Output

Data I/Os: Data bus.

SA0

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

100

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.

5, 8, 14, 19, 30, 38, 41, 55,

58, 64, 69, 80, 88, 91

Supply

Power Supply: +2.5V ±0.2V (See note 49 on page 19).

2, 11, 16, 25, 35, 44, 47, 52,

61, 66, 75, 85, 94, 97

Supply

Ground.

DNU

Do Not Use: This pin is not connected on these modules, but is
an assigned pin on other modules in this product family.

21 (128MB only), 22

No Connect: These pins should be left unconnected.

Table 5:

Pin Descriptions (Continued)

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Figure 3: Functional Block Diagram

DDR SDRAMs = MT46V16M8TG for 128MB Module
DDR SDRAMs = MT46V32M8TG for 256MB Module

SA0

SPD

SDA

RAS#

CAS#

CKE0

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs U1-U4

CKE1: DDR SDRAMs U5-U8

WE#: DDR SDRAMS

A0-A11: DDR SDRAMs

A0-A12: DDR SDRAMs

BA0: DDR SDRAMs

BA1: DDR SDRAMs

CKE1

WE#

A0-A11(128MB)

A0-A12 (256MB)

BA0

BA1

REF

SPD

DDR SDRAMs

SCL

S0#

S1#

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DM0

DM CS# DQS

DQS0

DM1

DQS1

DM2

DQS2

DM CS# DQS

DM3

DQS3

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DDR SDRAM X4

CK0
CK0#

120

DDR SDRAM X4

CK1
CK1#

120

DDR SDRAMs
(V

and V

DDR SDRAMs, SPD

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

NOTE: All resistor values are 22

W unless otherwise specified.

Per industry standard, Micron modules utilize various component speed grades, as referenced in the
module part number guide at

www.micron.com/numberguide

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

General Description

The MT8VDDT3232U and MT8VDDT6432U are

high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in x32 config-
uration. These modules use internally configured
quad-bank DDR SDRAMs.

These DDR SDRAM modules use a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM mod-
ule effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

These DDR SDRAM modules operate from differen-

tial clock inputs (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as
the positive edge of CK. Commands (address and con-
trol signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to the DDR SDRAM mod-

ules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the device bank and row
to be accessed (BA0, BA1 select devices bank; A0A11
select device row for 128MB module, A0A12 select
device row for 256MB module). The address bits regis-
tered coincident with the READ or WRITE command
are used to select the device bank and the starting
device column location for the burst access (BA0, BA1;
A0A9).

These DDR SDRAM modules provide for program-

mable READ or WRITE burst lengths of 2, 4, or 8 loca-
tions. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb and 256Mb DDR SDRAM component data
sheets.

Serial Presence-Detect Operation

These DDR SDRAM modules incorporate serial

presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard IIC bus using the DIMM's SCL (clock) and
SDA (data) signals, together with SA (2:0), which pro-
vide eight unique DIMM/EEPROM addresses.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in Fig-
ure 4, Mode Register Definition Diagram, on page 7.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A11
(128MB module) or A7A12 (256MB module) specify
the operating mode.

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Mode Register Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A9 when the burst length is set to two,
by A2-A9 when the burst length is set to four and by
A3-A9 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The
programmed burst length applies to both READ and
WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition
Table.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram, on page 8.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA1and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

128MB Module Address Bus

256MB Module Address Bus

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

NOTE:

1. For a burst length of two, A1A9 select the two-

data-element block; A0 selects the first access
within the block.

2. For a burst length of four, A2A9 select the four-

data-element block; A0A1 select the first access
within the block.

3. For a burst length of eight, A3A9 select the eight-

data-element block; A0A2 select the first access
within the block.

4. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7A11 (for
128MB module), or A7A12 (256MB module) each set
to zero, and bits A0-A6 set to the desired values. A DLL
reset is initiated by issuing a MODE REGISTER SET
command with bits A7 and A9A11 (for 128MB mod-
ule), or A7 and A9A12 (256MB module) each set to
zero, bit A8 set to one, and bits A0A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.

All other combinations of values for A7A11, or A7

A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.

Table 6:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Table 7:

CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED

CL = 2

CL = 2.5

-6

N/A

£ f £167

-75

£ f £ 100

£ f £133

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable, output
drive strength, and QFC#. These functions are con-
trolled via the bits shown in Figure 6, Extended Mode
Register Definition Diagram. The extended mode reg-
ister is programmed via the LOAD MODE REGISTER
command to the mode register (with BA0 = 1 and BA1
= 0) and will retain the stored information until it is
programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

Output Drive Strength

The normal full drive strength for all outputs is

specified to be SSTL2, Class II. For detailed informa-
tion on output drive strength, refer to 128MB and
256Mb DDR SDRAM component data sheets.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Figure 6: Extended Mode Register

Definition Diagram

Operating Mode

Normal Operation

All other states reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

QFC Function

Disabled

Reserved

E1,

Operating Mode

A10

A11

BA1 BA0

Notes: 1. E13 and E12 (BA1 and BA0) must be "0, 1" to select the
Extended Mode Register (vs. the base Mode Register) for

128MB module, or E14 and E13 for 256MB module.

2. The QFC option is not supported.

E2,

E6 E5

E10

E11

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Operating Mode

A10

A11

A12

BA1 BA0

QFC#

128MB Module

256MB Module

QFC#

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

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DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Commands

The Truth Tables below provide a general reference

of available commands. For a more detailed descrip-

tion of commands and operations, refer to the 128Mb
or 256Mb DDR SDRAM component data sheet.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;

BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0BA1 are reserved). A0A11 (128MB
module) or A0A12 (256MB module) provide the op-code to be written to the selected mode register.

3. BA0BA1 provide device bank address and A0-A11 (128MB module) or A0A12 (256MB module) provide row

address.

4. BA0BA1 provide device bank address; A0A9 provide column address; A10 HIGH enables the auto precharge fea-

ture (nonpersistent), and A10 LOW disables the auto precharge feature.

5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and

BA0BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for

READ bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.
10.Used to mask write data; provided coincident with the corresponding data.

Table 8:

Truth Table Commands

Note: 1

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 9:

Truth Table DM Operation

Note: 10

NAME (FUNCTION)

DQS

WRITE Enable

Valid

WRITE Inhibit

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

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DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on VDD Supply

Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VDDQ Supply

Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs

Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to VSS . . . . . . . . . . . . -0.5V to V

Q +0.5V

Operating Temperature,

TA (ambient). . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 15, 14, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

32, 36

I/O Supply Voltage

2.3

2.7

32, 36, 39

I/O Reference Voltage

REF

0.49

0.51

6, 39

I/O Termination Voltage (system)

REF

- 0.04 V

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(DC)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(DC)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

£ VDD, V

REF

pin 0V

£ V

1.35V (All other pins not under test = 0V)

Command/

Address, RAS#,

CAS#, WE#,

-16

µA

CKE0, CKE1,

S0#, S1#

CK, CK#

-8

-4

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ V

OUT

£ V

DDQ

)

DQ, DQS

-10

µA

OUTPUT LEVELS

High Current (V

OUT

= V

DDQ

-0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

Table 11: AC Input Operating Conditions

Notes: 15, 14, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(AC)

REF

+ 0.310

12, 25, 35

Input Low (Logic 0) Voltage

(AC)

REF

- 0.310

12, 25, 35

I/O Reference Voltage

REF

(AC)

0.49

´ V

0.51

´ V

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

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Table 12: I

Specifications and Conditions 128MB Module

DDR SDRAM components only
Notes: 15, 14, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-6

-75

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

TBD

432

20, 43

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address

and control inputs changing once per clock cycle

DD1

TBD

492

20, 43

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks

idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

TBD

21, 28, 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK MIN; CKE = HIGH; Address and other control inputs changing

once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

TBD

360

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

TBD

160

21, 28, 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle

DD3N

TBD

360

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

TBD

512

20, 43

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4W

TBD

472

AUTO REFRESH CURRENT

RC =

RC(MIN)

DD5

TBD

1,680

20, 45

RC = 15.625µs

DD5A

TBD

24, 45

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

TBD

OPERATING CURRENT: Four device bank interleaving READs (BL =

4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address

and control inputs change only during Active READ or WRITE
commands

DD7

TBD

1,312

20, 44

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Table 13: I

Specifications and Conditions 256MB Module

DDR SDRAM components only
Notes: 15, 14, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYMBOL

-6

-75

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs
changing once every two clock cycles

DD0

TBD

496

20, 43

OPERATING CURRENT: One device bank; Active -Read Precharge;

Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address

and control inputs changing once per clock cycle

DD1

TBD

576

20, 43

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

TBD

21, 28, 45

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

TBD

320

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

TBD

240

21, 28, 45

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device

bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ,

DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle

DD3N

TBD

360

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

TBD

736

20, 43

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once

per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle

DD4W

TBD

772

AUTO REFRESH CURRENT

RC =

RC(MIN)

TBD

1,960

20, 45

RC = 7.8125µs

DD5A

TBD

24, 45

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

TBD

OPERATING CURRENT: Four device bank interleaving READs (BL =

4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address

and control inputs change only during Active READ or WRITE
commands

DD7

TBD

1,476

20, 44

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

2p (CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Table 14: Capacitance (All Modules)

Note: 11; notes appear following parameter tables.

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS, DM

Input Capacitance: Command and Address

Input Capacitance: S0#, S1#; CK0, CK0#; CK1, CK1#; CKE0, CKE1

Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions

Notes: 15, 1215, 29, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-6

-75

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS NOTES

Access window of DQ from CK/CK#

-0.7

+0.7

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

40, 47

CL=2

CK (2)

7.5

40, 47

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.6

+0.6

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group,
per access

DQSQ

0.45

0.5

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 37

Data-out low-impedance window from CK/CK#

-0.7

-0.75

16, 38

Address and control input hold time (fast slew rate)

0.75

.90

Address and control input setup time (fast slew rate)

0.75

.90

Address and control input hold time (slow slew rate)

0.8

Address and control input setup time (slow slew rate)

0.8

LOAD MODE REGISTER command cycle time

MRD

DQDQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.6

0.75

ACTIVE to PRECHARGE command

RAS

70,000

120,000

128MB, 256MB (x32)

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ADVANCE

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DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

ACTIVE to READ with Auto precharge command 128MB

RAP

RAS (MIN) -

burst length *

CK/2

ACTIVE to READ with Auto precharge command 256MB

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

128MB

REFC

140

140.6

µs

REFRESH to REFRESH command interval

256MB

REFC

70.3

µs

Average periodic refresh interval

128MB

REFI

15.6

µs

Average periodic refresh interval

256MB

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (Continued)

Notes: 15, 1215, 29, 49; notes appear on pages 1619; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-6

-75

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS NOTES

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(AC)

and V

(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

bypass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time at CL = 2.5 for -6 and -75 with the
outputs open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= VSS, f = 100 MHz,

= 25°C, V

OUT

(DC) = V

Q/2, V

OUT

(peak to

peak) = 0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in load-
ing.

12. Command/Address input slew rate = 0.5V/ns. For

-75 with slew rates 1V/ns and faster,

IS and

are reduced to 900ps. If the slew rate is less than

0.5V/ ns, timing must be derated:

IS has an addi-

tional 50ps per each 100mV/ns reduction in slew
rate from the 500mV/ns.

IH has 0ps added, that

is, it remains constant. If the slew rate exceeds
4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is
V

16.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. The maximum limit for this parameter is not a

device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

Output
(V

OUT

)

Reference

Point

30pF

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Figure 7: Derating Data Valid Window

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (128MB module) or
7.8125µs (256MB module). However, an AUTO
REFRESH command must be asserted at least
once every 140.6µs (128MB module) or 70.3µs
(256MB module); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.

22. The valid data window is derived by achieving

other specifications -

HP (

CK/2),

DQSQ, and

QH (

QH =

HP -

QHS). The data valid window

derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.

23. Referenced to each output group: x8 = DQ0-DQ7.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, V

(AC)

or V

(AC).

b. Reach at least the target AC level.
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(DC)

or V

(DC).

26. JEDEC specifies CK and CK# input slew rate must

1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-
tain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.

(

QH -

DQSQ)

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-75@

CK = 10ns

-75@

CK = 7.5ns

-6 TBD

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS (MIN) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch to the nominal voltage must be

less than 1/3 of the clock and not more than
+400mV or 2.9 volts maximum, whichever is less.
Any negative glitch must be less than 1/3 of the
clock cycle and not exceed either -300mV or 2.2
volts minimum, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum V

level and the referenced test load. In

practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

35. V

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(MIN) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

36. V

and V

Q must track each other.

37. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to

310ps less for

HZ (MAX) and the last DVW.

(MAX) will prevail over

DQSCK (MAX) +

RPST

(MAX) condition.

LZ (MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

38. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

39. During initialization, V

Q, V

, and V

REF

must

be equal to or less than V

+ 0.3V. Alternatively,

may be 1.35V maximum during power up,

even if V

DDQ

are 0 volts, provided a mini-

mum of 42 ohms of series resistance is used
between the V

supply and the input pin.

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

41.

RAP

RCD.

42. For the -6 and -75 I

3N is specified to be 35mA at

100 MHz.

Figure 8: Pull-Down Characteristics

Figure 9: Pull-Up Characteristics

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43. Random addressing changing 50 percent of data

changing at every transfer.

44. Random addressing changing 100 percent of data

at every transfer.

45. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

REF later.

46. I

2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. I

2Q is

similar to I

2F except I

2Q specifies the

address and control inputs to remain stable.
Although I

2F, I

2N, and I

2Q are similar,

2F is "worst case."

47. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.

48. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

49. The -6 module speed grade, using the -6R speed

device, has V

(MIN) = 2.4V.

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 10, Data Validity and Figure 11, Defini-
tion of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 12, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 10: Data Validity

Figure 11: Definition of Start and Stop

Figure 12: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

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Table 16: EEPROM Device Select Code

The most significant bit (b7) is sent first

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 17: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions

= +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

2.3

2.7

INPUT HIGH VOLTAGE: Logic 1; All inputs

´ 0.7

+ 1

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

´ 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

±2

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

±2

µA

POWER SUPPLY CURRENT: SCL clock frequency = 400 KHz

1.0

STAND-BY SUPPLY CURRENT: VIN = V

or V

, V

= 2.5 V

0.5

µA

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Figure 13: SPD EEPROM Timing Diagram

NOTE:

1. For a reSTART condition, or following a WRITE cycle.
2. This parameter is sampled.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising

edge of SDA.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

Table 19: Serial Presence-Detect EEPROM AC Operating Conditions

Notes: 1; V

= +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

200

900

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

600

Clock HIGH period

HIGH

600

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

300

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

600

Stop condition setup time

SU:STO

600

WRITE cycle time

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Table 20: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 24

BYTE

DESCRIPTION

ENTRY (VERSION)

MT8VDDT3232U

MT8VDDT6432U

NUMBER OF SPD BYTES USED BY MICRON

128

TOTAL NUMBER OF BYTES IN SPD DEVICE

256

FUNDAMENTAL MEMORY TYPE

DDR SDRAM

NUMBER OF ROW ADDRESSES ON ASSEMBLY

12, 13

NUMBER OF COLUMN ADDRESSES ON
ASSEMBLY

NUMBER OF PHYSICAL RANKS ON DIMM

MODULE DATA WIDTH

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS (V

SSTL 2.5V

SDRAM CYCLE TIME, (

CK)

(CAS LATENCY = 2.5)

6ns (-6)

7.5ns (-75)

60
75

SDRAM ACCESS FROM CLOCK (

AC)

(CAS LATENCY = 2.5)

0.7ns (-6)

0.75ns (-75)

70
75

MODULE CONFIGURATION TYPE

None

REFRESH RATE/TYPE

15.62µs, 7.8µs/SELF

SDRAM DEVICE WIDTH
(PRIMARY DDR SDRAM)

ERROR-CHECKING DDR SDRAM DATA WIDTH

None

MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS

1 clock

BURST LENGTHS SUPPORTED

2, 4, 8

NUMBER OF BANKS ON DDR SDRAM DEVICE

CAS LATENCIES SUPPORTED

2, 2.5

CS LATENCY

WE LATENCY

SDRAM MODULE ATTRIBUTES

Unbuffered/Diff. Clock

SDRAM DEVICE ATTRIBUTES: GENERAL

Fast/Concurrent AP

SDRAM CYCLE TIME, (

CK)

(CAS latency = 2)

7.5ns (-6)

10ns (-75)

SDRAM ACCESS FROM CLOCK (

AC)

(CAS LATENCY = 2)

0.7ns (-6)

0.75ns (-75)

70
75

SDRAM CYCLE TIME, (

CK)

(CAS LATENCY = 1.5)

N/A

SDRAM ACCESS FROM CK , (

AC)

(CAS LATENCY = 1.5)

N/A

MINIMUM ROW PRECHARGE TIME, (

RP)

18ns (-6)

20ns (-75)

48
50

MINIMUM ROW ACTIVE TO ROW ACTIVE,

(

RRD)

12ns (-6)

15ns (-75)

30
3C

MINIMUM RAS# TO CAS# DELAY, (

RCD)

18ns (-6)

20ns (-75)

48
50

MINIMUM RAS# PULSE WIDTH, (

RAS)

(See note 1)

42ns (-6)

45ns (-75)

2A
2D

MODULERANK DENSITY

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NOTE:

1. The value of

RAS used for -75 modules is calculated from

RC -

RP. Actual device spec. value is 40 ns.

2. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value

is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster
minimim slew rate is met.

ADDRESS AND COMMAND SETUP TIME, (

IS)

[Value set to slow slew rate (

)] (See note 2)

0.8ns (-6)

1.0ns (-75)

ADDRESS AND COMMAND HOLD TIME, (

IH);

[Value set to slow slew rate (

)] (See note 2)

0.8ns (-6)

1.0ns (-75)

DATA/DATA MASK INPUT SETUP TIME, (

DS)

0.45ns (-6)

0.5ns 9-75)

45
50

DATA/DATA MASK INPUT HOLD TIME, (

DH)

0.45ns (-6)
0.5ns (-75)

45
50

36-40 RESERVED

MIN ACTIVE AUTO REFRESH TIME (

RC)

60ns (-6)

65ns (-75)

3C
41

MINIMUM AUTO REFRESH TO ACTIVE/AUTO

REFRESH COMMAND PERIOD, (

RFC)

72ns (-6)

75ns (-75)

48
4B

SDRAM DEVICE MAX CYCLE TIME (

MAX

)

12ns (-6)

13ns (-75)

30
34

SDRAM DEVICE MAX DQS-DQ SKEW TIME

(

DQSQ)

0.45ns (-6)
0.5ns (-75)

SDRAM DEVICE MAX READ DATA HOLD SKEW

FACTOR (

QHS)

0.55ns (-6)

0.75ns (-75)

55
75

RESERVED

DIMM Height

4861 RESERVED

SPD REVISION

Release 1.0

CHECKSUM FOR BYTES 0-62

-6

-75

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71 MANUFACTURER'S JEDEC ID CODE

(Continued)

MANUFACTURING LOCATION

0112

010C

73-90 MODULE PART NUMBER (ASCII)

Variable Data

PCB IDENTIFICATION CODE

1-9

01-09

IDENTIFICATION CODE (continued)

YEAR OF MANUFACTURE IN BCD

Variable Data

WEEK OF MANUFACTURE IN BCD

Variable Data

95-98 MODULE SERIAL NUMBER

Variable Data

99-127 MANUFACTURER-SPECIFIC DATA (RSVD)

Table 20: Serial Presence-Detect Matrix (Continued)

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 24

BYTE

DESCRIPTION

ENTRY (VERSION)

MT8VDDT3232U

MT8VDDT6432U

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

128MB, 256MB (x32)

100-PIN DDR DIMM

ADVANCE

32, 64 Meg x 32 DDR SDRAM DIMMs

DD8C32_64X32UG_C.fm - Rev. C 7/03 EN

Figure 14: 100-Pin DIMM Dimensions

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

Advance: This data sheet contains initial descrip-

tions of products still under development.

0.157 (4.0)

MAX

PIN 1

3.556 (90.32)
3.544 (90.02)

0.70 (17.78)

TYP

0.118 (3.0) DIA

(2X)

0.050 (1.27)

TYP

0.039 (1.0)

TYP

0.079 (2.00) R

(2X)

PIN 50

PIN 100

PIN 51

FRONT VIEW

2.850 (72.39)

0.118 (3.0)

0.054 (1.37)
0.046 (1.17)

TYP

0.039 (1.0) R (2X)

0.118 (3.0)

BACK VIEW

1.206 (30.63)
1.194 (30.33)

MAX

MIN

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