CDC 32xxG-C
Automotive Controller Family
User Manual
CDC 3205G-C
Automotive Controller
Specification
Edition June 12, 2003
6251-579-1PD
PRELIMINARY DATA SHEET
MICRONAS
MICRONAS
CDC 32xxG-C
PRELIMINARY DATA SHEET
2
June 12, 2003; 6251-579-1PD
Micronas
Contents
Page
Section
Title
7
1.
Introduction
7
1.1.
Features
9
1.2.
Abbreviations
10
1.3.
Block Diagram
11
2.
Packages and Pins
11
2.1.
Pin Assignment
14
2.2.
Package Outline Dimensions
15
2.3.
Multiple Function Pins
15
2.4.
Pin Function Description
19
2.5.
External Components
20
2.6.
Pin Circuits
23
3.
Electrical Data
23
3.1.
Absolute Maximum Ratings
24
3.2.
Recommended Operating Conditions
25
3.3.
Characteristics
34
3.4.
Recommended Quartz Crystal Characteristics
35
4.
CPU and Clock System
35
4.1.
ARM7TDMITM CPU
35
4.2.
Operating Modes
39
4.3.
Clock System
41
4.4.
Memory Controller
43
4.5.
EMI Reduction Module (ERM)
44
4.6.
Registers
46
4.7.
PLL/ERM Application Notes
49
5.
Memory and Special Function ROM (SFR) System
50
5.1.
RAM and ROM
51
5.2.
I/O Map
52
5.3.
Special Function ROM (SFR)
55
6.
Core Logic
55
6.1.
Control Word (CW)
56
6.2.
Device Lock Module (DLM)
57
6.3.
Standby Registers
58
6.4.
UVDD Analog Section
60
6.5.
Reset Logic
64
6.6.
Test Registers
67
7.
Power Saving Module (PSM)
68
7.1.
Functional Description
69
7.2.
Registers
73
7.3.
Operation of Power Saving Module
75
7.4.
Operation of RTC Module
76
7.5.
Operation of Polling Module
77
7.6.
Operation of Port Wake Module
Contents, continued
Page
Section
Title
PRELIMINARY DATA SHEET
CDC 32xxG-C
Micronas
June 12, 2003; 6251-579-1PD
3
79
8.
JTAG Interface
79
8.1.
Functional Description
80
8.2.
Registers
80
8.3.
External Circuit Layout
80
8.4.
JTAG ID
83
9.
Embedded Trace Module (ETM)
83
9.1.
Functional Description
85
10.
Memory Patch Module V1.0
85
10.1.
Principle of operation
86
10.2.
Registers
87
11.
IRQ Interrupt Controller Unit (ICU)
87
11.1.
Functional Description
90
11.2.
Timing
90
11.3.
Registers
92
11.4.
Principle of Operation
92
11.5.
Application Hints
95
12.
FIQ Interrupt Logic
95
12.1.
Functional Description
95
12.2.
Registers
96
12.3.
Principle of Operation
97
13.
Port Interrupts
99
14.
Ports
99
14.1.
Analog Input Port
101
14.2.
Universal Ports U0 to U8
103
14.3.
Universal Port Registers
105
14.4.
High Current Ports H0 to H7
106
14.5.
High Current Port Registers
107
15.
AVDD Analog Section
108
15.1.
VREFINT Generator
108
15.2.
BVDD Regulator
108
15.3.
Wait Comparator
108
15.4.
P0.6 Comparator
109
15.5.
PLL/ERM
109
15.6.
A/D Converter (ADC)
111
15.7.
Registers
113
16.
Timers (TIMER)
113
16.1.
Timer T0
115
16.2.
Timer T1 to T4
117
17.
Pulse Width Modulator (PWM)
117
17.1.
Principle of Operation
CDC 32xxG-C
PRELIMINARY DATA SHEET
4
June 12, 2003; 6251-579-1PD
Micronas
Contents, continued
Page
Section
Title
118
17.2.
Registers
121
18.
Pulse Frequency Modulator (PFM)
121
18.1.
Principle of Operation
122
18.2.
Registers
123
19.
Capture Compare Module (CAPCOM)
125
19.1.
Principle of Operation
127
19.2.
Registers
129
20.
Stepper Motor Module SV (SMV)
129
20.1.
Principle of Operation
133
20.2.
Registers
134
20.3.
Timing
135
21.
LCD Module
135
21.1.
Principle of Operation
138
21.2.
Registers
138
21.3.
Application Hints for Cascading LCD Modules
139
22.
DMA Controller
139
22.1.
Functions
141
22.2.
Registers
142
22.3.
Principle of Operation
144
22.4.
Timing Diagrams
147
23.
Graphic Bus Interface
147
23.1.
Functions
147
23.2.
GB Registers
148
23.3.
Principle of Operation
151
24.
Serial Synchronous Peripheral Interface (SPI)
152
24.1.
Principle of Operation
153
24.2.
Registers
154
24.3.
Timing
155
25.
Universal Asynchronous Receiver Transmitter (UART)
156
25.1.
Principle of Operation
158
25.2.
Timing
160
25.3.
Registers
163
26.
I2C-Bus Master Interface
164
26.1.
Principle of Operation
166
26.2.
Registers
169
27.
CAN Manual
170
27.1.
Abbreviations
170
27.2.
Functional Description
176
27.3.
Application Notes
Contents, continued
Page
Section
Title
PRELIMINARY DATA SHEET
CDC 32xxG-C
Micronas
June 12, 2003; 6251-579-1PD
5
182
27.4.
Bit Timing Logic
183
27.5.
Bus Coupling
185
28.
DIGITbus System Description
185
28.1.
Bus Signal and Protocol
185
28.2.
Other Features
186
28.3.
Standard Functions
187
28.4.
Optional Functions
189
29.
DIGITbus Master Module
189
29.1.
Context
190
29.2.
Functional Description
192
29.3.
Registers
195
29.4.
Principle of Operation
198
29.5.
Timings
199
30.
Audio Module (AM)
200
30.1.
Functional Description
204
30.2.
Registers
205
31.
Hardware Options
205
31.1.
Functional Description
205
31.2.
Listing of Dedicated Addresses of the Hardware Options Field
206
31.3.
HW Options Registers and Code
211
32.
Register Cross Reference Table
211
32.1.
8-Bit I/O Region
217
32.2.
32-Bit I/O Region
219
33.
Register Quick Reference
245
34.
Control Register and Memory Interface
245
34.1.
Control Register CR
248
34.2.
Memory Clock Delay Lines
249
34.3.
External Memory Interface
255
35.
Differences
258
36.
Data Sheet History
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