CIP 3250A

ADVANCE INFORMATION

Micronas

Contents

Page

Section

Title

Introduction

1.1.

Block Diagram

1.2.

System Configurations

Functional Description

2.1.

Analog Front End

2.2.

Clamping

2.3.

Matrix

2.4.

YUV Control (on RGB-path only)

2.5.

Delay Adjustment

2.6.

Skew Filter

2.7.

Fast Blank Processing

2.7.1.

Soft Mixer

2.7.2.

Fast Blank Monitor

2.8.

FSY Front Sync and AVI Active Video In

2.9.

Digital Input Formats

2.9.1.

The Chroma Demultiplexers

2.10.

YUVin Interpolator (LPF 4:4:4)

2.11.

YUV Output Low-pass Filter 4:2:2 and 4:1:1

2.12.

Selectable RGB/YUV Output Formats

2.12.1.

DIGIT 2000 4:1:1 Output Format

2.12.2.

DIGIT 2000 4:2:2 Output Format

2.12.3.

DIGIT 3000 Orthogonal 4:2:2 Output Format

2.12.4.

Orthogonal 4:1:1 Output Format

2.12.5.

YUV Output Levels

2.13.

I/O Code Levels

2.14.

AVO Active Video Output

2.15.

PRIO Interface

2.16.

C Serial Bus Control

Specifications

3.1.

Outline Dimensions

3.2.

Pin Connections and Short Descriptions

3.3.

Pin Descriptions

3.4.

Pin Configuration

3.5.

Pin Circuits

3.6.

Electrical Characteristics

3.6.1.

Absolute Maximum Ratings

3.6.2.

Recommended Operating Conditions

3.6.3.

Characteristics

3.6.3.1.

Characteristics Standby Input

3.6.3.2.

Characteristics Test Input

3.6.3.3.

Characteristics Reset Input

3.6.3.4.

Characteristics Main Clock Input

3.6.3.5.

Characteristics Active Video Output

3.6.3.6.

Characteristics Active Video Input

3.6.3.7.

Characteristics Fsync Input

3.6.3.8.

Characteristics I

C Bus Interface Input/Output

3.6.3.9.

Characteristics Luma/Chroma Input

ADVANCE INFORMATION

CIP 3250A

Micronas

Component Interface Processor

Release Notes: Revision bars indicate significant
changes to the previous edition.

1. Introduction

The CIP 3250A is a new CMOS IC that contains on a
single chip the entire circuitry to interface analog YUV/
RGB/Fast Blank to a digital YUV system. The Fast Blank
signal is used to control a soft mixer between the digi-
tized RGB and an external digital YUV source. The CIP
supports various output formats such as YUV
4:1:1/4:2:2 or RGB 4:4:4.

Together with the DIGIT 3000 (e.g. VPC 32xxA) or DIGIT
2000 (e.g. DTI 2250), an interface to a TV-scanrate con-
version circuit and/or multi-media frame buffer can be
obtained.

1.1. Block Diagram

The CIP 3250A contains the following main functional
blocks (see Fig.1�1):

� analog input for RGB or YUV and Fast Blank

� triple 8 bit analog to digital converters for RGB/YUV

with internal programmable clamping

� single 6 bit analog to digital converter for Fast Blank

signal

� digital matrix RGB

YUV (Y, B�Y, R�Y)

� luma contrast and brightness correction for signals

from analog input

� color saturation and hue correction for signals from

analog input

� digital input for DIGIT 2000 or DIGIT 3000 formats

� digital interpolation to 4:4:4 format

� high quality soft mixer controlled by Fast Blank signal

� programmable delays to match digital YUVin and ana-

log RGB/YUV

� variable low pass filters for YUV output

� digital output in DIGIT 2000 and DIGIT 3000 formats,

as well as RGB 4:4:4

� I

C bus interface

� clock frequency 13.5 ... 20.25 MHz

1.2. System Configurations

The following figures, 1�2 and 1�3, show different basic
system applications for the CIP 3250A in the DIGIT 3000
environment. Beyond that, a stand alone application
(figure 1�4) also shows the flexibility of the CIP 3250A
in implementing simple analog video interfaces to digital
standards.

YUV 4:1:1

YUV 4:2:2

R/V

MATRIX

I2C

interface

G/Y

B/U

FSY

interface

clock

buffer

FSY

CLK

I2C

Bus

FBL

ADC

Format

4:4:4

CT
BR

SAT

SOFT

MIXER

Adjustable

LPF

YUV 4:1:1

YUV 4:2:2

RGB 4:4:4

Fig. 1�1: Block diagram of the CIP 3250A Component Interface Processor

Conversion

(4:4:4)

(on/off)

Format

Conversion

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2. Functional Description

This section describes the functionality of the various
blocks shown in the block diagram of Fig. 2�1 in detail.
The CIP 3250A is controlled via an I

C bus interface. For

information regarding how to program the registers of
the CIP 3250A, please refer to the register list (see
Tables 2�9 and 2�10). The I

C bus interface uses sub-

addressing to access the register. In the following, I

registers are referenced by the sub-addresses given in
parenthesis; for example, I

C register <9>. To interface

correctly, a pin description for the CIP 3250A is given in
section 3.3.

2.1. Analog Front End

� SCART-level inputs (RGB/YUV and

Fast Blank = 1.0 Vpp, Fast Blank must be ext. clipped)

� triple 8-bit ADC for RGB/YUV

� 6 bit ADC for Fast Blank

� sampling rate 13.5 to 20.25 MHz

� no sync separation included

All analog video input signals and the analog Fast Blank
signal must be band limited to 5 MHz before analog to
digital conversion.

The CIP 3250A can process either analog YUV input
signals or analog RGB input signals which are AC-
coupled with a nominal input voltage level of 700 mV +
3 dB (1 V

). There is no circuitry implemented for inter-

nal sync separation. Input voltage range of the Fast
Blank signal is 0 to 1 V. The Fast Blank input signal is
DC-coupled.

2.2. Clamping

� internal clamping for RGB and YUV with adjustable

start and width

� black level reference only during horizontal and verti-

cal blanking interval on RGB/YUV inputs

� no proper clamping if sync is on G

In RGB mode, clamping takes place on black level (digi-
tal 16 or 8) using a clamping window as described below.
In YUV mode, clamping is done on black level (digital 16)
for Y (luma) and on saturation level zero (digital 128) for
UV (chroma) using a clamping window. Select between
RGB mode and YUV mode via I

C register <09>YUV.

The black level reference value (digital 16 or 8) can be
selected via I

C register <09>CLMPOFS. In a standard

DIGIT 2000 application without a conversion of Y (luma)
to ITUR code levels at the digital inputs (see section 2.9.
<10>YLEVEL), convert the black level to digital 32 via
I

C register <04>CLSEL.

The clamping window is programmable in reference to
the H-sync signal (see Fig. 2�13) by a start and stop val-

ue via I

C registers <18> and <19>. A window size of 32

or 64 sample clocks is recommended. Clamping is dis-
abled if start and stop values are equal after reset. Once
enabled it can not be switched off. Using a coupling ca-
pacitor of 220 nF, a hum of approximately 400 mV at
50 Hz can be compensated.

2.3. Matrix

� matrix RGB

Y(R�Y)(B�Y):

Y = 0.299*R + 0.587*G + 0.114*B
(R�Y) = 0.701*R � 0.587*G � 0.114*B
(B�Y) = �0.299*R � 0.587*G + 0.886*B

� fixed coefficients with a resolution of 8 bits.

� matrix enable/disable for analog RGB/YUV input pro-

grammable via I

C register

The matrix of the CIP 3250A converts the digitized RGB
signals to the intermediate signals Y, R�Y, and B�Y. En-
able the matrix via I

C register <04>MAON. The inter-

mediate signals at the output of the matrix can be con-
verted to YUV signals of the DIGIT 2000 system or to
YC

of the DIGIT 3000 system by the YUV control (see

section 2.4.). To omit conversion from RGB to
Y(R�Y)(B�Y), switch off the matrix and the CTBRST
block via I

C register <04>MAON and <04>CBSON.

2.4. YUV Control (on RGB-path only )

� Y contrast (ct) and brightness (br) with rounding or

noise shaping and limiting to 8 bit:
Y = Y*ct + br
ct = 0 ... 63/32 in 64 steps
br = �128 ... +127 in 256 steps

� UV saturation (sat) with rounding or noise shaping and

limiting to 8 bit (controllable by CCU via I

C bus):

EXT

= (B�Y) * Usat

EXT

= (R�Y) * Vsat

Usat,Vsat = 0 ... 63/32 in 64 steps
(U

INT

= [0.5*(B�Y)] * Usat

INT

= [0.875*(R�Y)] * Vsat)

Within the CTBRST block, switched on via I

C register

<04>CBSON, two different options can be used to con-
vert from (R�Y)(B�Y) to UV (PAL standard). In internal
mode (UV

INT

), conversion to PAL standard is done be-

fore the multiplication of the contents of the saturation
registers. Using the external mode (UV

EXT

) of

<04>SMODE, the user has to implement the conversion
factors via the two saturation registers (Usat, Vsat).
Since the two saturation registers can be programmed
separately, it is also very easy to convert to YC

(Stu-

dio standard) of the DIGIT 3000 system.

Contrast, brightness, and saturation can be adjusted for
the video signals of the analog input via I

C registers

<00> to <03>. A functional description of this circuit can
be found in figures 2�2 and 2�3 respectively.

To improve the amplitude resolution of the luma (Y) and
chroma (UV) video signals after multiplication with the

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weighting factors (ct) and (sat), the user can select be-
tween rounding and two different modes of noise shap-
ing (1 bit error diffusion or 2 bit error diffusion).

Rounding

1 bit

Err. Diff.

2 bit

Err. Diff.

255

Select

C Registers

Fig. 2�2: Luma Contrast & Brightness Adjustment

Rounding

1 bit

Err. Diff.

2 bit

Err. Diff.

sat

127

�128

Select

C Registers

Fig. 2�3: Chroma Saturation Adjustment

B�Y

R�Y

2.5. Delay Adjustment

� DL1 to compensate internal processing delay of the

CIP 3250A in reference to digital YUVin

� DL1 to compensate processing delay of the DIGIT

2000 SPU chroma channel in SECAM mode

� DL2 to compensate delay between digital YUVin and

analog RGBin or FSY; as for example, produced by
ACVP or SPU.

To mix the analog RGB/YUV input signals and the digital
YUVin input signals at the soft mixer correctly, in refer-
ence to the horizontal synchronization pulse, two pro-
cessing delay adjustments can be made. In many sys-
tem applications, ICs in front of the CIP 3250A cause a
fixed processing delay in the digital YUVin path. There-
fore, a delay of up to 210 sample clocks can be pro-
grammed via I

C register <21>DL2 to match analog

RGB/YUV data with digital YUV data . If the delay is less
than 48 sample clocks, the DL1 block can be activated
(80 sample clocks) via I

C register <10>DL1ON to get

a value for <21>DL2 within the range of 48 to 210.

In applications where there will be no fixed delay be-
tween digital YUVin and analog RGB/YUV, the pixel
skew correction can be switched on via I

C register

<17>PXSKWON. In this mode, the DL2 block serves as
a variable delay to match the analog RGB/YUV data with
digital YUV data. The first pixel of analog RGB/YUV writ-
ten into the DL2 block (which works like a FIFO) is se-
lected by <21>DL2. Read of the DL2 block starts syn-
chronously with the AVI input, which in turn marks the
first pixel in digital YUV data (see Fig. 2�14). Care must
be taken that the number of pixels stored in DL2 block
must be within the limits of 48 to 210.

In case of SECAM processing in the DIGIT 2000 envi-
ronment, the digital luma and chroma signals do not
match in front of the CIP 3250A. Therefore, the I

C regis-

ter <10>SECAM must be enabled, and fine adjustment
has to be carried out within the ACVP.

2.6. Skew Filter

Two interpolation filters perform data orthogonalization
(= skew correction) for luma and chroma in case of a
non-line-locked system clock. The skew value is serially
input via the FSY input. In a system environment where
digital YUV data are orthogonal (e.g. DIGIT 3000), the
skew correction must be set to DIGIT 3000 mode via I

register <04>SKWCBS in order to apply skew correction
to analog RGB/YUV data only. Additionally, the skew
correction must be switched on via I

C register

<04>SKWON. This has to be done in order to mix the
analog input with the digital YUV input correctly and to
output the mixed YUV signal in an orthogonal format.

For standard DIGIT 2000 operation, the skew correction
should be switched off via I

C register <04>SKWON, in

order to output the mixed YUV data with the same skew
values as the digital YUV input. Only in special applica-
tions (e.g. multi media), where the output connects to a
field or frame memory which processes orthogonal data,
the skew correction for mixed YUV data has to be
switched on and set to DIGIT 2000 mode via I

C register

<04>SKWCBS.

2.7. Fast Blank Processing

� mixing of RGB-path and YUV-path in YUV 4:4:4 format

controlled by the Fast Blank signal

� linear or nonlinear mixing technique selectable

� programmable polarity of Fast Blank signal

� programmable step response of Fast Blank signal

� RGB-path or YUV-path can be statically selected

� Fast Blank signal monitoring

2.7.1. Soft Mixer

In the Fast Blank signal path, special hardware is sup-
plied to improve edge effects, such as blurring because
of band limiting in the analog front end. Different step re-
sponses are user selectable via I

C register <12>MIX-

AMP, still obtaining high quality phase resolution. Also,

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the polarity of the Fast Blank signal can be changed via
I

C register <12>MIXAMP. The I

C register

<11>FBLOFF influences the phase delay between the
RGB path and the Fast Blank signal (see Fig. 2�4).

Additionally, a delay of �1 to 2 clocks between the Fast
Blank signal and the RGB-path is programmable via I

register <16>FBLDEL. By selecting a positive delay,
shadowing of characters can be obtained, if the back-
ground color of the RGB-path is set to black.

With the built-in linear mixer, the CIP 3250A is able to
support simple AB roll techniques between analog input
(A) and digital YUV input (B):

VideoOut = A * (1 � FBLMIX/32) + B * FBLMIX/32,

controllable via the Fast Blank signal (FBL):

FBLMIX = INT[(FBL � FBLOFF)* MIXAMP/2] + 16,

with FBL of values from 0 to 63. The mixing coefficient
FBLMIX resolves 32 steps within the range from 0 to 32
(dependent on step response chosen via I

C register

<12>MIXAMP) (see Fig. 2�4).

When the I

C register bit <16>FBLCLP is enabled, the

soft mixer operates independently of the analog Fast
Blank input. FBL is clamped to digital 31 (see Fig. 2�4).
Mixing between RGB-path and YUV-path is controllable
via the I

C register <11>FBLOFF.

fbloff

mixamp

C Registers

Fig. 2�4: Fast Blank Processing

FBLMIX

1/2

FBL (0...63)

fblclp

0
1

Select the linear mixer or the nonlinear mixer via I

C reg-

ister <12>SELLIN. If the nonlinear mixer is selected, a
dynamic delay control of the analog RGB/YUV input can
be chosen, to avoid edge artefacts of the RGB/YUV sig-
nal (e.g. shading), during transition time of Fast Blank
signal with the I

C register <12>CTRLDLY.

In some applications, it is desired to disable the control
by the Fast Blank signal and to pass through the digital
YUVin path or the analog RGB/YUV path. This is pos-
sible by adequately programming the I

C registers

<06>PASSYUV and <11>PASSRGB (Table 2�1).

Table 2�1: Source selection of soft mixer

<11>
PASSRGB

<06>
PASSYUV

Fast Blank
signal

Source

RGB

MIX

YUV/RGB

YUV

X: don't care

2.7.2. Fast Blank Monitor

Bits 0 to 3 of I

C register <27> are monitoring the analog

Fast Blank input. Reading I

C register <27> Fig. 2�5 dis-

plays the contents depending on the analog FBL input
signal.

Fig. 2�5: Fast Blank Monitor

analog fast
blank input

<27>FBLSTAT

<27>FBLRISE

<27>FBLFALL

<27>FBLHIGH

reading I

2.8. FSY Front Sync and AVI Active Video In

� DIGIT 2000 chroma sync detection

� DIGIT 2000 throughput of 72-bit data and clock

� skew data input for DIGIT 2000

� skew data input for DIGIT 3000

� HSYNC as timing reference for clamping pulse gener-

ator

� active video input to indicate valid video data and to

synchronize chroma multiplex for DIGIT 3000

The FSY input and the AVI input are used to supply all
synchronization information necessary. Three basic
modes of operation can be selected via I

C registers

<06>D2KIN, <17>D2KSYNC, <17>SYNCSIM, and
<17>P72BEN.

In a DIGIT 2000 system environment, the CIP 3250A re-
ceives the synchronization information at the FSY input
via the DIGIT 2000 SKEW-protocol. The AVI Input may
be connected to ground GND or VDD (see section
2.14.).

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(not in scale)

input

analog

video

Skew

V: Vert.

sync

0 = off
1 = on

Fig. 2�6: DIGIT 2000 skew data

skew

MSB

skew

LSB

ig�

nored

ig�

nored

data

Bit:

In a DIGIT 3000 system environment, the CIP 3250A re-
ceives the synchronization information at the FSY input
via the DIGIT 3000 FSY-protocol (see Fig. 2�7). The AVI
input receives the chroma multiplex information implicit-
ly with the rising edge of the AVI signal.

(not in scale)

input

analog

video

FSY

Parity

V: Vert.

sync

0 = off
1 = on

Fig. 2�7: DIGIT 3000 front sync format

skew

MSB

skew

LSB

ig�

nored

F0, F2 ... F5: reserved

ig�

nored

In a stand alone application, for example, RGB-analog-
to-digital conversion, a horizontal sync pulse must serve
the FSY input, and a vertical sync pulse must serve the
AVI input. The polarity of these two sync pulses can be
programmed via I

C registers <10>AVIINV and

<07>FSYINV.

Inside the CIP 3250A, synchronization information is be-
ing decoded and used to control clamping, DL2, skew fil-
ters, video control logic, input formatter, and output for-
matter as shown in Fig. 2�1.

2.9. Digital Input Formats

� YUV 4:2:2 (16 bit) from DIGIT 2000 and DIGIT 3000

(YUV as well as YCrCb)

� YUV 4:1:1 (12 bit) from DIGIT 2000

� input levels according to DIGIT 2000/DIGIT 3000

The CIP 3250A supports the YUV 4:1:1 (12 bit) standard
from DIGIT 2000, the YUV 4:2:2 (16 bit) standard from

DIGIT 2000, and the YUV 4:2:2 (16 bit) standard from
DIGIT 3000. Therefore, the CIP 3250A can be used in
either the DIGIT 2000 system environment or the DIGIT
3000 system environment. Refer to I

C registers

<06>DELAYU, <10>UVFRM3, and <10>UVFRM1 for a
correct setup. Additionally, within the DIGIT 2000 sys-
tem, a Y (luma) format conversion to ITU-R 601 can be
achieved via programming the I

C register <10>YLE-

VEL.

Table 2�2: Digital input selection

<06>
DELAYU

<11>
UVFRM3

<11>
UVFRM1

Digital
Input Format

DIGIT 2000 4:2:2

DIGIT 2000 4:1:1

DIGIT 3000 4:2:2

MAC

2.9.1. The Chroma Demultiplexers

In DIGIT 2000 mode, via pins 36 to 39, the CIP 3250A
receives the V and U signals from the C0 to C3 outputs
of the color decoder, time-multiplexed in 4-bit nibbles
(Fig. 2�8). For the digital signal processing, the 4-bit V
and U chroma nibbles are demultiplexed to 8-bit signals
by the V and U demultiplexers. Both demultiplexers are
clocked by the main clock. They are synchronized to the
V and U transmission during the vertical blanking period.

Fig. 2�8: Timing diagram of the multiplexed color dif-
ference signal transfer between decoder and CIP
3250A

four clock periods

U MSB

V LSB

V MSB

U LSB

U MSB

Notes to Fig. 2�8:

a) CLK main clock signal

b) Multiplexed color difference signals from PVPU/

ACVP/SPU/VSP/DMA to DTI 2260

c) Sync pulse on C0 output during sync time in vertical

blanking interval.

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2.10. YUVin Interpolator (LPF 4:4:4)

� UV-Interpolation 4:1:1 or 4:2:2

4:4:4

In order to mix the digital input data with the 4:4:4 video
standard from the analog RGB/YUV input, correctly, the
chroma samples of the digital input have to be interpo-
lated.

In case of YUV 4:1:1 input from DIGIT 2000, a two stage
interpolation filter is implemented. In the first stage, an
interpolation filter is used, which converts the YUV 4:1:1
standard into the YUV 4:2:2 standard.

In the second stage, the interpolation is from the YUV
4:2:2 to YUV 4:4:4.

In the case of YUV 4:2:2 input, only the second stage is
necessary.

Refer to I

C registers <06>DELAYU, <10>UVFRM3,

and <10>UVFRM1 to choose the correct interpolation
filters (see Fig. 2�2).

2.11. YUV Output Low-pass Filter 4:2:2 and 4:1:1

� Y low-pass filter with 7 selectable cutoff frequencies

� UV low-pass decimation filter 4:4:4

4:2:2/4:1:1 with

5 selectable cutoff frequencies

To meet the bandwidth requirements of different video
standards, such as 4:2:2 or 4:1:1 at various sampling
frequencies, the luma signal (Y) and the chroma signal
(UV) can be lowpass filtered. There are 7 different cutoff
frequencies selectable for luma, via I

C register

<05>LPFLUM and 5 different cutoff frequencies select-
able for chroma, via I

C register <07>LPFCHR. The

spectra of the luminance filters are shown in Fig. 2�9,
and the spectra of the chrominance filters are shown in
Fig. 2�10.

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2.12. Selectable RGB/YUV Output Formats

� RGB, 8-bit pure binary (24 bit)

� YUV 4:2:2 (16 bit) for DIGIT 2000, DIGIT 3000, and

Philips/Siemens

� YUV 4:1:1 (12 bit) for DIGIT 2000 and Philips/Siemens

� UV format selectable between 2's complement and

binary offset

In a first stand alone application, the CIP 3250A can
serve as a RGB video analog-to-digital converter to out-
put digital R, G, and B in a pure binary format, 8 bits pure
binary per channel, and a sampling rate between 13.5
MHz and 20.25 MHz.

In a second stand alone application, the CIP 3250A can
serve as a YUV or RGB (with the matrix switched on) vid-
eo analog-to-digital converter to output digital YUV, sup-
porting various formats such as YUV 4:1:1 (12 bit) from
DIGIT 2000 and Philips, YUV 4:2:2 (16 bit) from DIGIT
2000 and DIGIT 3000, or YUV 4:2:2 (16 bit) industry
standard. Additionally, the signed format of the UV sig-
nal is programmable between 2's complement and
binary offset. A sampling rate between 13.5 MHz and
20.25 MHz can be selected, and the YUV output data
can be low pass filtered.

In a DIGIT 2000 environment, the CIP 3250A can pro-
cess either RGB or YUV signals from the analog Input,
mix it with the digital YUV Input data � controlled by the
Fast Blank input, and generate low pass filtered output
data in the YUV 4:1:1 (12 bit) DIGIT 2000 format. A sam-
pling rate locked to the color subcarrier frequency (4*fsc)
for the NTSC or PAL video standard has to be used.

In a DIGIT 3000 environment, the CIP 3250A can pro-
cess either RGB or YUV signals from the analog input,
mix it with the digital YUV input data � controlled by the
Fast Blank input, and generate low pass filtered output
data in the YUV 4:2:2 (16 bit) DIGIT 3000 format. Addi-
tionally, the signed format of the UV signal is program-
mable between 2's complement and binary offset. The
sampling rate is derived from the VPC 320x and ranges
from 13.5 to 20.25 MHz for all of the video standards.

The U and V chrominance samples are transmitted in
multiplex operation. Depending on the application, the
CIP 3250A provides the following different output for-
mats of the YUV signals (selectable via I

C-Bus):

� 4:1:1 orthogonal output format for DIGIT 3000 applica-

tions

� 4:2:2 orthogonal output format for DIGIT 3000 applica-

tions

� 4:1:1 output format for standard DIGIT 2000 applica-

tions

� 4:2:2 output format for DIGIT 2000 applications

Refer to I

C registers <15> to <16> to select the desired

output format. Additionally, the CIP 3250A provides con-
version of ITURY (luma) to DIGIT 2000 Y (luma) output
black levels, selectable via I

C register <16>ADD16Q.

A programmable two-dimensional active video signal
(AVO) allows the write control of external video memory
directly. The characteristic of the YUV output is select-
able between open-drain or push-pull.

Table 2�3: Digital output selection

<15>
YUVO

<15>
MOD411ON

<15>
IND

<15>
UVSW

<15>
DTI

Digital
Output Format

DIGIT 2000 4:1:1

orthogonal 4:1:1

DIGIT 2000 4:2:2

DIGIT 3000 4:2:2

4:4:4

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2.12.1. DIGIT 2000 4:1:1 Output Format

The DIGIT 2000 4:1:1 output format is shown in Tables
2�4 and 2�5. A control signal for the chroma multiplex
is transmitted during the vertical blanking interval (see
Section 2.9.1.).

Table 2�4: Bit map of DIGIT 2000 4:1:1 format

Luma
Chroma

, C

Note: U

x = pixel number and y = bit number

Table 2�5: Sampling raster of DIGIT 2000 4:1:1 format

Luma
Chroma

line 1

line 2

line 3

line 4

line 5

Note: U

x = pixel number and y = LSB/MSB nibble

pixel no. X indicates an invalid sample at the
beginning of the line

2.12.2. DIGIT 2000 4:2:2 Output Format

In the DIGIT 2000 4:2:2 output format, the U and V sam-
ples are non-orthogonal (calculated from adjacent pixel,
e.g. line n starts with a V pixel and line (n+1) starts with
a U pixel (see Table 2�6).

Table 2�6: DIGIT 2000 4:2:2 output format

Luma
Chroma

Note: U

x = pixel number and y = bit number

2.12.3. DIGIT 3000 Orthogonal 4:2:2 Output Format

The DIGIT 3000 orthogonal 4:2:2 output format is com-
patible to the industry standard. The U and V samples
are skew corrected and interpolated to an orthogonal
sampling raster, e.g. every line starts with the current U
pixel (see Table 2�7).

Table 2�7: Orthogonal 4:2:2 output format

Luma
Chroma

Note: U

x = pixel number and y = bit number

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2.12.4. Orthogonal 4:1:1 Output Format

The orthogonal 4:1:1 output format is compatible to the
industry standard. The U and V samples are skew cor-
rected and interpolated to an orthogonal sampling raster
(see Table 2�8).

Table 2�8: 4:1:1 orthogonal output format

Luma
Chroma

, C

Note: U

x = pixel number and y = bit number

2.12.5. YUV Output Levels

The Y output black level of the CIP 3250A can be con-
verted from ITU-R 601 Standard (digital 16) to DIGIT
2000 Standard (digital 32) via I

C register

<16>ADD16Q.

2.13. I/O Code Levels

� ITU-R/DIGIT 3000 code levels:

Y or RGB = 16 ... 240, clamp level = 16
UV =

�

112, bias level = 0

� or DIGIT 2000 code levels:

Y = 32 ... 127, clamp level = 32
UV =

�

127, bias level = 0

2.14. AVO Active Video Output

In a DIGIT 3000 system environment, the AVO signal is
equivalent to the delayed AVI signal. It signalizes valid
video data and chroma multiplex at the output of the
CIP 3250A. Furthermore, the AVO signal can be used to
control the write enable of a frame memory. The polarity
of the AVO signal is programmable via I

C register

<10>AVOINV.

In a DIGIT 2000 system environment, the AVO signal
can be programmed via I

C registers <23> to <26> to

define a window of valid video data at the output of the
CIP 3250A (see Fig. 2�11).

AVO

Fig. 2�11: Programmable AVO signal

<23>AVHSTRT

<24>AVHLEN

<26>AVVSTOP

<25>AVVSTRT

start of field

Select the desired mode via I

C register <17>AVINT. If

the AVO signal is derived from the AVI signal, the I

registers <22>AVDLY can be used to compensate inter-
nal processing delays of the CIP 3250A.

C register <22>AVPR can be used to precede the AVO

signal in relation to the RGB/YUV data output up to 3
clocks.

2.15. PRIO Interface

� real-time bus arbitration for 8 sources in DIGIT 3000

picture bus.

Up to eight digital YUV or RGB sources (main decoder,
PIP, OSD, Text, etc.) may be selected in real-time by
means of a 3 bit priority bus. Thus, a pixelwise bus arbi-
tration and source switching is possible. It is essential
that all YUV-sources are synchronous and orthogonal.

In general, each source (= master) has its own YUV bus
request. This bus request may either be software or
hardware controlled, i.e. a fast blank signal. Data colli-
sion is avoided by a bus arbiter that provides the individ-
ual bus acknowledge, in accordance to a user defined
priority.

Each master sends a bus request with its individual
priority ID onto the PRIO-bus and immediately reads
back the bus status. Only in case of positive arbitration
(send-PRIO-ID = read-PRIO-ID), the RGB/YUV outputs
become active and the data is send. PRIO requests
must be enabled by I

C register <14>PRIOEN.

The requests asserted by the CIP 3250A may be gener-
ated by two different sources, which are selectable by
I

C register <09>PRIOSRC. With the first source, the

CIP 3250A asserts requests only when the AVO signal
is active, else RGB/YUV outputs are tristated. With the
second source, the CIP 3250A asserts continuous re-
quests where the YUV data are forced to "clamp/bias
level data" (see section 2.13.) during the time that the
AVO signal is inactive.

If only one source is connected to the YUV bus, the out-
puts GL, RC, and B may drive the bus during a full clock
cycle. This can be selected by I

C register <06>HALF-

OUT. If more than one source is connected to the YUV
bus, the output drivers must be switched to driving only
during the first half of clock cycle to avoid bus collision.
In the last case, the layout of the PCB must consider that

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CIP 3250A

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data on YUV bus must be kept dynamically for a half
clock cycle. Thus, capactitvie coupling from other sig-
nals to YUV bus must be avoided or reduced to a toler-
able minimum.

This procedure has many features which have an impact
on the appearance of a TV picture:

� real-time bus arbitration (PIP, OSD, ...)

� priorities are software configurable

� different coefficients for different sources

2.16. I

C Serial Bus Control

Communication between the CIP 3250A and the exter-
nal controller is done via I

C bus. The CIP 3250A has an

C bus slave interface and uses I

C clock synchroniza-

tion to slow down the interface if required. The I

C bus

interface uses one level of subaddressing: one I

C bus

address is used to address the IC and a subaddress se-
lects one of the internal registers.

The registers of the CIP 3250A have 8 bit data size. All
registers are writeable (except subaddress hex27) and
readable as well. Register bits of parameter addresses,
which are marked with an X in the description field of the
register table, must be set to zero. All registers are initial-
ized to zero with reset.

Figure 2�12 shows I

C bus protocols for read and write

operations of the interface.

1 byte Data

Ack

0111 1100

Ack

SDA

SCL

1 byte Data

Ack

Nak

= Start

Stop

Device Address = 110 1110[R/W]

Nak

Fig. 2�12: I

C Bus Protocol

1101110

C write access

C read access

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CIP 3250A

Micronas

Table 2�9: The I

C-bus addresses of the CIP 3250A � Device Address: 6E Hex (7 bit, R/W bit omitted, see Sec. 2.16.)

MIXAMP

amplification of Fast Blank amplitude

MSB

LSB

Bit
No.

Sub.

Addr.

NOISSU

noise shaping of U

�

SATU

saturation multiplier of U

NOISSV

noise shaping of V

�

SATV

saturation multiplier of V

NOISSY

noise shaping of Y

�

SATY

contrast multiplier of Y

BRY

brightness correction of Y

CBSON

CTBRST block

enable

MAON

matrix block

enable

SKWON

skew correction

�

enable

SMODE

saturation mode

CLSEL

clamping offset for Y

SKWCBS

skew filter mode

�

ATST

testbits

LPFLUM

luma low pass filter selection

�

PASSYUV

soft mixer control

D2KIN

input amplifier of

�

digital YUVin

DELAYU

UV format of YUVin

�

HALFOUT

output drive

CYLUM1

Y low pass filter

�

offset correction 1

CYLUM2

Y low pass filter

�

offset correction 2

CYCHR1

UV low pass filter

�

offset correction 1

CYCHR2

UV low pass filter

�

offset correction 2

LPFCHR

chroma low pass filter selection

�

TESTCLP

test clamping

YUV

analog input select

SE_4_8Q

analog gain control

SELAMP

analog gain control

CLMPOFS

RGB clamping offset

AVODIS

disable ACVOUT

�

DL1ON

delay of YUVin

UVBINCON

UV sign of YUVin

UVFRM3

UV format of YUVin

UVFRM1

UV format of YUVin

YLEVEL

convert Y format

�

SELDLY

adjust delay of RGB/YUV-path

SELLIN

select soft mixer

CTRLDLY

delay control

FBLOFF

Fast Blank offset correction

FBLTEN

Fast Blank test

PASSRGB

soft mixer control

OVR

override value for PRIO-interface

�

PRIOID

set PRIO priority

�

PRIOEN

access to Picture Bus

LOAD

adjust load strength of

�

Picture Bus and PRIO bus

PUDIS

disable pull up

�

of YUV/RBG output

UVSW

UV multiplex of

�

YUV output

BINO

UV sign of

�

output format

YUVO

select RGB/YUV

�

output format

DTI

UV output format

�

IND

UV output format

�

MOD411ON

UV output format

�

CDEL

select UV output sample from 4:4:4

�

YDEL

adjust Y output delay

�

ADD16Q

black level

�

of Y output

DL422Y

additional

�

Y output delay

DL422C

additional

�

UV output delay

SYNCIN

UV sync control

�

of YUVin

SYNCOUT

UV sync control

�

of YUV output

SYNCSIM

H-sync, V-sync

�

input

D2KSYNC

sync input at

�

FSY-pin

�

AVINT

AVO control

�

PXSKWON

pixel skew corretion

�

P72BEN

72 bit data bypass

�

SECAM

delay for SECAM

FBLCLP

static Fast Blank

FBLDEL

delay Fast Blank vs. analog RGB/YUV

FSYINV

polarity FSY

AVOINV

polarity AVO

AVIINV

polarity AVI

�

NEGCLK

select active

clockedge

TESTLUY

test y channel

TESTCHU

test u channel

TESTCHV

test v channel

TESTFBL

test fbl channel

ICLPTST

test fbl clamp

duration

and IDDQ test

PRIOSRC

Source for

PRIO request

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CIP 3250A

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Table 2�10: I

C-Bus operation � Device Address: 6E Hex (7 bit, R/W bit omitted, see Sec. 2.16.)

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for ADC and CLAMPING

YUV

analog input select
0 = RGB
1 = YUV

CLPSTRT

7�0

start of clamping window
(0...255)*2 clocks after H-sync (see Fig. 2�13)

CLPSTOP

7�0

stop of clamping window
(0...255)*2 clocks after H-sync (see Fig. 2�13)

[note:

� maximum window size: 64 sample clocks]

[

� minimum window size: 6 sample clocks]

CLMPOFS

RGB clamping offset
0 = +16 (digital)
1 = +8 (digital)

CLSEL

Y (luma) black level adjust at RGB-path
0 =convert Y (luma) black level from digital 16 to 32 (DIGIT 2000)
1 =Y (luma) black level at digital 16 (ITU-R 601 Standard)

SELAMP

4�3

analog gain control
0 = 1/8
1 = 1/16
2 = 1/32

SE_4_8Q

analog gain control
0 = 1/8
1 = 1/4

C registers for MATRIX

MAON

matrix block
0 = matrix off (YUV input or RGB bypass)
1 = matrix on (RGB to Y(R�Y)(B�Y))

C registers for CONTRAST / BRIGHTNESS / SATURATION

CBSON

CTBRST block
0 = bypassed ( for dig. RGB bypass only (<04>MAON=0))
1 = on

BRY

7�0

brightness correction of Y (luma) in CTBRST block
Y + (�128...127)

SATY

5�0

contrast multiplier of Y (luma) in CTBRST block
Y * (0...63)/32

NOISSY

7,6

noise shaping of Y (luma) in CTBRST block
0 = off (rounding is activated)
2 = 1 bit error diffusion
3 = 2 bit error diffusion

SATU

5�0

saturation multiplier of U (chroma) in CTBRST block
U * (0...63)/32

NOISSU

7,6

noise shaping of U (chroma) in CTBRST block
0 = off (rounding is activated)
2 = 1 bit error diffusion
3 = 2 bit error diffusion

SATV

5�0

saturation multiplier of V (chroma) in CTBRST block
V * (0...63)/32

NOISSV

7,6

noise shaping of V (chroma) in CTBRST block
0 = off (rounding is activated)
2 = 1 bit error diffusion
3 = 2 bit error diffusion

SMODE

saturation mode of UV (chroma) in CTBRST block
0 = internal PAL (U * 0.5, V * 0.875)
1 = external (U * 1, V * 1)

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CIP 3250A

Micronas

Table 2�10: I

C-Bus operation, continued

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for OUTPUT FORMATTER

YUVO

select video component output format
0 = output formater off (i.e. RGB or YUV output with format 4:4:4)
1 = output formater on (i.e. YUV output with format 4:2:2 or 4:1:1)

ADD16Q

black level of Y (luma) output
0 = Convert Y black level at output from ITU-R 601 Standard
to DIGIT 2000 Standard (digital 32)
1 = Y black level at output unchanged

MOD411ON

UV (chroma) output format
0 = 4:2:2
1 = 4:1:1

BINO

UV (chroma) sign of output format
0 = two's complement
1 = binary offset

CDEL

1�0

select UV (chroma) output sample from 4:4:4 format
(0...3)

IND

UV (chroma) output format
0 = DIGIT 2000
1 = DIGIT 3000 / orthogonal

UVSW

UV (chroma) multiplex of output format
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1
1 = DIGIT 2000 4:2:2

DTI

UV (chroma) output format
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1
1 = DIGIT 2000 4:2:2

YDEL

4�3

adjust Y (luma) output delay in reference to UV (chroma) output
(0...3) clocks

DL422Y

additional Y (luma) output delay
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)

DL422C

additional UV (chroma) output delay
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)

C registers for SKEW FILTER

SKWON

skew correction
0 = off
1 = on

SKWCBS

skew filter active for
0 = DIGIT 2000 pixel orthogonalization
1 = DIGIT 3000 pixel orthogonalization

SKEWLAT

7�0

latch time for sub-pixel skew value (from FSY-/SKEW-protocol) to ad-
just the processing delays of video data to H-sync (see Fig. 2�13)
(0...255)*2 clocks

C registers for PRIO

PRIOEN

access to Picture Bus (GL, RC, B output)
0 = disabled (Picture Bus is tristate)
1 = enabled (access to Picture Bus possible)

PRIOSRC

Source for PRIO request
0 = PRIO request only if AVO is active
1 = PRIO request always independent of AVO

PRIOID

6�4

set PRIO priority
(0...7)

OVR

7�0

override value for PRIO-interface

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CIP 3250A

Micronas

Table 2�10: I

C-Bus operation, continued

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for SOFT MIX

PASSRGB

soft mixer control
0 = analog RGB/YUV-path passed only
1 = mixing controlled by Fast Blank (if <11>PASSYUV=0)

PASSYUV

soft mixer control
0 = mixing controlled by Fast Blank (if <11>PASSRGB=1)
1 = digital YUVin-path passed only (if <11>PASSRGB=1)

FBLCLP

enable static operation of Fast Blank
0 = Fast Blank derived from analog FBL input
1 = static Fast Blank (FBL = 31)

FBLOFF

5�0

Fast Blank offset correction
FBL � (0...63)

FBLDEL

6�5

delay Fast Blank vs. analog RGB/YUV input
3 = �1 clocks
0 = 0 clocks
1 = 1 clocks
2 = 2 clocks

MIXAMP

7�4

amplification of Fast Blank amplitude
FBL * (�4...4) [note: value 0 invalid, use <06>PASSYUV
or <11>PASSRGB for static operation of soft mixer instead]

CTRLDLY

delay control of analog RGB/YUV data in relation to
digital YUV data
0 = statically (by value of <12>SELDLY)
1 = dynamically (by nonlinear mixer)

SELDLY

3�2

delay value for analog RGB/YUV data in relation to
digital YUV data (<12>CTRLDLY=0)
0 = �1 pixel
1 = 0 pixel
2 = +1 pixel

SELLIN

select soft mixer type
0 = linear mixer
1 = nonlinear mixer

FBLSTAT

fast blank input : 1 = high, 0 = low (see Fig. 2�5)

FBLRISE

set with an rising edge at fast blank input
reset at read of <27>

FBLFALL

set with an falling edge at fast blank input
reset at read of <27>

FBLHIGH

dynamic FBL read high level

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CIP 3250A

Micronas

Table 2�10: I

C-Bus operation, continued

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for ACTIVE VIDEO SIGNAL

AVIINV

polarity of AVI signal
0 = active video during AVI is high (if <17>AVINT = 0)
1 = active video during AVI is low (if <17>AVINT = 0)

AVOINV

polarity of AVO signal
0 = AVO is high active
1 = AVO is low active

AVDLY

5�0

delay from AVI (active video in) to AVO to compensate CIP 3250A
processing delays (if <17>AVINT = 0)
(0...63) + 14 � <22>AVPR clocks (if <10>DL1ON=0)
(0...63) + 92 � <22>AVPR clocks (if <10>DL1ON=1)

AVPR

7�6

delay between AVO and YUV output
AVO preceedes YUV output by AVPR (0...3) clocks

AVINT

AVO (active video out)
0 = derived from AVI (active video in)
1 = generated internally (see <23>AVHSTRT, <24>AVHLEN,
<25>AVVSTRT, <26>AVVSTOP)

AVHSTRT

7�0

horizontal start of AVO after H-sync if <17>AVINT = 1
(0...255)*8 + 11 � <22>AVPR clocks (see Fig. 2�13)

AVHLEN

7�0

horizontal length of AVO if <17>AVINT = 1
(0...255)*8 clocks

AVVSTRT

7�0

vertical start of AVO if <17>AVINT = 1
(0...255)*4 lines

AVVSTOP

7�0

vertical stop of AVO if <17>AVINT = 1
(0...255)*4 lines

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CIP 3250A

Micronas

Table 2�10: I

C-Bus operation, continued

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for ADJUSTABLE LOWPASS FILTER

LPFLUM

7�0

Y luma low pass filter selection
0 = bypass
128 = Y1 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 1)

192 = Y2 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 1)

224 = Y3 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 2)

240 = Y4 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 2)

241 = Y5 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 2)

249 = Y6 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 2)

255 = Y7 (<06>CYLUM1=0, <06>CYLUM2=0,

increment <16>YDEL by 2)

[note: <16>YDEL has to be incremented to match group delays]

CYLUM1

Y (luma) low pass filter offset correction 1
0 = off
1 = on

CYLUM2

Y (luma) low pass filter offset correction 2
0 = off
1 = on

LPFCHR

6�0

UV (chroma) low pass filter selection
0 = bypass
96 = UV1 (<06>CYCHR1=0, <06>CYCHR2=0)
97 = UV2 (<06>CYCHR1=0, <06>CYCHR2=0)
113 = UV3 (<06>CYCHR1=0, <06>CYCHR2=0)
125 = UV4 (<06>CYCHR1=0, <06>CYCHR2=0)
127 = UV5 (<06>CYCHR1=0, <06>CYCHR2=0)

CYCHR1

UV (chroma) low pass filter offset correction 1
0 = off
1 = on

CYCHR2

UV (chroma) low pass filter offset correction 2
0 = off
1 = on

C registers for DELAY2 (DL2)

PXSKWON

pixel skew correction (see section 2.5.)
0 = off
[note: delay adapted every field, see Fig. 2�15]
1 = on
[note: delay adapted every line, see Fig. 2�14]

DL2

7�0

delay adjust for RGB to YUV-path (see section 2.5.)
(0...255)*2 + 2 clocks delay to write DL2�FIFO if <17>PXSKWON = 1
(48...212) clocks delay to read DL2�FIFO if <17>PXSKWON = 0

C registers for DELAY1 (DL1)

SECAM

delay of digital YUVin (SECAM mode)
0 = see <10>DL1ON
1 = UV: 2 clocks, Y: 76 clocks (set <10>DL1ON = 0)

DL1ON

delay of digital YUVin (set <10>SECAM = 0)
0 = 2 clocks
1 = 80 clocks

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Function

Typical
Operation
Value

Bit No.
(LSB = 0)

Label

Sub-
Address
(decimal)

C registers for OUTPUT CONTROL

HALFOUT

Output drive duration
0 = output active a full clock cycle (only one IC on Picture Bus)
1 = output active half a clock cycle (more than one IC on Picture Bus)

AVODIS

disable AVO pin
0 = AVO pin is active
1 = AVO pin is tristate

PUDIS

disable pull-up transistors at GL, RC, and B output pins
0 = pull-up on (output is in push-pull mode)
1 = pull-up off (output is in open drain mode)

LOAD

2�0

adjust load of AVO, GL, RC, B and PRIO
(select lowest possible load to keep electromagnetic radiation
and noise at A/D-Converter low)

LOAD |

GL, RC, B, and AVO outputs

@PVDD = 5 Volt

@PVDD = 3.3 Volt

000 |

Load

100 pF I

Load

3.4mA| C

Load

50 pF I

Load

3.0mA

001 |

Load

55 pF

Load

2.3mA| C

Load

28 pF I

Load

1.5mA

010 |

Load

37 pF

Load

1.5mA| C

Load

20 pF I

Load

1.0mA

011 |

Load

28 pF

Load

1.2mA| C

Load

16 pF I

Load

0.8mA

100 |

Load

23 pF

Load

0.9mA| C

Load

12 pF I

Load

0.6mA

101 |

Load

18 pF

Load

0.7mA| C

Load

10 pF I

Load

0.5mA

110 |

Load

14 pF

Load

0.6mA| C

Load

8 pF

Load

0.4mA

111

| pins tristate

LOAD |

PRIO bus

000 |

SINK

12mA

001 |

SINK

12mA

010 |

SINK

9mA

011 |

SINK

9mA

100 |

SINK

6mA

101 |

SINK

6mA

110 |

SINK

3mA

111 |

SINK

3mA

NOTE:
Total C

LOAD

at pins GL, RC, B, AVO, and PRIO must not exceed 2 nF.

Load

= max. load capacitance for AVO

Load

= max. load capacitance for GL, RC, and B at push-pull mode

12C:<14> PUDIS = 0
I

Load

= max. sink current for GL, RC, and B at open drain mode

12C:<14> PUDIS = 1

ADVANCE INFORMATION

CIP 3250A

Micronas

Table 2�10: I

C-Bus operation, continued

Sub-
Address
(decimal)

Label

Bit No.
(LSB = 0)

Typical
Operation
Value

Function

C registers for SYNCHRONIZATION

NEGCLK

select active clockedge for inputs and outputs
0 = all inputs and outputs relate to rising edge at CLK input (DIGIT 3000)
1 = all inputs and outputs relate to falling edge at CLK input (DIGIT 2000)

SYNCSIM

HSYNC, VSYNC input
0 = FSY-/SKEW-protocol (see <17>D2KSYNC)
1 = HSYNC at FSY-pin, VSYNC at AVI-pin
(see also <07>FSYINV, <10>AVIINV)

D2KSYNC

sync protocol at FSY-pin
0 = DIGIT 3000 (FSY protocol)
AVI-Pin and FSY-Pin with trigger level at 1.2 Volt
1 = DIGIT 2000 (SKEW protocol)
AVI-Pin and FSY-Pin with Schmitt-Trigger characteristic

AVIINV

polarity of AVI signal
0 = vertical sync at falling edge of AVI (if <17>SYNCSIM = 1
1 = vertical sync at rising edge of AVI (if <17>SYNCSIM = 1)

FSYINV

polarity of FSY signal (see also <17>SYNCSIM)
0 = horizontal sync at falling edge of FSY (if <17>SYNCSIM = 1)
select always <07>FSYINV = 0 if <17>SYNCSIM = 0
1 = horizontal sync at rising edge of FSY (if <17>SYNCSIM = 1)

SYNCIN

UV (chroma) multiplex control of digital YUVin
0 = by AVI (active video in)
1 = by 72 bit data (DIGIT 2000)

SYNCOUT

UV (chroma) multiplex control of YUV output
0 = by AVO (active video out)
1 = by 72 bit data (DIGIT 2000)

P72BEN

72 bit data and clock bypass enable
0 = off
1 = on (DIGIT 2000)

Fig. 2�13: H-sync reference generation

FSY

H-sync

AVO

(delay/clocks see table)

H-sync delay in respect to falling edge of FSY/
SKEW (H-sync is derived from FSY/SKEW)

D2KSYNC

delay

SYNCSIM

<17>

(clocks)

<17>

<23>AVHSTRT + 11 � <22>AVPR clocks

Fig. 2�14: DL2-setup

(<17>PXSKWON = 1)

AVI

DL2-RD

H-sync

DL2-WR

(see Fig. 2�13)

<21>DL2*2 + 2 clocks

4 clocks
82 clocks

24 clocks
102 clocks

<10>DL1ON = 0
<10>DL1ON = 1

48..212 clocks

Fig. 2�15: DL2-reset during line 7

(<17>PXSKWON = 0)

DL2-reset

DL2-WR

DL2-RD

program delay
see <21>DL2

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3. Specifications

3.1. Outline Dimensions

1.2 x 45

�

16 x 1.27

= 20.32

0.1

�

0.1

�

24.2

0.1

�

+0.25

x 45

�

0.457

0.2

0.71

1.9 1.5

4.05

0.1

4.75

�

0.15

1.27

0.1

�

2.4

1.27

0.1

�

16 x 1.27

= 20.32

0.1

�

0.1

�

24.2

0.1

�

+0.2

2.4

Fig. 3�1:
68-Pin Plastic Leaded Chip Carrier Package
(PLCC68)
Weight approximately 4.8 g
Dimensions in mm

3.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram

DVSS = if not used, connect to DVSS
AVSS = connect to AVSS

Pin No.

Connection

Pin Name

Type

Short Description

PLCC
68-pin

(if not used)

DVSS

STANDBY

Standby connect to ground

OUT

Blue Output (MSB)

OUT

Blue Output

OUT

Blue Output

OUT

Blue Output

OUT

Blue Output

OUT

Blue Output

OUT

Blue Output

OUT

Blue Output (LSB)

GL7

OUT

Green/Luma Output (MSB)

GL6

OUT

Green/Luma Output

GL5

OUT

Green/Luma Output

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Short Description

Type

Pin Name

Connection

Pin No.

(if not used)

PLCC
68-pin

GL4

OUT

Green/Luma Output

GL3

OUT

Green/Luma Output

GL2

OUT

Green/Luma Output

GL1

OUT

Green/Luma Output

GL0

OUT

Green/Luma Output (LSB)

PVSS

SUPPLY

Pad Ground

PVDD

SUPPLY

Pad Supply Voltage +5 V/+3.3 V

RC7

OUT

Red/Chroma Output (MSB)

RC6

OUT

Red/Chroma Output

RC5

OUT

Red/Chroma Output

RC4

OUT

Red/Chroma Output

RC3

OUT

Red/Chroma Output

RC2

OUT

Red/Chroma Output

RC1

OUT

Red/Chroma Output

RC0

OUT

Red/Chroma Output (LSB)

AVO

OUT

Active Video Output

Supply +5 V

AVI

Active Video Input

Supply +5 V

FSY

Front Sync Input

SCL

IN/OUT

C Clock Input/Output

SDA

IN/OUT

C Data Input/Output

PRIO2

IN/OUT

Picture Bus Priority (MSB)

PRIO1

IN/OUT

Picture Bus Priority

PRIO0

IN/OUT

Picture Bus Priority (LSB)

DVSS

Chroma Input (LSB)

DVSS

Chroma Input

DVSS

Chroma Input

DVSS

Chroma Input

DVSS

Chroma Input

DVSS

Chroma Input

DVSS

Chroma Input

DVSS

Chroma Input (MSB)

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Short Description

Type

Pin Name

Connection

Pin No.

(if not used)

PLCC
68-pin

DVSS

Luma Input (LSB)

DVSS

Luma Input

DVSS

Luma Input

DVSS

Luma Input

DVSS

Luma Input

DVSS

Luma Input

DVSS

Luma Input

DVSS

Luma Input (MSB)

DVSS

SUPPLY

Digital Ground

DVDD

SUPPLY

Digital Supply Voltage +5 V

CLK

Main Clock Input

RESQ

Reset Input

DVSS

TMODE

Test Mode connect to ground

AVDD

SUPPLY

Analog Supply Voltage +5 V

AVSS

SUPPLY

Analog Ground

ADREF

Reference

External Capacitor

SUBSTRATE

�

Substrate connect to ground

AVSS

Fast Blank Input

AVSS

GNDFB

Ground Fast Blank

AVSS

Blue/U Input

AVSS

GNDBU

Ground Blue/U

AVSS

Green/Luma Input

AVSS

GNDGY

Ground Green/Luma

AVSS

Red/V Input

AVSS

GNDRV

Ground Red/V

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3.3. Pin Descriptions

Pin 1 � STANDBY Input (Fig. 3�2)
Via this input pin, the standby mode of the CIP 3250A is
enabled. A high level voltage switches all outputs to tris-
tate mode, and power consumption is significantly re-
duced. When the IC is returned to active mode, a reset
is generated internally. Connect to VSS if not used.

Pins 2 to 9 � B7 to B0 Blue Output (Fig.3�3 )
In a stand alone application, where the CIP 3250A
serves as an A/D-converter, these are the outputs for the
digital Blue signal (pure binary) or the digital U signal (2's
complement). Leave vacant if not used.

Pins 10 to 17 � GL7 to GL0 Green/Luma Output
(Fig.3�3 )
At these outputs, the digital luminance signal is received
in pure binary coded format for DIGIT 2000 and DIGIT
3000 applications. In a stand alone application, where
the CIP 3250A serves as an A/D-converter, these are
the outputs for the digital Green signal (pure binary) or
the digital luma signal (pure binary). Leave vacant if not
used.

Pin 18 � PVSS Output Pin Ground
This is the common ground connection of all output
stages and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 19 � PVDD Output Pin Supply +5 V / +3.3 V
This pin supplies all output stages and must be con-
nected to a positive supply voltage.
Note: The layout of the PCB must take into consideration
the need for a low-noise supply. A bypass capacitor has
to be connected between ground and PVDD
(see section 4. Application Circuit.

Pins 20 to 27 � RC7 to RC0 Red/Chroma Output
(Fig. 3�3 )
These are the outputs for the digital chroma signal in the
DIGIT 3000 system, where U and V are multiplexed
bytewise. In a DIGIT 2000 system, RC3 to RC0 and RC7
to RC4 carry the halfbyte (nibble) multiplex format. In a
stand alone application, where the CIP 3250A serves as
an AD-converter, these are the outputs for the digital
Red signal (pure binary) or the digital chroma V signal
(2's complement). Leave vacant if not used.

Pin 28 � AVO Active Video Output (Fig. 3�4)
This output provides the Active Video signal, which car-
ries information about the chroma multiplex in a DIGIT
3000 application and indicates valid video data at the
Luma/Chroma outputs. This signal is programmable via
I

C registers. Leave vacant if not used.

Pin 29 � AVI Active Video Input (Fig. 3�5)
In a DIGIT 2000 application, this input can be connected
to ground. In a DIGIT 3000 application, this input ex-
pects the DIGIT 3000 AVI signal. In a stand alone ap-
plication, this input expects the VSYNC vertical sync
pulse. Connect to ground if not used.

Pin 30 � FSY Front Sync Input (Fig. 3�5)
In a DIGIT 2000 application, this input pin expects the
DIGIT 2000 SKEW protocol. In a DIGIT 3000 applica-
tion, this input expects the DIGIT 3000 FSY protocol. In
a stand alone application, this input expects the HSYNC
horizontal sync pulse. Connect to ground if not used.

Pins 31 to 32 � SDA and SCL of I

C-Bus (Fig. 3�6)

These pins connect to the I

C bus, which takes over the

control of the CIP 3250A via the internal registers. The
SDA pin is the data input/output, and the SCL pin is the
clock input/output of I

C bus control interface. All regis-

ters are writeable (except address hex27) and readable.

Pins 33 to 35 � PRIO0 to PRIO2 Priority Bus (Fig. 3�7)
These pins connect to the Priority Bus of a DIGIT 3000
application. The Picture Bus Priority lines carry the digi-
tal priority selection signals. The priority interface allows
digital switching of up to 8 sources to the backend pro-
cessor. Switching for different sources is prioritized and
can be on a per pixel basis. In all other applications, they
must not be connected.

Pins 36 to 43 � C0 to C7 Chroma Input (Fig. 3�8)
These are the inputs for the digital chroma signal which
can be received in binary offset or 2's complement
coded format. In a DIGIT 2000 (4:1:1) system, C3 to C0
take the halfbyte (nibble) multiplex format. C7 to C4
have to be connected to ground. Within the DIGIT 3000
(4:2:2) system, U and V are multiplexed bytewise. Con-
nect to ground if not used.

Pins 44 to 51 � L0 to L7 Luma Input (Fig. 3�8)
These are the inputs for the digital luma signal which
must be in pure binary coded format. Connect to ground
if not used.

Pin 52 � DVSS Digital Ground
This is the common ground connection of all digital
stages and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 53 � DVDD Digital Supply +5 V
This pin supplies all digital stages and must be con-
nected to a positive supply voltage.
Note: The layout of the PCB must take into consideration
the need for a low-noise supply. A bypass capacitor has
to be connected between ground and DVDD
(see section 4. Application Circuit.

Pin 54 � CLK Main Clock Input (Fig. 3�9)
This is the input for the clock signal. The frequency can
vary in the range from 13.5 MHz to 20.25 MHz.

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Pin 55 � RESQ Input (Fig. 3�10)
A low signal at this input pin generates a reset. The low-
to-high transition of this signal should occur when the
supply voltage is stable (power-on reset).

Pin 56 � TMODE Input (Fig. 3�2)
This pin is for test purposes only and must be connected
to ground in normal operation.

Pin 57 � AVDD Analog Supply +5 V
This is the supply voltage pin for the A/D converters and
must be connected to a positive supply voltage.
Note: The layout of the PCB must take into consideration
the need for a low-noise supply. A bypass capacitor has
to be connected between ground and AVDD.

Pin 58 � AVSS Analog Ground
This is the ground pin for the A/D converters and must
be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 59 � ADREF Connect External Capacitor (Fig. 3�11)
This pin should be connected to ground over a 10

�

F and

a 100 nF capacitor in parallel.

Pin 60 � SUBSTRATE
This is connected to the platform which carries the "die"
and must be connected to the ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 61 � FB Analog Fast Blank Input (Fig. 3�12)
This input takes the DC-coupled analog Fast Blank sig-
nal. The amplitude is 1.0 V maximum at 75 Ohms. Con-
nect to ground if not used.

Pin 62 � GNDFB Analog Ground
This is the ground pin for the AD converter of the Fast
Blank signal and has to be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 63 � BU Analog Blue/U Chroma Input (Fig. 3�13)
This input pin takes the AC-coupled analog component
signal Blue or U Chroma. The amplitude is 1.0 V maxi-
mum at 75 Ohms and a coupling capacitor of 220 nF. In-
ternally, the DC-offset of the input signal is adjusted via
the programmable internal clamping circuit. Connect to
ground if not used.

Pin 64 � GNDBU Analog Ground
This is the ground pin for the A/D converter of the Blue
or U Chroma signal and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 65 � GY Analog Green/Luma Input (Fig. 3�13)
This input pin takes the AC-coupled analog component
signal Green or Luma. The amplitude is 1.0 V maximum
at 75 Ohms and a coupling capacitor of 220 nF. Inter-
nally, the DC-offset of the input signal is adjusted via the
programmable internal clamping circuit. Connect to
ground if not used.

Pin 66 � GNDGY Analog Ground
This is the ground pin for the A/D converter of the Green
or Luma signal and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

Pin 67 � RV Analog Red/V Chroma Input (Fig. 3�13)
This input pin takes the AC-coupled analog component
signal Red or V Chroma. The amplitude is 1.0 V maxi-
mum at 75 Ohms and a coupling capacitor of 220 nF. In-
ternally, the DC-offset of the input signal is adjusted via
the programmable internal clamping circuit. Connect to
ground if not used.

Pin 68 � GNDRV Analog Ground
This is the ground pin for the A/D converter of the Red
or V Chroma signal and must be connected to ground.
Note: All ground pins of the chip (i.e. 18, 52, 58, 60, 62,
64, 66, and 68) must be connected together low resis-
tive. The layout of the PCB must take into consideration
the need for a low-noise ground.

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3.6. Electrical Characteristics

3.6.1. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

Unit

Ambient Temperature

�

Storage Temperature

�40

125

�

SUP

Supply Voltage, all Supply Inputs

�0.3

Input Voltage, all Inputs

�0.3

SUP

+0.3

Output Voltage, at Outputs
PRIO, SDA, and SCL

�0.3

SUP

+0.3

Output Voltage, at Outputs
GL, RC, B, and AVO

�0.3

EXT

+0.3

Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
"Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maxi-
mum ratings conditions for extended periods may affect device reliability.

3.6.2. Recommended Operating Conditions

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Ambient Operating Temperature

�

SUP

Supply Voltages Analog and Digital

DVDD, AVDD

4.75

5.0

5.25

EXT

Supply Voltages Output Circuits

PVDD

3.1

3.3

5.25

MCLK

Clock Frequency

CLK

13.50

�

20.25

MHz

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3.6.3. Characteristics
at T

= 0 to 65

�

C, V

SUP

= 4.75 to 5.25 V, V

EXT

= 3.1 to 5.25 V, f = 13.5 to 20.25 MHz for min./max.-values

at T

= 20

�

C, V

SUP

= 5 V, V

EXT

= 3.3 V, f = 20.25 MHz for typical values

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

DIG

Current Consumption Digital

DVDD

C:<06>D2KIN = 1

70 pF load at all outputs

ANA

Current Consumption Analog

AVDD

EXT

Current Consumption Picture-
Bus

PVDD

70 pF load at all outputs

TOT

Total Power Dissipation

950

C:<06>D2KIN = 1

70 pF load at all outputs

SDTBY

Standby Current Consumption

DVDD,
AVDD,
PVDD

tbd

Standby pin = high

Leakage Current

L[7...0],
C[7...0],
RC[7...0],
GL[7...0],
B[7...0],
PRIO[2:0],
SDA,
SCL,
FSY,
AVI

�

Standby pin = high
Uin = 0 V/5 V

Input Capacitance

AVI,
CLK,
RESQ,
TMODE,
AVO,
STANDBY,
RV,
GY,
BU,
FB

at DC = 0 V, AC = 100 mV
f = 10 MHz

3.6.3.1. Characteristics Standby Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

STANDBY

�

0.8

Input High Voltage

2.0

�

3.6.3.2. Characteristics Test Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

TMODE

�

0.8

Input High Voltage

2.0

�

3.6.3.3. Characteristics Reset Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

RESQ

�

1.3

Input High Voltage

3.3

�

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3.6.3.4. Characteristics Main Clock Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

MIDC

M Main Clock Input DC Voltage

CLK

1.5

�

3.5

MIAC

M Main Clock Input

AC Voltage (p�p)

0.8

�

2.5

MIH

MIL

M Clock Input

High to Low Ratio

2
3

1
1

3
2

MIHL

M Clock Input

High to Low Transition Time

�

0.15
f

MILH

M Clock Input

Low to High Transition Time

�

0.15
f

CLK Input

0 V

MIDC

MIAC

MIHL

MIH

MIL

MILH

Fig. 3�14: Main clock input

3.6.3.5. Characteristics Active Video Output

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Output Low Voltage

AVO

�

0.4

Load as described at
I

C:<14>LOAD

Output High Voltage

2.4

�

Load as described at
I

C:<14>LOAD

Output Delay TIme after
active Clock Transition

�

Load as described at
I

C:<14>LOAD

Output Hold Time after
active Clock Transition

�

AVO Output

CLK Input

Fig. 3�15: Active video output

Note: active clock edge depends on I

C:<17>NEGCLK

see NOTE

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3.6.3.6. Characteristics Active Video Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

AVI

�
�

1.3
0.8

V
V

C:<17>D2KSYNC = 1

C:<17>D2KSYNC = 0

Input High Voltage

3.3
1.5

�
�

V
V

C:<17>D2KSYNC = 1

C:<17>D2KSYNC = 0

Input Setup Time before
active Clock Transition

�

Input Hold Time after
active Clock Transition

�

AVI Input

CLK Input

Data valid

Fig. 3�16: Active video input

Note: active clock edge depends on I

C:<17>NEGCLK

see NOTE

3.6.3.7. Characteristics Fsync Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

FSY

�
�

1.3
0.8

V
V

C: D2KSYNC = 1

C: D2KSYNC = 0

Input High Voltage

3.3
1.5

�
�

V
V

C: D2KSYNC = 1

C: D2KSYNC = 0

Input Setup TIme before
active Clock Transition

�

Input Hold Time after active
active Clock Transition

�

FSY Input

CLK Input

Data valid

Fig. 3�17: Fsync input

Note: active clock edge depends on I

C:<17>NEGCLK

see NOTE

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3.6.3.8. Characteristics I

C Bus Interface Input/Output

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

SDA,
SCL

�

0.3*V

Input High Voltage

SCL

0.6*V

�

Output Low Voltage

�

0.4
0.6

V
V

= 3 mA

= 6 mA

Signal Fall Time

�

300

= 400 pF

SCL

Clock Frequency

SCL

�

400

kHz

I2C3

C-Clock Low Pulse Time

500

�

I2C4

C-Clock High Pulse Time

500

�

I2C1

C Start Condition Setup Time

SCL,
SDA

120

�

I2C2

C Stop Condition Setup Time

SDA

120

�

I2C5

C-Data Setup Time Before

Rising Edge of Clock SCL

�

I2C6

C-Data Hold Time after

Falling Edge of Clock SCL

�

I2C7

C-Slew Times at

C-Clock = 1 MHz

�

3.6.3.9. Characteristics Luma/Chroma Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

L[7..0],
C[7 0]

�

0.8

Input High Voltage

C[7..0]

1.5

�

PUP

Pullup Current

1.5
�

2.1
�

3.0

�

@ 1 Volt / I

C:<06>D2KIN = 1

@ 1 Volt / I

C:<06>D2KIN = 0

PUP

Pullup Voltage

1.8
�

�
�

3.2
�

V
V

C:<06>D2KIN = 1

C:<06>D2KIN = 0

Input Setup Time before
active Clock Transition

�

Input Hold Time after
actice Clock Transition

�

L/C Input

CLK Input

Data valid

Fig. 3�18: Luma/chroma input

Note: active clock edge depends on I

C:<17>NEGCLK

see NOTE

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3.6.3.10. Characteristics Priority Input/Output

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

Input Low Voltage

PRIO[2...0]

�

0.8

Input High Voltage

1.5

�

Output Low Voltage

�

0.6

Load as described at
I

C:<14>LOAD

PUP

Pullup Current

1.2

�

2.0

@ 1 Volt

PUP

Pullup Voltage

1.8

2.0

2.5

Input Setup Time before
active Clock Transition

�

Input Hold Time after
active Clock Transition

�

Output Delay Time after
active Clock Transition

�

Load as described at
I

C:<14>LOAD

Output Hold Time after
active Clock Transition

�

OHL

Output Low Hold Time after
active Clock Transition

�

PRIO Input

CLK Input

Data valid

PRIO Output

PUP

OHL

Data valid

Fig. 3�19: Priority input/output

Note: active clock edge depends on I

C:<17>NEGCLK

see NOTE

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3.6.3.12. Characteristics Analog R, G, B Inputs

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

VRT

Reference Voltage Top

ADREF

2.4

2.6

2.8

�

F/10 nF, 1G

Probe

C: <14>LOAD = 3

RGB � Path

VIN

Input Resistance

RV
GY

Code Clamp�DAC=0

VIN

Input Capacitance

GY
BU

4.5

VIN

Full Scale Input Voltage

0.85

1.0

1.1

Full Scale 0 ... 255

VINCL

Input Clamping Level,
UV for Binary Code 128

1.5

Binary Level = 128 LSB

VINCL

Input Clamping Level,
RGB, Y for Binary Code 16

1.06

Binary Level = 16 LSB

Gain Match

tbd

Full Scale @ 1 MHz

Clamping DAC Resolution

�32

steps

6 Bit � I�DAC, bipolar
V

VIN

=1 5 V

CL�LSB

Input Clamping Current per step

0.59

0.85

1.11

�

VIN

=1.5 V

INL

ICL

Clamping DAC Integral
Non-Linearity

0.5

LSB

ICL

Clamping�Capacitor

�

220

�

Coupling�Cap. @ Inputs

Dynamic Characteristics for RGB�Path
at V

EXT

= 3.3 V, 70 pF load at all outputs, I

C: <14>LOAD = 0

Bandwidth

RV
GY

MHz

�2 dBr input signal pegel

XTALK

Crosstalk, any Two Video Inputs

GY
BU

�42

�tbd

1 MHz, �2 dBr signal pegel

THD

Total Harmonic Distortion

�42

�tbd

1 MHz, 5 harmonics,
�2 dBr signal pegel

SINAD

Signal to Noise and Distortion
Ratio

tbd

1 MHz, all outputs,
�2 dBr signal pegel

INL

Integral Non-Linearity,

�

4.0

LSB

Code Density,
DC ramp

DNL

Differential Non-Linearity

�

1.0

LSB

DC�ramp

3.6.3.13. Characteristics Analog FBL Input

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

FBIN

Input Resistance

�

FBIN

Full Scale Input Voltage

0.85

1.0

1.1

Full Scale 0 ... 63

Threshold for FBL�Monitor

0.5

0.65

0.8

Dynamic Characteristics for FBL Input
at V

EXT

= 3.3 V, 70 pF load at all outputs, I

C: <14>LOAD = 0

Bandwidth

MHz

�2 dBr input signal pegel

THD

Total Harmonic Distortion

�38

�tbd

1 MHz, 5 harmonics,
�2 dBr signal pegel

SINAD

Signal to Noise and Distortion
Ratio

tbd

�36

1 MHz, all outputs,
�2 dBr signal pegel

ADVANCE INFORMATION

CIP 3250A

Micronas

5. Data Sheet History

1. Advance Information: "CIP 3250 Component Inter-
face Processor", May 2, 1995, 6251-403-1AI.
First release of the advance information.

2. Advance Information: "CIP 3250A Component Inter-
face Processor", Feb. 16, 1996, 6251-403-2AI.
Second release of the advance information.
Major changes:

� Modifications and new features from CIP 3250 to

CIP 3250A

� Fig. 3�1: PLCC68 package dimensions changed

� section 3.2.: Pin Connections and Short Descriptions

new

� Correction of errors

3. Advance Information: "CIP 3250A Component Inter-
face Processor", Oct. 9, 1996, 6251-403-3AI.
Third release of the advance information.
Major changes:

� section 2.7.: Modified description of Soft Mixer and

Fast Blank Monitor, Fig. 2�4: Fast Blank Processing
changed, Fig. 2�5: Fast Blank Monitor, Fig. 2�6: DIGIT
2000 skew data and Fig. 2�7: DIGIT 3000 front sync
format new

� section 2.9.: Table 2�2: Digital input selection new

� section 2.12.: Table 2�3: Digital output selection new

� section 2.16.: Table 2�10 modified and description of

<04>CLSEL changed; Fig. 2�14: DL2-setup and
Fig 2�15: DL2-reset during line 7 changed

� section 3.6.3.12. and 3.6.3.13.: new characteristics

� section 4.: Application Circuit new

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com

Printed in Germany
Order No. 6251-403-3AI

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirma-
tion form; the same applies to orders based on development samples
delivered. By this publication, Micronas GmbH does not assume re-
sponsibility for patent infringements or other rights of third parties
which may result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on
a retrieval system, or transmitted without the express written consent
of Micronas GmbH.

Электронный компонент: CIP3250A