DDP 3315C

ADVANCE INFORMATION

Micronas

Contents

Page

Section

Title

Introduction

1.1.

System Architecture

1.2.

System Application

Functional Description

2.1.

Display Part

2.1.1.

Digital Input Interface

2.1.2.

Chroma Input

2.1.3.

Horizontal Scaler

2.1.4.

Luma Contrast and Brightness

2.1.5.

Black Level Expander/Compressor (BLEC)

2.1.6.

Luma Sharpness Enhancer (LSE)

2.1.6.1.

Dynamic Peaking

2.1.6.2.

Luma Transient Improvement (LTI)

2.1.7.

Chroma Interpolation

2.1.8.

Chroma Transient Improvement

2.1.9.

Inverse Matrix and Digital RGB Processing

2.1.10.

Picture Frame Generator

2.1.11.

Scan Velocity Modulation

2.1.12.

Non-linear Colorspace Enhancer (NCE)

2.2.

Analog Back End

2.2.1.

Analog RGB Insertion

2.2.2.

Fast Blank Monitor

2.2.3.

Half Contrast Control

2.2.4.

CRT Measurement and Control

2.2.5.

Average Beam Current Limiter

2.3.

Synchronization and Deflection

2.3.1.

Deflection Processing

2.3.2.

Security Unit for H-Drive

2.3.3.

Horizontal Phase Adjustment

2.3.4.

Vertical Synchronization

2.3.5.

Vertical and East/West Deflection

2.3.6.

Vertical Zoom

2.3.7.

EHT Compensation

2.3.8.

Protection Circuitry

2.3.9.

Display Frequency Doubling

2.3.10.

General Purpose D/A Converter

2.3.11.

Clock and Reset

2.3.12.

Reset and Power-On

Serial Interface

3.1.

C-Bus Interface

3.2.

C Control and Status Registers

3.3.

XDFP Control and Status Registers

3.3.1.

Scaler Adjustment

Contents, continued

Page

Section

Title

ADVANCE INFORMATION

DDP 3315C

Micronas

Specifications

4.1.

Outline Dimensions

4.2.

Pin Connections and Short Descriptions

4.3.

Pin Descriptions

4.4.

Pin Configuration

4.5.

Pin Circuits

4.6.

Electrical Characteristics

4.6.1.

Absolute Maximum Ratings

4.6.2.

Recommended Operating Conditions

4.6.3.

Recommended Crystal Characteristics

4.6.4.

Characteristics

4.6.4.1.

General Characteristics

4.6.4.2.

LLC2: Line-locked Clock Input

4.6.4.3.

Luma, Chroma Inputs

4.6.4.4.

Digital Inputs, Static Pins

4.6.4.5.

C-Bus Interface

4.6.4.6.

Horizontal Flyback Input

4.6.4.7.

Sync Signals and PWM Outputs

4.6.4.8.

Horizontal Drive Output

4.6.4.9.

Vertical Protection Input

4.6.4.10.

Horizontal Safety Input

4.6.4.11.

Vertical and East/West D/A Converter Output

4.6.4.12.

East/West PWM Output

4.6.4.13.

Sense A/D Converter Input

4.6.4.14.

Analog RGB / YPBPR and FB Inputs

4.6.4.15.

Analog RGB Outputs, D/A Converters

4.6.4.16.

Scan Velocity Modulation Output

4.6.4.17.

DAC Reference, Beam Current Safety

Application Circuit

Data Sheet History

DDP 3315C

ADVANCE INFORMATION

Micronas

DDP 3315C
Display and Deflection Processor

1. Introduction

The DDP 3315C is a mixed-signal single-chip digital
display and deflection processor, designed for high-
quality backend applications in double scan and HDTV
TV sets with 4:3 or 16:9 picture tubes. The interfaces
qualify the IC to be combined with state of the art digi-
tal scan rate converters, as well as analog HDTV
sources. The DDP 3315C contains the entire digital
video component, deflection processing, and all ana-
log interfaces to display the picture on a CRT. The
main features are

Video Processing

� linear horizontal scaling (0.25 ... 4), as well as

nonlinear horizontal scaling "panorama vision"

� dynamic black level expander

� luma sharpness enhancement by dynamic peaking

and luma transient improvement (LTI)

� color transient improvement (CTI)

� programmable RGB matrix

� black stretch, blue stretch, gamma correction via

programmable Non-linear Colorspace Enhancer
(NCE) on RGB

� two analog double scan inputs with fast blank (one

RGB and one RGB/YC

/YP

selectable)

� average and peak beam current limiter

� automatic picture tube adjustment (cutoff, drive)

Deflection Processing

� scan velocity modulation output

� digital EHT compensation for vertical / east-west

� vertical angle and bow correction

� differential vertical outputs

� vertical zoom via deflection adjustment

� horizontal and vertical protection circuit

� horizontal frequency for VGA/SVGA/1080I

� black switch off procedure

� supports horizontal and vertical dynamic focus

Miscellaneous

� selectable ITU-R 601 4:1:1 / 4:2:2 YC

input at

27/32 MHz or double scan ITU-R 656 input at
54 MHz line-locked clock

� crystal oscillator for horizontal safety

� picture frame generator

� hardware for simple 50/60 Hz to 100/120 Hz con-

version (display frequency doubling)

� PQFP80 package, 5 V analog and 3.3 V digital sup-

ply

Fig. 1�1: Block diagram of the DDP 3315C

E/W

SVM

Y
P

FBL

Input

LLC
27/32/
54 MHz

R
G
B

Y
C

Output

Y /
656 YC

4:2:2 /
4:1:1

Sense
Input

E/W

VERT+
VERT

HOUT

SDA
SCL

PWM 1/2

2H / 2V

(1H / 1V)

FIFO

Controlling

HFLB

DFVBL

PWMV

VPROT

HSAFETY

Clock

Genera-

tor

SVM

Input

Interface

Upcon-
version /
scaling

Picture

Improve-

ment

Matrix /

PFG /

NCE

Video

DAC

analog

RGB-

Matrix

Analog

RGB

Switch

Tube

Control

H&V

Security

Unit

H/V

dynamic

focus

Sawtooth /

Parabola

Generation

H-Drive

Generation

Display-

Freq.

Doubling

EHT

Sync

Pro-

cessing

Interface

general

purpose

PWM

ADVANCE INFORMATION

DDP 3315C

Micronas

1.1. System Architecture

Fig. 1�1 shows the block diagram of the DDP 3315C.

A clock generator converts different external line
locked clock rates to a common internal sample rate of
~40 MHz, in order to provide a higher horizontal reso-
lution. The input interface accepts ITU-R 601 at 27 or
32 MHz and ITU-R 656 with encoded or external sync
at 54 MHz. The horizontal scaler is used for the scan
rate conversion and for the nonlinear aspect ratio con-
version as well.

For the picture improvement, luma and chroma are
processed separately. The luminance contrast ratio
can be extended with a dynamic black level expander.
In addition the frequency characteristic is improved by
a transient improvement (LTI) and an adaptive
dynamic peaking circuit. The peaking adapts to small
AC amplitudes of high frequency parts, while large AC
amplitudes are processed by the LTI. The chroma sig-
nal is enhanced with a transient improvement (CTI)
with proper limitation to avoid wrong colors.

The full programmable RGB matrix covers control of
color saturation and temperature. A digital white drive
control is used to adjust the white balance and for the
beam current limitation to prevent the CRT from over-
load. A non-linear colorspace enhancer (NCE) for
RGB gives full flexibility for any amplitude characteris-
tic.

High speed10-bit D/A converters are used to convert
digital RGB to analog signals. Separate 9-bit D/A con-
verters control brightness and cutoff. For picture tubes
equipped with an appropriate yoke a scan velocity
modulation (SVM) signal is calculated using a differen-
tiated luminance signal.

Two analog sources can be inserted in the main RGB,
controlled by separate fastblank (FBL) signals. Con-
trast and brightness are adjusted separately from main
RGB. One input is dedicated to RGB for on screen dis-

play (OSD). The second input is processed with an
analog RGB matrix to insert YC

/YP

or RGB with

control of color saturation and programmable half con-
trast. The bandwidth of ~30 MHz guarantees pixel
based graphics to be displayed with full accuracy.

All previously mentioned features are implemented in
dedicated hardware. An integrated processor controls
the horizontal and vertical deflection, tube measure-
ment loops and beam current limitation. It is also used
to calculate an amplitude histogram of the displayed
image.

The horizontal deflection is synchronized with two
numeric phase-locked loops (PLL) to the incoming
sync. One PLL generates the horizontal timing signals,
e.g. blanking and key-clamping. The second PLL
adjusts the phase of the horizontal drive pulse with a
subpixel accuracy less than 1 ns.

Vertical deflection and east/west correction waveforms
are calculated as 6th order polynomials. This allows
adjustment of an east/west parabola with trapezoidal,
pincushion and an upper/lower corner correction (even
for real flat CRT's), as well as a vertical sawtooth with
linearity and S-correction. Scaling both waveforms,
and limiting to fix amplitudes, performs a vertical zoom
or compression of the displayed image. A field and line
frequent control loop compensates picture content
depending EHT distortions.

1.2. System Application

To form a complete TV set, the video backend must be
complemented with additional components. Due to the
flexible architecture of the DDP, it can be placed in
various environments (see Fig. 1�2). Applications to
display digital MPEG or PC graphics on large screens,
inserting analog VGA sources in a TV as well as mem-
ory based image processing for 100/120 Hz or pro-
gressive scan rate conversion of TV sources, are
intended with the DDP.

Fig. 1�2: DDP 3315C applications

Combf

i
lt

16:

9 Vid

Line

flic

Sca

t
i
o

r
ess

ive

t
i
o

r
e

duc

tion

r V

sca

CVBS

VPC
323xD

CVBS

RGB

SDA
9400/1

DDP
3315C

RGB

H/V
Defl.

OSD, VGA, 1080l

VSP
940x

CVBS

RGB / VGA

DDP
3315C

RGB

H/V
Defl.

OSD, 1080l

Электронный компонент: DDP3315C

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