DRD 3515A
2
Micronas
Contents
Page
Section
Title
4
1.
Introduction
4
1.1.
Features of the DRD 3515A
4
1.2.
System Overview
6
2.
Functional Overview
6
2.1.
The WorldSpace Signal
6
2.2.
General Signal Flow
6
2.3.
Power Supply Concept
6
2.3.1.
Digital Power Supply
6
2.3.2.
Analog Power Supply of the IF Section and the Oscillator
6
2.3.3.
Performance of the Quartz Oscillator
6
2.3.4.
Analog Power Supplies for the Audio Parts
7
2.4.
IF Frontend
8
2.5.
QPSK Demodulator
8
2.6.
Frame Synchronization and Demultiplexing
8
2.6.1.
Synchronization to MFP and PRCP
8
2.6.2.
TSCC Acquisition
9
2.6.3.
TDM Demultiplexing: Selection of Broadcast Channel
9
2.7.
Viterbi and Reed-Solomon Decoding
9
2.8.
Broadcast Channel Output and Selection of an Additional Service Component
9
2.9.
Analog Audio
12
3.
Modes of Operation
12
3.1.
Interactions Between DRD 3515A and MAS 3506D
12
3.2.
Clock Concept
12
3.3.
Operation and Stand-By Modes
12
3.4.
Power Up Sequence (2 Battery Operation)
12
3.5.
Power Up Sequence (Operation Without DC/DC Converter)
13
3.6.
Power Down Sequence
13
3.6.1.
Full WorldSpace Operation
13
3.6.2.
Audio Amplifier Operation
13
3.6.3.
WorldSpace Operation Only
13
3.6.4.
Off
15
4.
Serial Control Interface
15
4.1.
I
2
C-Bus Interface
15
4.2.
Register Overview
18
4.3.
Detailed Description of the Registers
18
4.3.1.
Main Configuration Register GLB_CONFIG
19
4.3.2.
IF Input Configuration
19
4.3.3.
IF Input: Analog Automatic Gain Control
19
4.3.4.
QPSK Demodulator Carrier Frequency Offset
20
4.3.4.1.
QPSK Demodulator Receiving Quality Indicator
20
4.3.5.
QPSK Demodulator Timing Recovery Symbol Time.
21
4.3.6.
Analog Audio Gain
22
4.4.
Registers for Advanced Features
23
4.5.
FEC Registers
23
4.5.1.
Conventions for the Command Description
Contents, continued
Page
Section
Title
DRD 3515A
Micronas
3
23
4.5.2.
Detailed DRD 3515A Command Syntax
23
4.5.2.1.
Idle Mode
24
4.5.2.2.
TSCC Mode
24
4.5.2.3.
BC Mode
24
4.5.2.4.
MEM Read
24
4.5.2.5.
MEM Write
24
4.5.2.6.
Default Read
25
4.5.3.
Memory Table
26
4.5.4.
Standard Memory Cells
26
4.5.4.1.
Mute
26
4.5.4.2.
Test Mode for BER Measurements
26
4.5.4.3.
VMinDist
27
4.5.4.4.
Reed-Solomon Error Counter
27
4.5.4.5.
Service Component Output of the DRD 3515A
27
4.5.4.6.
TSCC Information
27
4.5.5.
Encryption Related Memory Cells
28
5.
Interface Specifications
28
5.1.
Broadcast Channel (BC) Interface
29
5.2.
Service Component Interface
29
5.3.
Serial Audio Data Interface
31
6.
Specifications
31
6.1.
Outline Dimensions
32
6.2.
Pin Connections and Short Descriptions
34
6.3.
Pin Descriptions
34
6.3.1.
Power Supply Pins
34
6.3.1.1.
IF-Related Pins
34
6.3.1.2.
Analog Audio Pins
35
6.3.1.3.
Oscillator and Clock Pins
35
6.3.1.4.
Digital Interface Section
35
6.3.1.5.
Other Pins
38
6.4.
Electrical Characteristics
38
6.4.1.
Absolute Maximum Ratings
39
6.4.2.
Recommended Operating Conditions
41
6.4.3.
Extended Operating Range
42
6.4.4.
Characteristics
48
7.
Application Notes
48
7.1.
Line Output Details
48
7.2.
Recommended Low Pass Filters for Analog Outputs
49
7.3.
Equivalent Output Circuitry in 3 Different Analog Modes
50
8.
Data Sheet History
DRD 3515A
4
Micronas
StarManTM Channel Decoder for a WorldSpaceTM
TDM Downlink Carrier
1. Introduction
The WorldSpace System is a satellite based digital
radio service for direct to home transmission of digital
radio programs to WorldSpace radios. The coverage
areas of this service are Africa, South America, and
parts of Asia.
The DRD 3515A is the part of Micronas' StarMan
chipset for demodulating and decoding the signals
from the WorldSpace satellites. It performs channel
demodulation, error correction, demultiplexing and the
separation of one Broadcast Channel (BC). The
DRD 3515A additionally provides an embedded stereo
D/A converter and an amplifier for headphones or a
small loudspeaker. Together with the audio decoder
MAS 3506D, a micro controller and an L-band tuner,
the DRD 3515A allows the design of compact and low
cost WorldSpace receivers.
1.1. Features of the DRD 3515A
Embedded 14.725 MHz crystal oscillator
Two-battery cell (with DC/DC converter on the
MAS 3506D) or three battery cell operation sup-
ported
IF input with AGC and RSSI
Digital I/Q splitting
Fast synchronization strategy
Crystal frequency offset compensation
Embedded signal quality indication
Demodulator status observable
Stored TSCC information available in BC-mode
Support of ES1 WorldSpace decrypting algorithm
Full Broadcast Channel (BC) output available
Optional serial output of one selected Service Com-
ponent (SC)
I
2
S input interface for decoded MPEG audio signals
Stereo D/A converter: S/N > 90 dB, THD < 0.01 %
Two auxiliary analog stereo inputs
Baseband audio source selector matrix
Stereo line output, amplifier for stereo headphones
or small mono speaker with click reduction
Various low power and stand-by functions
I
2
C controller interface
1.2. System Overview
The Micronas StarMan chip set consists of the channel
decoder DRD 3515A and the MPEG Layer 3 audio
decoder MAS 3506D. All essential analog and digital
building blocks for WorldSpace reception are provided
on the Micronas chipset. Together with an L-band
tuner and an appropriate controller this set builds a
complete StarMan radio receiver.
Fig. 11: Standard application of StarMan chipset
Since the DRD 3515A also contains an audio amplifier
for headphone or small loudspeaker operation, only a
minimum of external components are necessary. The
additional inputs for analog signals (e.g. conventional
AM/FM receiver, tape etc.) make the amplifier accessi-
ble to these audio sources and thus considerably sim-
plify the design of complete radio receivers.
The analog audio output of the WorldSpace signal can
be supplied to an external stereo amplifier for higher
power output. Also a digital audio signal in standard
I
2
S format is provided for high end applications that
may require an external D/A converter.
The complete WorldSpace Broadcast Channel (BC) is
available as a serial output signal from the DRD 3515A
and provides full access to all WorldSpace data by
additional decoder modules. The additional Service
Component (SC) output of the DRD 3515A may be
useful in applications where a data and an audio chan-
nel are transmitted simultaneously. In this case the
data component is directed to the SC output. The per-
formance requirements for the data decoders are con-
siderably lower for the Service Component because
the demultiplexing of the BC-channel is already done
inside the DRD 3515A. This function is independent
from the audio Service Component extraction in the
MAS 3506D.
Service Control Header data are available via I
2
C con-
troller interface from the MAS 3506D.
DRD 3515A
MAS 3506D
AM/FM
Receiver
Tape Player
MAS 3506D
DRD 3515A
WorldSpace
Tuner
Aux1/2
IF input
SC-out
analog out
BC
I
2
S
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