MAS 35xyH
PRELIMINARY DATA SHEET
2
Dec. 4, 2003; 6251-598-2PD
Micronas
Contents
Page
Section
Title
5
1.
Introduction
5
1.1.
Features
6
1.2.
TV System Application
7
1.3.
TV Application Details
9
2.
Functional Description
9
2.1.
Overview
9
2.2.
Architecture
9
2.3.
DSP Core
10
2.4.
Internal Program ROM and Firmware
10
2.5.
RAM and Registers
10
2.6.
Clock Management
11
2.7.
Interfaces
11
2.7.1.
I
2
C Control Interface
11
2.7.2.
S/PDIF Input Interfaces
11
2.7.3.
S/PDIF Output
11
2.7.4.
Serial Input Interface
11
2.7.4.1.
Multiline Serial Output
11
2.7.5.
Frame Synchronization
12
2.8.
Power-Supply Regions
12
2.9.
Functional Blocks and Operation
12
2.9.1.
Power-Up Sequence and Default Operation
12
2.9.2.
Input Switching
13
2.9.3.
Standard Selection and Decoding
13
2.9.4.
Dolby Digital Data Stream
13
2.9.5.
DTS (Digital Theater Systems) Data Stream
13
2.9.6.
MPEG Layer-2 Data Stream
14
2.9.7.
PCM Audio Data
14
2.9.8.
De-emphasis
14
2.9.9.
Dolby Pro Logic II Input Matrix
14
2.9.10.
Dolby Pro Logic II Decoder
14
2.9.10.1.
Major Operational Modes of Pro Logic II
15
2.9.10.2.
Additional Operational Modes
15
2.9.11.
Channel Expander
15
2.9.12.
Noise Generator
15
2.9.13.
Virtual Dolby Digital
16
2.9.14.
Post Processing/Bass Management
16
2.9.14.1.
Extra Stereo Output
16
2.9.14.2.
Digital Volume
16
2.9.14.3.
Bass Management
18
2.9.15.
Output Format Selection
18
2.9.16.
S/PDIF Loop-Through
18
2.9.17.
Output Sampling Rate
18
2.10.
System Interaction
18
2.10.1.
Minimum Required Interconnections
18
2.10.2.
Required Special Modes in the System
19
2.10.3.
Minimum System Set-Up
Contents, continued
Page
Section
Title
PRELIMINARY DATA SHEET
MAS 35xyH
Micronas
Dec. 4, 2003; 6251-598-2PD
3
20
3.
Control Interface
20
3.1.
Start-Up Sequence
20
3.2.
I
2
C Interface Access
20
3.2.1.
General
20
3.2.2.
I
2
C Registers and Subaddresses
20
3.2.3.
Conventions for the Command Description
21
3.2.4.
The Internal Fixed Point Number Format
21
3.3.
I
2
C Control Register (Code 6A
hex
)
21
3.4.
I
2
C Data Register (Codes 68
hex
and 69
hex
) and the MAS 35xyH DSP-Command Syntax
23
3.4.1.
Read Register (Code A
hex
)
23
3.4.2.
Write Register (Code B
hex
)
23
3.4.3.
Read Memory (Codes C
hex
and D
hex
)
23
3.4.4.
Short Read Memory (Codes C4
hex
and D4
hex
)
24
3.4.5.
Write Memory (Codes E
hex
and F
hex
)
24
3.4.6.
Short Write Memory (Codes E4
hex
and F4
hex
)
24
3.4.7.
Default Read
25
3.5.
Registers
27
3.6.
Special Memory Locations and User Interface
27
3.6.1.
Status Interface for Decoding
38
3.6.2.
Control Interface for Decoding Operation
49
3.6.3.
Hybrid User Interface Cells
51
4.
Specifications
51
4.1.
Outline Dimensions
53
4.2.
Pin Connections and Short Descriptions
56
4.3.
Pin Descriptions
56
4.3.1.
Power Supply Pins
56
4.3.2.
Control Lines
56
4.3.3.
General Purpose Input/Output
56
4.3.4.
Clocking
56
4.3.5.
Serial Input Interface
56
4.3.6.
S/PDIF Input Interface
56
4.3.7.
S/PDIF Output Interface
56
4.3.8.
Serial Output Interface
56
4.3.9.
Miscellaneous
57
4.4.
Pin Configurations
59
4.5.
Internal Pin Circuits
60
4.6.
Electrical Characteristics
60
4.6.1.
Absolute Maximum Ratings
61
4.6.2.
Recommended Operating Conditions
61
4.6.2.1.
General Recommended Operating Conditions
62
4.6.2.2.
Reference Frequency Generation and Crystal Recommendations
62
4.6.3.
Characteristics
62
4.6.3.1.
General Characteristics
63
4.6.3.2.
I
2
C Characteristics
64
4.6.3.3.
S/PDIF Bus Input Characteristics
65
4.6.3.4.
S/PDIF Bus Output Characteristics
MAS 35xyH
PRELIMINARY DATA SHEET
4
Dec. 4, 2003; 6251-598-2PD
Micronas
Contents, continued
Page
Section
Title
66
4.6.3.5.
I
2
S Bus Characteristics Input
67
4.6.3.6.
I
2
S Characteristics Output
68
4.6.4.
Firmware Characteristics
69
5.
Application
72
6.
Data Sheet History
License Notice:
DTS, DTS Digital Surround, and DTS Virtual 5.1 are trademarks and the "DTS" Logos are registered trademarks of
the Digital Theatre Systems Corporation.
"Dolby Digital", "Pro Logic
", and the double-D Symbol are trademarks of Dolby Laboratories. Supply of this imple-
mentation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial
or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-
use final product. Companies planning to use this implementation in products must obtain a license from Dolby Lab-
oratories Licensing Corporation before designing such products.
Spatializer
, Spatializer N-2-2`, and the circle-in-square device are trademarks of Desper Products, Inc.
PRELIMINARY DATA SHEET
MAS 35xyH
Micronas
Dec. 4, 2003; 6251-598-2PD
5
Audio Decoder IC Family
This data sheet applies to the MAS 35xyH family,
version C6, and to following versions.
Release Note: Revision bars indicate significant
changes to the previous edition.
1. Introduction
The Micronas MAS 35xyH family consists of ICs with
various combinations of DTS, Dolby Digital, Dolby
Pro Logic II and MPEG-1 Layer-2 decoders and Virtu-
alizer on a single chip. The family consists of the fol-
lowing members:
The MAS 35xyH decoder IC acts as a complete imple-
mentation of 5.1 DTS and Dolby Digital/Pro Logic II
decoders. On the chip's 8-channel output an Lt/Rt or
Lo/Ro downmix is available simultaneously to the mul-
tichannel audio for recording or headphone usage. All
necessary processing units, together with the I/O inter-
faces, have been integrated in a single 44-pin IC.
In a TV application, a two-chip solution of MAS 3527H
and MSP 44x0G results in a Virtual Dolby Digital Sys-
tem, whereas a multichannel audio TV uses
MAS 35xyH, MSP 44x0G and DPL 4519G. Due to the
scalable and flexible Micronas system solution, a sin-
gle hardware (PCB) solution, as well as a single TV
software solution, can be used to implement TV audio
systems from stereo only, via Virtual Dolby Digital, to
DTS/Dolby Digital multichannel audio.
In a consumer audio application, the MAS 35xyH,
completed by a standard audio codec and power
amplifiers, forms a 5.1 multichannel audio A/V ampli-
fier or receiver. The high integration level of
MAS 35xyH with its S/PDIF on chip, enables the
design of very economic 5.1 home audio sets.
1.1. Features
Two multiplexed S/PDIF, IEC-958, IEC 61937, AES/
EBU, EIA-J CP-340 receivers
Two freely configurable multiplexed serial inputs
Decoders for 5.1 Dolby Digital (AC-3),
5.1 DTS, Dolby Pro Logic II and MPEG-1 Layer-2
Spatializer N-2-2 ULTRA as "Virtual Dolby Digital"-
compliant virtualizer
Handling of PCM input format
S/PDIF PCM output or loop-through for all inputs
Lt, Rt encoding or straight downmixing to two chan-
nels (Lo, Ro) simultaneously to 5.1 multichannel
output
Multichannel I
2
S output
(four stereo data lines or one 8-channel line)
Dynamic range compression
Karaoke downmixing
Delay for center (0
...
5 ms)
Delay for surround (two channels, 0
...
25 ms)
Bandpass-shaped/white-noise generator
Bass management according to Dolby specification
(output configuration 0, 1, 2, 3, and DVD) and "Bass
to Center"
I
2
C control
Table 11: MAS 35xyH family
Decoder
MAS35xyH Type
3527H
3529H
3530H
DTS
-
-
Dolby Digital
-
Pro Logic II
-
VDD (Virtual
Dolby Digital)
VDS (Virtual
Dolby Surround)
MPEG1 L2
N-2-2 ULTRA
optional
optional
optional
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