MSP 34x7G
Multistandard
Sound Processor Family
Edition March 5, 2001
6251-535-2PD
PRELIMINARY DATA SHEET
MICRONAS
MICRONAS
MSP 34x7G
PRELIMINARY DATA SHEET
2
Micronas
Contents
Page
Section
Title
5
1.
Introduction
6
1.1.
Features of the MSP 34x7G Family and Differences to MSPD
6
1.2.
MSP 34x7G Version List
7
1.3.
MSP 34x7G Versions and their Application Fields
8
2.
Functional Description
9
2.1.
Architecture of the MSP 34x7G Family
9
2.2.
Sound IF Processing
9
2.2.1.
Analog Sound IF Input
9
2.2.2.
Demodulator: Standards and Features
10
2.2.3.
Preprocessing of Demodulator Signals
10
2.2.4.
Automatic Sound Select
10
2.2.5.
Manual Mode
12
2.3.
Preprocessing for SCART
12
2.4.
Source Selection and Output Channel Matrix
12
2.5.
Audio Baseband Processing
12
2.5.1.
Automatic Volume Correction (AVC)
12
2.5.2.
Quasi-Peak Detector
13
2.6.
SCART Signal Routing
13
2.6.1.
SCART DSP In and SCART Out Select
13
2.6.2.
Stand-by Mode
13
2.7.
Digital Control I/O Pins and Status Change Indication
13
2.8.
Clock PLL Oscillator and Crystal Specifications
14
3.
Control Interface
14
3.1.
I
2
C Bus Interface
14
3.1.1.
Internal Hardware Error Handling
15
3.1.2.
Description of CONTROL Register
15
3.1.3.
Protocol Description
16
3.1.4.
Proposals for General MSP 34x7G I
2
C Telegrams
16
3.1.4.1.
Symbols
16
3.1.4.2.
Write Telegrams
16
3.1.4.3.
Read Telegrams
16
3.1.4.4.
Examples
16
3.2.
Start-Up Sequence: Power-Up and I
2
C-Controlling
16
3.3.
MSP 34x7G Programming Interface
16
3.3.1.
User Registers Overview
18
3.3.2.
Description of User Registers
19
3.3.2.1.
STANDARD SELECT Register
19
3.3.2.2.
Refresh of STANDARD SELECT Register
19
3.3.2.3.
STANDARD RESULT Register
21
3.3.2.4.
Write Registers on I
2
C Subaddress 10
hex
22
3.3.2.5.
Read Registers on I
2
C Subaddress 11
hex
23
3.3.2.6.
Write Registers on I
2
C Subaddress 12
hex
29
3.3.2.7.
Read Registers on I
2
C Subaddress 13
hex
30
3.4.
Programming Tips
30
3.5.
Examples of Minimum Initialization Codes
Contents, continued
Page
Section
Title
PRELIMINARY DATA SHEET
MSP 34x7G
Micronas
3
30
3.5.1.
B/G-FM (A2 or NICAM)
30
3.5.2.
BTSC-Stereo
30
3.5.3.
BTSC-SAP with SAP at Loudspeaker Channel
31
3.5.4.
FM-Stereo Radio
31
3.5.5.
Automatic Standard Detection
31
3.5.6.
Software Flow for Interrupt driven STATUS Check
33
4.
Specifications
33
4.1.
Outline Dimensions
34
4.2.
Pin Connections and Short Descriptions
36
4.3.
Pin Descriptions
38
4.4.
Pin Configurations
39
4.5.
Pin Circuits
41
4.6.
Electrical Characteristics
41
4.6.1.
Absolute Maximum Ratings
42
4.6.2.
Recommended Operating Conditions
42
4.6.2.1.
General Recommended Operating Conditions
42
4.6.2.2.
Analog Input and Output Recommendations
43
4.6.2.3.
Recommendations for Analog Sound IF Input Signal
44
4.6.2.4.
Crystal Recommendations
46
4.6.3.
Characteristics
46
4.6.3.1.
General Characteristics
47
4.6.3.2.
Digital Inputs, Digital Outputs
48
4.6.3.3.
Reset Input and Power-Up
49
4.6.3.4.
I
2
C Bus Characteristics
50
4.6.3.5.
Analog Baseband Inputs and Outputs, AGNDC
51
4.6.3.6.
Sound IF Input
51
4.6.3.7.
Power Supply Rejection
52
4.6.3.8.
Analog Performance
53
4.6.3.9.
Sound Standard Dependent Characteristics
57
5.
Appendix A: Overview of TV Sound Standards
57
5.1.
NICAM 728
58
5.2.
A2 Systems
59
5.3.
BTSC-Sound System
59
5.4.
Japanese FM Stereo System (EIA-J)
60
5.5.
FM Satellite Sound
60
5.6.
FM-Stereo Radio
61
6.
Appendix B: Manual/Compatibility Mode
61
6.1.
Demodulator Write and Read Registers for Manual/Compatibility Mode
62
6.2.
DSP Write and Read Registers for Manual/Compatibility Mode
63
6.3.
Manual/Compatibility Mode: Description of Demodulator Write Registers
63
6.3.1.
Automatic Switching between NICAM and Analog Sound
63
6.3.1.1.
Function in Automatic Sound Select Mode
63
6.3.1.2.
Function in Manual Mode
65
6.3.2.
A2 Threshold
65
6.3.3.
Carrier-Mute Threshold
MSP 34x7G
PRELIMINARY DATA SHEET
4
Micronas
Contents, continued
Page
Section
Title
66
6.3.4.
Register AD_CV
68
6.3.5.
Register MODE_REG
69
6.3.6.
FIR-Parameter, Registers FIR1 and FIR2
69
6.3.7.
DCO-Registers
71
6.4.
Manual/Compatibility Mode: Description of Demodulator Read Registers
71
6.4.1.
NICAM Mode Control/Additional Data Bits Register
71
6.4.2.
Additional Data Bits Register
71
6.4.3.
CIB Bits Register
72
6.4.4.
NICAM Error Rate Register
72
6.4.5.
PLL_CAPS Readback Register
72
6.4.6.
AGC_GAIN Readback Register
72
6.4.7.
Automatic Search Function for FM-Carrier Detection in Satellite Mode
73
6.5.
Manual/Compatibility Mode: Description of DSP Write Registers
73
6.5.1.
Additional Channel Matrix Modes
73
6.5.2.
Volume Modes of SCART1 Output
73
6.5.3.
FM Fixed Deemphasis
73
6.5.4.
FM Adaptive Deemphasis
73
6.5.5.
NICAM Deemphasis
74
6.5.6.
Identification Mode for A2 Stereo Systems
74
6.5.7.
FM DC Notch
74
6.6.
Manual/Compatibility Mode: Description of DSP Read Registers
74
6.6.1.
Stereo Detection Register for A2 Stereo Systems
74
6.6.2.
DC Level Register
75
6.7.
Demodulator Source Channels in Manual Mode
75
6.7.1.
Terrestric Sound Standards
75
6.7.2.
SAT Sound Standards
75
6.8.
Exclusions of Audio Baseband Features
75
6.9.
Compatibility Restrictions to MSP 34x7D
77
7.
Appendix D: Application Information
77
7.1.
Phase Relationship of Analog Outputs
78
7.2.
Application Circuit
80
8.
Appendix E: MSP 34x7G Version History
80
9.
Data Sheet History
License Notice:
"Dolby Pro Logic" is a trademark of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec-
tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
PRELIMINARY DATA SHEET
MSP 34x7G
Micronas
5
Multistandard Sound Processor Family
Release Note: Revision bars indicate significant
changes to the previous edition. The hardware and
software description in this document is valid for
the MSP 34x7G version B8 and following versions.
1. Introduction
The MSP 34x7G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to pro-
cessed analog AF-out, is performed in a single chip.
Figure 11 shows a simplified functional block diagram
of the MSP 34x7G.
These TV sound processing ICs include versions for
processing the multichannel television sound (MTS)
signal conforming to the standard recommended by
the Broadcast Television Systems Committee (BTSC).
The DBX noise reduction, or alternatively, Micronas
Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM-Stereo-Radio
standard.
Current ICs have to perform adjustment procedures in
order to achieve good stereo separation for BTSC and
EIA-J. The MSP 34x7G has optimum stereo perfor-
mance without any adjustments.
All MSP 34xxG versions are pin compatible to the
MSP 34xxD. Only minor modifications are necessary
to adapt a MSP 34xxD controlling software to the
MSP 34xxG. The MSP 34x7G further simplifies con-
trolling software. Standard selection requires a single
I
2
C transmission only.
Note: The MSP 34x7G version has reduced control
registers and less functional pins. The remaining regis-
ters are software-compatible to the MSP 34x0G. The
pinning is compatible to the MSP 34x0G.
The MSP 34x7G has built-in automatic functions: The
IC is able to detect the actual sound standard automat-
ically (Automatic Standard Detection). Furthermore,
pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/
stereo/bilingual; no I
2
C interaction is necessary (Auto-
matic Sound Selection).
The MSP 34x7G can handle very high FM deviations
even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
China.
The ICs are produced in submicron CMOS technology.
The MSP 34x7G is available in the following packages:
PSDIP52 and PMQFP44.
Fig. 11: Simplified functional block diagram of MSP 34x7G
S
ource Sel
e
ct
Loud-
SCART1
SCART1
MONO
De-
modulator
speaker
Sound
Processing
DAC
ADC
Loud-
DAC
ADC
Sound IF1
speaker
Pre-
processing
Prescale
SCART
DSP
Input
Select
SCART
Output
Select
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