VDP 313xY
ADVANCE INFORMATION
2
Micronas
Contents
Page
Section
Title
5
1.
Introduction
5
1.1.
Features
5
1.2.
System Architecture
6
1.3.
Video Processor Family
7
2.
Functional Description
7
2.1.
Introduction
7
2.2.
Video Front End
7
2.2.1.
Input Selection
7
2.2.2.
Clamping
7
2.2.3.
Automatic Gain Control
7
2.2.4.
Analog-to-Digital Converters
7
2.2.5.
Digitally Controlled Clock Oscillator
8
2.3.
Adaptive Comb Filter
9
2.4.
Color Decoder
9
2.4.1.
IF-Compensation
10
2.4.2.
Demodulator
10
2.4.3.
Chrominance Filter
10
2.4.4.
Frequency Demodulator
10
2.4.5.
Burst Detection / Saturation Control
10
2.4.6.
Color Killer Operation
11
2.4.7.
Automatic standard recognition
11
2.4.8.
PAL Compensation/1-H Comb Filter
12
2.4.9.
Luminance Notch Filter
12
2.4.10.
Skew Filtering
13
2.5.
Horizontal Scaler
13
2.6.
Blackline Detector
13
2.7.
Test Pattern Generator
14
2.8.
Video Sync Processing
14
2.9.
Macrovision detection
15
2.10.
Display Part
15
2.10.1.
Luminance Contrast Adjustment
15
2.10.2.
Black Level Expander
16
2.10.3.
Dynamic Peaking
17
2.10.4.
Digital Brightness Adjustment
17
2.10.5.
Soft Limiter
17
2.10.6.
Chrominance Interpolation
18
2.10.7.
Chrominance Transient Improvement
18
2.10.8.
Inverse Matrix
18
2.10.9.
RGB Processing
18
2.10.10.
Picture Frame Generator
19
2.10.11.
Priority Decoder
19
2.10.12.
Scan Velocity Modulation
19
2.10.13.
Display Phase Shifter
21
2.11.
Video Back End
21
2.11.1.
CRT Measurement and Control
22
2.11.2.
SCART Output Signal
Contents, continued
Page
Section
Title
ADVANCE INFORMATION
VDP 313xY
Micronas
3
23
2.11.3.
Average Beam Current Limiter
23
2.11.4.
Analog RGB Insertion
24
2.11.5.
Fast Blank Monitor
24
2.11.6.
Half Contrast Control
24
2.11.7.
IO Port Expander
26
2.12.
Synchronization and Deflection
26
2.12.1.
Deflection Processing
27
2.12.2.
Angle & Bow Correction
27
2.12.3.
Horizontal Phase Adjustment
27
2.12.4.
Vertical and East/West Deflection
28
2.12.5.
EHT Compensation
28
2.12.6.
Protection Circuitry
28
2.13.
Reset and Power On
29
2.14.
Serial Interface
29
2.14.1.
I
2
C-Bus Interface
30
2.14.2.
Control and Status Registers
48
2.14.2.1.
Scaler Adjustment
51
2.14.2.2.
Calculation of Vertical and East-West Deflection Coefficients
52
3.
Specifications
52
3.1.
Outline Dimensions
52
3.2.
Pin Connections and Short Descriptions
55
3.3.
Pin Descriptions
56
3.4.
Pin Configuration
57
3.5.
Pin Circuits
59
3.6.
Electrical Characteristics
59
3.6.1.
Absolute Maximum Ratings
59
3.6.2.
Recommended Operating Conditions
60
3.6.2.1.
Analog Input and Output Recommendations
61
3.6.3.
Recommended Crystal Characteristics
62
3.6.4.
Characteristics
62
3.6.4.1.
General Characteristics
62
3.6.4.2.
I
2
C Bus Interface
62
3.6.4.3.
Reset Input
63
3.6.4.4.
Power-up Sequence
64
3.6.4.5.
Test Input
64
3.6.4.6.
Analog Video Front-End and A/D Converters
66
3.6.4.7.
Horizontal Flyback Input
66
3.6.4.8.
Horizontal Drive Output
66
3.6.4.9.
Vertical Protection Input
66
3.6.4.10.
Vertical Safety Input
67
3.6.4.11.
Vertical and East/West D/A Converter Output
67
3.6.4.12.
Combined Sync, Vertical Sync, Interlace and Front Sync Output
67
3.6.4.13.
CLK20 Output
67
3.6.4.14.
Sense A/D Converter Input
67
3.6.4.15.
Range Switch Output
68
3.6.4.16.
Scan Velocity Modulation Output
ADVANCE INFORMATION
VDP 313xY
Micronas
5
Video Processor Family
1. Introduction
The VDP 313xY is a video IC family of high-quality sin-
gle-chip video processors. Modular design and a sub-
micron technology allow the economic integration of
features in all classes of TV sets. The VDP 313xY fam-
ily is based on the VDP 31xxB including YC
R
C
B
inputs
for DVD component signals.
The main features of the VDP 3130Y are
1.1. Features
Video Decoding and Processing
four CVBS, one S-VHS input,
one YC
R
C
B
component input
integrated high-quality A/D converters and associ-
ated clamp and AGC circuits
adaptive 2H comb filter Y/C separator
multistandard color decoder PAL/NTSC/SECAM
including all substandards
multistandard sync decoder
automatic standard recognition
black-line detector
linear horizontal scaling (0.25...4), as well as nonlin-
ear horizontal scaling "Panoramavision"
black-level expander
dynamic peaking
soft limiter (gamma correction)
color transient improvement
RGB Processing and Deflection
programmable RGB matrix
two analog RGB / Fastblank inputs
half-contrast switch
picture frame generator
scan velocity modulation output
high-performance H/V deflection
separate ADC for tube measurements
EHT compensation
angle and bow correction
one 20.25 MHz crystal, few external components
I
2
C-Bus Interface
64-pin PSDIP package
1.2. System Architecture
Fig. 11 shows the block diagram of the video proces-
sor
Fig. 11: Block diagram of the VDP 313xY
SVM
RGB OUT
Half Contrast
RGB/FB IN2
RGB/FB IN1
Sync and Deflection
H/V/EW
I
2
C
I
2
C
Sense
VOUT
VIN4
VIN3
VIN2
VIN1
CBIN
CIN2/CRIN
CIN1
Analog
Frontend
AGC,
2
8 bit ADC
2H
Adaptive
Combfilter
Color
Decoder
NTSC,
PAL,
SECAM
Horizontal
Scaler
Panorama
Mode
Display
Processor
RGB Matrix,
CLUT,
Scan Veloc.
Analog
Backend
3
10 bit DAC,
Tube Control,
RGB Switch
20.
25
M
H
z
Clock Gen.
DCO
Measurement
ADC
PDF 
ZIP
